LLVM: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Source File (original) (raw)
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35#include
36#include
37#include
38
39using namespace llvm;
40
41#define DEBUG_TYPE "mccodeemitter"
42
43STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
44STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
45
46namespace {
47
51 bool IsLittleEndian;
52
53public:
55 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
56 }
57 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
58 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
59 ~ARMMCCodeEmitter() override = default;
60
61 bool isThumb(const MCSubtargetInfo &STI) const {
62 return STI.hasFeature(ARM::ModeThumb);
63 }
64
65 bool isThumb2(const MCSubtargetInfo &STI) const {
67 }
68
69 bool isTargetMachO(const MCSubtargetInfo &STI) const {
71 return TT.isOSBinFormatMachO();
72 }
73
74 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
75
76
77
78 uint64_t getBinaryCodeForInstr(const MCInst &MI,
79 SmallVectorImpl &Fixups,
80 const MCSubtargetInfo &STI) const;
81
82
83
84 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
85 SmallVectorImpl &Fixups,
86 const MCSubtargetInfo &STI) const;
87
88
89
90
91
92 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl &Fixups,
94 const MCSubtargetInfo &STI) const;
95
96 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
97 unsigned &Reg, unsigned &Imm,
98 SmallVectorImpl &Fixups,
99 const MCSubtargetInfo &STI) const;
100
101
102
103 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 SmallVectorImpl &Fixups,
105 const MCSubtargetInfo &STI) const;
106
107
108
109 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl &Fixups,
111 const MCSubtargetInfo &STI) const;
112
113
114 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl &Fixups,
116 const MCSubtargetInfo &STI) const;
117
118
119 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl &Fixups,
121 const MCSubtargetInfo &STI) const;
122
123
124 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl &Fixups,
126 const MCSubtargetInfo &STI) const;
127
128
129
131 SmallVectorImpl &Fixups,
132 const MCSubtargetInfo &STI) const;
133
134
135
136 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl &Fixups,
138 const MCSubtargetInfo &STI) const;
139
140
141
142 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl &Fixups,
144 const MCSubtargetInfo &STI) const;
145 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
146 SmallVectorImpl &Fixups,
147 const MCSubtargetInfo &STI) const;
148 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
149 SmallVectorImpl &Fixups,
150 const MCSubtargetInfo &STI) const;
151
152
153
154 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl &Fixups,
156 const MCSubtargetInfo &STI) const;
157 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
158 SmallVectorImpl &Fixups,
159 const MCSubtargetInfo &STI) const;
160 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
161 SmallVectorImpl &Fixups,
162 const MCSubtargetInfo &STI) const;
163
164 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
165 SmallVectorImpl &Fixups,
166 const MCSubtargetInfo &STI) const;
167
168
169
170 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
171 SmallVectorImpl &Fixups,
172 const MCSubtargetInfo &STI) const;
173
174
175
176 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
177 SmallVectorImpl &Fixups,
178 const MCSubtargetInfo &STI) const;
179
180
181 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
182 SmallVectorImpl &Fixups,
183 const MCSubtargetInfo &STI) const;
184
185
186
187 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
188 SmallVectorImpl &Fixups,
189 const MCSubtargetInfo &STI) const;
190
191
192
193 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
194 SmallVectorImpl &Fixups,
195 const MCSubtargetInfo &STI) const;
196
197
198
199 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
200 SmallVectorImpl &Fixups,
201 const MCSubtargetInfo &STI) const;
202
203
204
205 template<unsigned Bits, unsigned Shift>
206 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
207 SmallVectorImpl &Fixups,
208 const MCSubtargetInfo &STI) const;
209
210
211
212 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
213 SmallVectorImpl &Fixups,
214 const MCSubtargetInfo &STI) const;
215
216
217
218 template
219 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
220 SmallVectorImpl &Fixups,
221 const MCSubtargetInfo &STI) const;
222
223
224
225 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
226 SmallVectorImpl &Fixups,
227 const MCSubtargetInfo &STI) const;
228
229
230 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
231 SmallVectorImpl &Fixups,
232 const MCSubtargetInfo &STI) const {
234 switch (Mode) {
240 }
241 }
242
243
244
246 switch (ShOpc) {
253 default:
255 }
256 }
257
258
259 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
260 SmallVectorImpl &Fixups,
261 const MCSubtargetInfo &STI) const;
262
263
264 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
265 SmallVectorImpl &Fixups,
266 const MCSubtargetInfo &STI) const;
267
268
269 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
270 SmallVectorImpl &Fixups,
271 const MCSubtargetInfo &STI) const;
272
273
274 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
275 SmallVectorImpl &Fixups,
276 const MCSubtargetInfo &STI) const;
277
278
279
280 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
281 SmallVectorImpl &Fixups,
282 const MCSubtargetInfo &STI) const;
283
284
285 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
286 SmallVectorImpl &Fixups,
287 const MCSubtargetInfo &STI) const;
288
289
290 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
291 SmallVectorImpl &Fixups,
292 const MCSubtargetInfo &STI) const;
293
294
295 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
296 SmallVectorImpl &Fixups,
297 const MCSubtargetInfo &STI) const;
298
299
300 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
301 SmallVectorImpl &Fixups,
302 const MCSubtargetInfo &STI) const;
303
304
305 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
306 SmallVectorImpl &Fixups,
307 const MCSubtargetInfo &STI) const {
308
309
310 return MI.getOperand(Op).getReg() == ARM::CPSR;
311 }
312
313 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
314 SmallVectorImpl &Fixups,
315 const MCSubtargetInfo &ST) const;
316
317
318 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
319 SmallVectorImpl &Fixups,
320 const MCSubtargetInfo &STI) const;
321
322 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
323 SmallVectorImpl &Fixups,
324 const MCSubtargetInfo &STI) const;
325 template<unsigned Bits, unsigned Shift>
326 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
327 SmallVectorImpl &Fixups,
328 const MCSubtargetInfo &STI) const;
329 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
330 SmallVectorImpl &Fixups,
331 const MCSubtargetInfo &STI) const;
332
333
334 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
335 SmallVectorImpl &Fixups,
336 const MCSubtargetInfo &STI) const;
337 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
338 SmallVectorImpl &Fixups,
339 const MCSubtargetInfo &STI) const;
340 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
341 SmallVectorImpl &Fixups,
342 const MCSubtargetInfo &STI) const;
343
344 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
345 SmallVectorImpl &Fixups,
346 const MCSubtargetInfo &STI) const {
347 return 64 - MI.getOperand(Op).getImm();
348 }
349
350 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
351 SmallVectorImpl &Fixups,
352 const MCSubtargetInfo &STI) const;
353
354 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
355 SmallVectorImpl &Fixups,
356 const MCSubtargetInfo &STI) const;
357 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
358 SmallVectorImpl &Fixups,
359 const MCSubtargetInfo &STI) const;
360 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
361 SmallVectorImpl &Fixups,
362 const MCSubtargetInfo &STI) const;
363 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
364 SmallVectorImpl &Fixups,
365 const MCSubtargetInfo &STI) const;
366 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
367 SmallVectorImpl &Fixups,
368 const MCSubtargetInfo &STI) const;
369
370 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
371 SmallVectorImpl &Fixups,
372 const MCSubtargetInfo &STI) const;
373 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
374 SmallVectorImpl &Fixups,
375 const MCSubtargetInfo &STI) const;
376 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
377 SmallVectorImpl &Fixups,
378 const MCSubtargetInfo &STI) const;
379 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
380 SmallVectorImpl &Fixups,
381 const MCSubtargetInfo &STI) const;
382
383 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
384 SmallVectorImpl &Fixups,
385 const MCSubtargetInfo &STI) const;
386
387 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
388 unsigned EncodedValue,
389 const MCSubtargetInfo &STI) const;
390 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
391 unsigned EncodedValue,
392 const MCSubtargetInfo &STI) const;
393 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
394 unsigned EncodedValue,
395 const MCSubtargetInfo &STI) const;
396 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
397 unsigned EncodedValue,
398 const MCSubtargetInfo &STI) const;
399
400 unsigned VFPThumb2PostEncoder(const MCInst &MI,
401 unsigned EncodedValue,
402 const MCSubtargetInfo &STI) const;
403
404 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
405 SmallVectorImpl &Fixups,
406 const MCSubtargetInfo &STI) const;
407
408 void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB,
409 SmallVectorImpl &Fixups,
410 const MCSubtargetInfo &STI) const override;
411
412 template <bool isNeg, ARM::Fixups fixup>
413 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
414 SmallVectorImpl &Fixups,
415 const MCSubtargetInfo &STI) const;
416
417 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
418 SmallVectorImpl &Fixups,
419 const MCSubtargetInfo &STI) const;
420
421 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
422 SmallVectorImpl &Fixups,
423 const MCSubtargetInfo &STI) const;
424 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
425 SmallVectorImpl &Fixups,
426 const MCSubtargetInfo &STI) const;
427 template
428 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
429 SmallVectorImpl &Fixups,
430 const MCSubtargetInfo &STI) const;
431};
432
433}
434
437 bool PCRel = false;
438 switch (Kind) {
468 PCRel = true;
469 }
471}
472
473
474
475
476unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
477 unsigned EncodedValue,
479 if (isThumb2(STI)) {
480
481
482
483 unsigned Bit24 = EncodedValue & 0x01000000;
484 unsigned Bit28 = Bit24 << 4;
485 EncodedValue &= 0xEFFFFFFF;
486 EncodedValue |= Bit28;
487 EncodedValue |= 0x0F000000;
488 }
489
490 return EncodedValue;
491}
492
493
494
495
496unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
497 unsigned EncodedValue,
498 const MCSubtargetInfo &STI) const {
499 if (isThumb2(STI)) {
500 EncodedValue &= 0xF0FFFFFF;
501 EncodedValue |= 0x09000000;
502 }
503
504 return EncodedValue;
505}
506
507
508
509
510unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
511 unsigned EncodedValue,
512 const MCSubtargetInfo &STI) const {
513 if (isThumb2(STI)) {
514 EncodedValue &= 0x00FFFFFF;
515 EncodedValue |= 0xEE000000;
516 }
517
518 return EncodedValue;
519}
520
521
522
523unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
524 unsigned EncodedValue,
525 const MCSubtargetInfo &STI) const {
526 if (isThumb2(STI)) {
527 EncodedValue |= 0xC000000;
528 }
529
530 return EncodedValue;
531}
532
533
534
535unsigned ARMMCCodeEmitter::
536VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
537 const MCSubtargetInfo &STI) const {
538 if (isThumb2(STI)) {
539 EncodedValue &= 0x0FFFFFFF;
540 EncodedValue |= 0xE0000000;
541 }
542 return EncodedValue;
543}
544
545
546
547unsigned ARMMCCodeEmitter::
548getMachineOpValue(const MCInst &MI, const MCOperand &MO,
549 SmallVectorImpl &Fixups,
550 const MCSubtargetInfo &STI) const {
551 if (MO.isReg()) {
554
555
556
557
558
559
560
561 if (STI.hasFeature(ARM::HasMVEIntegerOps))
562 return RegNo;
563
565 default:
566 return RegNo;
567 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
568 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
569 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
570 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
571 return 2 * RegNo;
572 }
573 } else if (MO.isImm()) {
574 return static_cast<unsigned>(MO.getImm());
577 .bitcastToAPInt()
578 .getHiBits(32)
579 .getLimitedValue());
580 }
581
583}
584
585
586bool ARMMCCodeEmitter::
587EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
588 unsigned &Imm, SmallVectorImpl &Fixups,
589 const MCSubtargetInfo &STI) const {
590 const MCOperand &MO = MI.getOperand(OpIdx);
591 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
592
594
595 int32_t SImm = MO1.getImm();
596 bool isAdd = true;
597
598
599 if (SImm == INT32_MIN) {
600 SImm = 0;
601 isAdd = false;
602 }
603
604
605 if (SImm < 0) {
606 SImm = -SImm;
607 isAdd = false;
608 }
609
610 Imm = SImm;
611 return isAdd;
612}
613
614
615
621
622
624 assert(MO.isExpr() && "Unexpected branch target type!");
627 addFixup(Fixups, 0, Expr, Kind);
628
629
630 return 0;
631}
632
633
634
636 offset >>= 1;
637 uint32_t S = (offset & 0x800000) >> 23;
638 uint32_t J1 = (offset & 0x400000) >> 22;
639 uint32_t J2 = (offset & 0x200000) >> 21;
640 J1 = (~J1 & 0x1);
641 J2 = (~J2 & 0x1);
642 J1 ^= S;
643 J2 ^= S;
644
645 offset &= ~0x600000;
646 offset |= J1 << 22;
647 offset |= J2 << 21;
648
649 return offset;
650}
651
652
653uint32_t ARMMCCodeEmitter::
654getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
655 SmallVectorImpl &Fixups,
656 const MCSubtargetInfo &STI) const {
657 const MCOperand MO = MI.getOperand(OpIdx);
660 Fixups, STI);
662}
663
664
665
666uint32_t ARMMCCodeEmitter::
667getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
668 SmallVectorImpl &Fixups,
669 const MCSubtargetInfo &STI) const {
670 const MCOperand MO = MI.getOperand(OpIdx);
673 Fixups, STI);
675}
676
677
678uint32_t ARMMCCodeEmitter::
679getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
680 SmallVectorImpl &Fixups,
681 const MCSubtargetInfo &STI) const {
682 const MCOperand MO = MI.getOperand(OpIdx);
685 Fixups, STI);
686 return (MO.getImm() >> 1);
687}
688
689
690uint32_t ARMMCCodeEmitter::
691getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
692 SmallVectorImpl &Fixups,
693 const MCSubtargetInfo &STI) const {
694 const MCOperand MO = MI.getOperand(OpIdx);
697 Fixups, STI);
698 return (MO.getImm() >> 1);
699}
700
701
702uint32_t ARMMCCodeEmitter::
703getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
704 SmallVectorImpl &Fixups,
705 const MCSubtargetInfo &STI) const {
706 const MCOperand MO = MI.getOperand(OpIdx);
709 return (MO.getImm() >> 1);
710}
711
712
714 int NumOp = MI.getNumOperands();
715 if (NumOp >= 2) {
716 for (int i = 0; i < NumOp-1; ++i) {
717 const MCOperand &MCOp1 = MI.getOperand(i);
718 const MCOperand &MCOp2 = MI.getOperand(i + 1);
719 if (MCOp1.isImm() && MCOp2.isReg() &&
720 (!MCOp2.getReg() || MCOp2.getReg() == ARM::CPSR)) {
722 return true;
723 }
724 }
725 }
726 return false;
727}
728
729
730
731uint32_t ARMMCCodeEmitter::
732getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
733 SmallVectorImpl &Fixups,
734 const MCSubtargetInfo &STI) const {
735
736
737 if (isThumb2(STI))
738 return
740 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
741}
742
743
744
745uint32_t ARMMCCodeEmitter::
746getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
747 SmallVectorImpl &Fixups,
748 const MCSubtargetInfo &STI) const {
749 const MCOperand MO = MI.getOperand(OpIdx);
752 return ::getBranchTargetOpValue(MI, OpIdx,
754 return ::getBranchTargetOpValue(MI, OpIdx,
756 }
757
758 return MO.getImm() >> 2;
759}
760
761uint32_t ARMMCCodeEmitter::
762getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
763 SmallVectorImpl &Fixups,
764 const MCSubtargetInfo &STI) const {
765 const MCOperand MO = MI.getOperand(OpIdx);
768 return ::getBranchTargetOpValue(MI, OpIdx,
771 }
772
773 return MO.getImm() >> 2;
774}
775
776uint32_t ARMMCCodeEmitter::
777getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
778 SmallVectorImpl &Fixups,
779 const MCSubtargetInfo &STI) const {
780 const MCOperand MO = MI.getOperand(OpIdx);
783
784 return MO.getImm() >> 1;
785}
786
787
788
789uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
790 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,
791 const MCSubtargetInfo &STI) const {
792 unsigned Val = 0;
793 const MCOperand MO = MI.getOperand(OpIdx);
794
797 else
798 Val = MO.getImm() >> 1;
799
800 bool I = (Val & 0x800000);
801 bool J1 = (Val & 0x400000);
802 bool J2 = (Val & 0x200000);
803 if (I ^ J1)
804 Val &= ~0x400000;
805 else
806 Val |= 0x400000;
807
808 if (I ^ J2)
809 Val &= ~0x200000;
810 else
811 Val |= 0x200000;
812
813 return Val;
814}
815
816
817
818uint32_t ARMMCCodeEmitter::
819getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
820 SmallVectorImpl &Fixups,
821 const MCSubtargetInfo &STI) const {
822 const MCOperand MO = MI.getOperand(OpIdx);
825 Fixups, STI);
826 int64_t offset = MO.getImm();
827 uint32_t Val = 0x2000;
828
829 int SoImmVal;
830 if (offset == INT32_MIN) {
831 Val = 0x1000;
832 SoImmVal = 0;
833 } else if (offset < 0) {
834 Val = 0x1000;
835 offset *= -1;
837 if(SoImmVal == -1) {
838 Val = 0x2000;
839 offset *= -1;
841 }
842 } else {
844 if(SoImmVal == -1) {
845 Val = 0x1000;
846 offset *= -1;
848 }
849 }
850
851 assert(SoImmVal != -1 && "Not a valid so_imm value!");
852
853 Val |= SoImmVal;
854 return Val;
855}
856
857
858
859uint32_t ARMMCCodeEmitter::
860getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
861 SmallVectorImpl &Fixups,
862 const MCSubtargetInfo &STI) const {
863 const MCOperand MO = MI.getOperand(OpIdx);
866 Fixups, STI);
867 int32_t Val = MO.getImm();
868 if (Val == INT32_MIN)
869 Val = 0x1000;
870 else if (Val < 0) {
871 Val *= -1;
872 Val |= 0x1000;
873 }
874 return Val;
875}
876
877
878
879uint32_t ARMMCCodeEmitter::
880getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
881 SmallVectorImpl &Fixups,
882 const MCSubtargetInfo &STI) const {
883 const MCOperand MaskMO = MI.getOperand(OpIdx);
884 assert(MaskMO.isImm() && "Unexpected operand type!");
885
887
888
889
890
891
892 assert(OpIdx > 0 && "IT mask appears first!");
893 const MCOperand CondMO = MI.getOperand(OpIdx-1);
894 assert(CondMO.isImm() && "Unexpected operand type!");
895 if (CondMO.getImm() & 1) {
896 unsigned LowBit = Mask & -Mask;
897 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
898 Mask ^= BitsAboveLowBit;
899 }
900
902}
903
904
905
906uint32_t ARMMCCodeEmitter::
907getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
908 SmallVectorImpl &Fixups,
909 const MCSubtargetInfo &STI) const {
910 const MCOperand MO = MI.getOperand(OpIdx);
913 Fixups, STI);
915}
916
917
918
919uint32_t ARMMCCodeEmitter::
920getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
921 SmallVectorImpl &,
922 const MCSubtargetInfo &STI) const {
923
924
925
926 const MCOperand &MO1 = MI.getOperand(OpIdx);
927 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
930 return (Rm << 3) | Rn;
931}
932
933
934
935uint32_t
936ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
937 SmallVectorImpl &Fixups,
938 const MCSubtargetInfo &STI) const {
939
940
941
942
943
944
945
946
947 unsigned Size, ShiftImm;
948 switch(MI.getOpcode()) {
949 case ARM::MVE_VSHLL_imms16bh:
950 case ARM::MVE_VSHLL_imms16th:
951 case ARM::MVE_VSHLL_immu16bh:
952 case ARM::MVE_VSHLL_immu16th:
954 break;
955 case ARM::MVE_VSHLL_imms8bh:
956 case ARM::MVE_VSHLL_imms8th:
957 case ARM::MVE_VSHLL_immu8bh:
958 case ARM::MVE_VSHLL_immu8th:
960 break;
961 default:
962 llvm_unreachable("Use of operand not supported by this instruction");
963 }
964 ShiftImm = MI.getOperand(OpIdx).getImm();
965 return Size + ShiftImm;
966}
967
968
969uint32_t ARMMCCodeEmitter::
970getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
971 SmallVectorImpl &Fixups,
972 const MCSubtargetInfo &STI) const {
973
974
975
976 unsigned Reg = 0, Imm12 = 0;
977 bool isAdd = true;
978
979 const MCOperand &MO = MI.getOperand(OpIdx);
980 if (MO.isReg()) {
981 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
982 if (MO1.isImm()) {
983 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
984 } else if (MO1.isExpr()) {
986 "Thumb mode requires different encoding");
988 isAdd = false;
991 }
992 } else if (MO.isExpr()) {
994 isAdd = false;
996 if (isThumb2(STI))
998 else
1001
1002 ++MCNumCPRelocations;
1003 } else {
1004 Reg = ARM::PC;
1006 if (Offset == INT32_MIN) {
1008 isAdd = false;
1009 } else if (Offset < 0) {
1011 isAdd = false;
1012 }
1014 }
1015 uint32_t Binary = Imm12 & 0xfff;
1016
1017 if (isAdd)
1018 Binary |= (1 << 12);
1021}
1022
1023template<unsigned Bits, unsigned Shift>
1024uint32_t ARMMCCodeEmitter::
1025getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1026 SmallVectorImpl &Fixups,
1027 const MCSubtargetInfo &STI) const {
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037 int32_t Imm = MI.getOperand(OpIdx).getImm();
1038 bool isAdd = Imm >= 0;
1039
1040
1041 if (Imm < 0)
1042 Imm = -(uint32_t)Imm;
1043
1044 Imm >>= Shift;
1045
1047
1048 if (isAdd)
1051}
1052
1053
1054
1055uint32_t ARMMCCodeEmitter::
1056getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1057 SmallVectorImpl &Fixups,
1058 const MCSubtargetInfo &STI) const {
1059
1060
1061 const MCOperand &M0 = MI.getOperand(OpIdx);
1062 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1063
1066
1067 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1068
1069 return (Rn << 3) | Qm;
1070}
1071
1072
1073
1074template
1075uint32_t ARMMCCodeEmitter::
1076getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1077 SmallVectorImpl &Fixups,
1078 const MCSubtargetInfo &STI) const {
1079
1080
1081 const MCOperand &M0 = MI.getOperand(OpIdx);
1082 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1083
1085 int32_t Imm = M1.getImm();
1086
1087 bool isAdd = Imm >= 0;
1088
1089 Imm >>= shift;
1090
1091 if (!isAdd)
1092 Imm = -(uint32_t)Imm;
1093
1094 Imm &= 0x7f;
1095
1096 if (isAdd)
1097 Imm |= 0x80;
1098
1099 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1100
1101 return (Qm << 8) | Imm;
1102}
1103
1104
1105
1106uint32_t ARMMCCodeEmitter::
1107getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1108 SmallVectorImpl &Fixups,
1109 const MCSubtargetInfo &STI) const {
1110
1111
1112
1114 bool isAdd = true;
1115
1116 const MCOperand &MO = MI.getOperand(OpIdx);
1117 if (!MO.isReg()) {
1120 isAdd = false ;
1121
1122 assert(MO.isExpr() && "Unexpected machine operand type!");
1123 const MCExpr *Expr = MO.getExpr();
1125 addFixup(Fixups, 0, Expr, Kind);
1126
1127 ++MCNumCPRelocations;
1128 } else
1129 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1130
1131
1132
1133
1134
1135
1136
1137 assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!");
1138 uint32_t Binary = (Imm8 >> 2) & 0xff;
1139
1140 if (isAdd)
1144}
1145
1146
1147
1148uint32_t
1149ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1150 SmallVectorImpl &Fixups,
1151 const MCSubtargetInfo &STI) const {
1152
1153
1154
1155 unsigned Reg, Imm7;
1156
1157 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1158
1159
1160
1161
1162
1163
1164
1165 uint32_t Binary = (Imm7 >> 2) & 0xff;
1166
1167 if (isAdd)
1171}
1172
1173
1174
1175uint32_t ARMMCCodeEmitter::
1176getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1177 SmallVectorImpl &Fixups,
1178 const MCSubtargetInfo &STI) const {
1179
1180
1181 const MCOperand &MO = MI.getOperand(OpIdx);
1182 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1185 return (Reg << 8) | Imm8;
1186}
1187
1188uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
1189 SmallVectorImpl &Fixups,
1190 const MCSubtargetInfo &STI) const {
1191
1192
1193 const MCOperand &MO = MI.getOperand(OpIdx);
1195
1196 return static_cast<unsigned>(MO.getImm());
1197
1198
1199
1200 const MCExpr *E = MO.getExpr();
1204 E = ARM16Expr->getSubExpr();
1205
1207 const int64_t Value = MCE->getValue();
1208 if (Value > UINT32_MAX)
1210
1211 switch (ARM16Expr->getSpecifier()) {
1213 return (int32_t(Value) & 0xffff0000) >> 16;
1215 return (int32_t(Value) & 0x0000ffff);
1216
1218 return (int32_t(Value) & 0xff000000) >> 24;
1220 return (int32_t(Value) & 0x00ff0000) >> 16;
1222 return (int32_t(Value) & 0x0000ff00) >> 8;
1224 return (int32_t(Value) & 0x000000ff);
1225
1227 }
1228 }
1229
1230 switch (ARM16Expr->getSpecifier()) {
1235 break;
1239 break;
1242 llvm_unreachable(":upper_8_15: not supported in Arm state");
1244 break;
1249 break;
1252 llvm_unreachable(":lower_8_15: not supported in Arm state");
1254 break;
1259 break;
1260 }
1261
1263 return 0;
1264 }
1265
1266
1267
1268
1269
1270
1271 llvm_unreachable("expression without :upper16:, :lower16:, :upper8_15:,"
1272 ":upper0_7:, lower8_15: or :lower0_7:");
1273}
1274
1275uint32_t ARMMCCodeEmitter::
1276getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1277 SmallVectorImpl &Fixups,
1278 const MCSubtargetInfo &STI) const {
1279 const MCOperand &MO = MI.getOperand(OpIdx);
1280 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1281 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1287 unsigned SBits = getShiftOp(ShOp);
1288
1289
1290
1291 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1292
1293
1294
1295
1296
1297
1298
1299
1300 uint32_t Binary = Rm;
1302 Binary |= SBits << 5;
1303 Binary |= ShImm << 7;
1304 if (isAdd)
1307}
1308
1309uint32_t ARMMCCodeEmitter::
1310getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1311 SmallVectorImpl &Fixups,
1312 const MCSubtargetInfo &STI) const {
1313
1314
1315
1316 const MCOperand &MO = MI.getOperand(OpIdx);
1317 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1322
1325 Binary <<= 7;
1326 Binary |= getShiftOp(ShOp) << 5;
1328 }
1329 return Binary | (isAdd << 12) | (isReg << 13);
1330}
1331
1332uint32_t ARMMCCodeEmitter::
1333getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1334 SmallVectorImpl &Fixups,
1335 const MCSubtargetInfo &STI) const {
1336
1337
1338 const MCOperand &MO = MI.getOperand(OpIdx);
1339 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1340 bool isAdd = MO1.getImm() != 0;
1342}
1343
1344uint32_t ARMMCCodeEmitter::
1345getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1346 SmallVectorImpl &Fixups,
1347 const MCSubtargetInfo &STI) const {
1348
1349
1350
1351
1352 const MCOperand &MO = MI.getOperand(OpIdx);
1353 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1358
1359 if (!isImm)
1361 return Imm8 | (isAdd << 8) | (isImm << 9);
1362}
1363
1364uint32_t ARMMCCodeEmitter::
1365getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1366 SmallVectorImpl &Fixups,
1367 const MCSubtargetInfo &STI) const {
1368
1369
1370
1371
1372
1373 const MCOperand &MO = MI.getOperand(OpIdx);
1374 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1375 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1376
1377
1378 if (!MO.isReg()) {
1380
1381 assert(MO.isExpr() && "Unexpected machine operand type!");
1382 const MCExpr *Expr = MO.getExpr();
1384 addFixup(Fixups, 0, Expr, Kind);
1385
1386 ++MCNumCPRelocations;
1387 return (Rn << 9) | (1 << 13);
1388 }
1394
1395 if (!isImm)
1397 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1398}
1399
1400
1401uint32_t ARMMCCodeEmitter::
1402getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1403 SmallVectorImpl &Fixups,
1404 const MCSubtargetInfo &STI) const {
1405
1406
1407 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1408 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1409 "Unexpected base register!");
1410
1411
1412
1413 return MO1.getImm() & 0xff;
1414}
1415
1416
1417uint32_t ARMMCCodeEmitter::
1418getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1419 SmallVectorImpl &Fixups,
1420 const MCSubtargetInfo &STI) const {
1421
1422
1423
1424 const MCOperand &MO = MI.getOperand(OpIdx);
1425 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1427 unsigned Imm5 = MO1.getImm();
1428 return ((Imm5 & 0x1f) << 3) | Rn;
1429}
1430
1431
1432uint32_t ARMMCCodeEmitter::
1433getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1434 SmallVectorImpl &Fixups,
1435 const MCSubtargetInfo &STI) const {
1436 const MCOperand MO = MI.getOperand(OpIdx);
1439 return (MO.getImm() >> 2);
1440}
1441
1442
1443uint32_t ARMMCCodeEmitter::
1444getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1445 SmallVectorImpl &Fixups,
1446 const MCSubtargetInfo &STI) const {
1447
1448
1449
1451 bool isAdd;
1452
1453 const MCOperand &MO = MI.getOperand(OpIdx);
1454 if (!MO.isReg()) {
1457 isAdd = false;
1458
1459 assert(MO.isExpr() && "Unexpected machine operand type!");
1460 const MCExpr *Expr = MO.getExpr();
1462 if (isThumb2(STI))
1464 else
1466 addFixup(Fixups, 0, Expr, Kind);
1467
1468 ++MCNumCPRelocations;
1469 } else {
1470 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1472 }
1473
1475
1476 if (isAdd)
1480}
1481
1482
1483uint32_t ARMMCCodeEmitter::
1484getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1485 SmallVectorImpl &Fixups,
1486 const MCSubtargetInfo &STI) const {
1487
1488
1489
1491 bool isAdd;
1492
1493 const MCOperand &MO = MI.getOperand(OpIdx);
1494 if (!MO.isReg()) {
1497 isAdd = false;
1498
1499 assert(MO.isExpr() && "Unexpected machine operand type!");
1500 const MCExpr *Expr = MO.getExpr();
1502 if (isThumb2(STI))
1504 else
1506 addFixup(Fixups, 0, Expr, Kind);
1507
1508 ++MCNumCPRelocations;
1509 } else {
1510 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1512 }
1513
1515
1516 if (isAdd)
1520}
1521
1522unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
1523 SmallVectorImpl &Fixups,
1524 const MCSubtargetInfo &ST) const {
1525 const MCOperand &MO = MI.getOperand(Op);
1526
1527
1529 const MCExpr *Expr = MO.getExpr();
1530
1532 addFixup(Fixups, 0, Expr, Kind);
1533 return 0;
1534 }
1535
1536
1538}
1539
1540unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
1541 SmallVectorImpl &Fixups,
1542 const MCSubtargetInfo &STI) const {
1543 const MCOperand &MO = MI.getOperand(Op);
1544
1545
1547 const MCExpr *Expr = MO.getExpr();
1548
1550 addFixup(Fixups, 0, Expr, Kind);
1551 return 0;
1552 }
1553 unsigned SoImm = MO.getImm();
1555 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
1557}
1558
1559unsigned ARMMCCodeEmitter::
1560getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1561 SmallVectorImpl &Fixups,
1562 const MCSubtargetInfo &STI) const {
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573 const MCOperand &MO = MI.getOperand(OpIdx);
1574 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1575 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1577
1578
1580
1581
1582 unsigned SBits = 0;
1583 MCRegister Rs = MO1.getReg();
1584 if (Rs) {
1585
1586
1587
1588
1589
1590 switch (SOpc) {
1596 }
1597 }
1598
1599 Binary |= SBits << 4;
1600
1601
1602
1605}
1606
1607unsigned ARMMCCodeEmitter::
1608getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1609 SmallVectorImpl &Fixups,
1610 const MCSubtargetInfo &STI) const {
1611
1612
1613
1614
1615
1616
1617
1618
1619 const MCOperand &MO = MI.getOperand(OpIdx);
1620 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1622
1623
1625
1626
1627 unsigned SBits = 0;
1628
1629
1630
1631
1632
1633
1634
1635 switch (SOpc) {
1644 }
1645
1646
1647 Binary |= SBits << 4;
1649 assert(Offset < 32 && "Offset must be in range 0-31!");
1651}
1652
1653
1654unsigned ARMMCCodeEmitter::
1655getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1656 SmallVectorImpl &Fixups,
1657 const MCSubtargetInfo &STI) const {
1658 const MCOperand &MO1 = MI.getOperand(OpNum);
1659 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1660 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1661
1662
1663
1669
1671}
1672
1673template<unsigned Bits, unsigned Shift>
1674unsigned ARMMCCodeEmitter::
1675getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1676 SmallVectorImpl &Fixups,
1677 const MCSubtargetInfo &STI) const {
1678 const MCOperand &MO1 = MI.getOperand(OpNum);
1679 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1680
1681
1683
1684
1685
1687 int32_t tmp = (int32_t)MO2.getImm();
1688 if (tmp == INT32_MIN) {
1689 tmp = 0;
1690 } else if (tmp < 0) {
1691 tmp = abs(tmp);
1692 } else {
1694 }
1695 Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1697}
1698
1699unsigned ARMMCCodeEmitter::
1700getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1701 SmallVectorImpl &Fixups,
1702 const MCSubtargetInfo &STI) const {
1703 const MCOperand &MO1 = MI.getOperand(OpNum);
1704
1705
1706 unsigned Value = 0;
1707 auto tmp = static_cast<uint32_t>(MO1.getImm());
1708 if (static_cast<int32_t>(tmp) < 0)
1709 tmp = -tmp;
1710 else
1711 Value |= 256;
1712 Value |= tmp & 255;
1714}
1715
1716unsigned ARMMCCodeEmitter::
1717getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1718 SmallVectorImpl &Fixups,
1719 const MCSubtargetInfo &STI) const {
1720
1721
1722
1723
1724
1725
1726
1727
1728 const MCOperand &MO = MI.getOperand(OpIdx);
1729 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1731
1732
1734
1735
1736 unsigned SBits = 0;
1737
1738
1739
1740
1741
1742 switch (SOpc) {
1749 }
1750
1751 Binary |= SBits << 4;
1754
1755
1757}
1758
1759unsigned ARMMCCodeEmitter::
1760getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1761 SmallVectorImpl &Fixups,
1762 const MCSubtargetInfo &STI) const {
1763
1764
1765 const MCOperand &MO = MI.getOperand(Op);
1766 uint32_t v = ~MO.getImm();
1769 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1770 return lsb | (msb << 5);
1771}
1772
1773unsigned ARMMCCodeEmitter::
1774getRegisterListOpValue(const MCInst &MI, unsigned Op,
1775 SmallVectorImpl &Fixups,
1776 const MCSubtargetInfo &STI) const {
1777
1778
1779
1780
1781
1782
1783 MCRegister Reg = MI.getOperand(Op).getReg();
1784 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1785 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1786
1787 unsigned Binary = 0;
1788
1789 if (SPRRegs || DPRRegs || Reg == ARM::VPR) {
1790
1792 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1793 Binary |= (RegNo & 0x1f) << 8;
1794
1795 if (MI.getOpcode() == ARM::VSCCLRMD)
1796
1797 --NumRegs;
1798 else if (MI.getOpcode() == ARM::VSCCLRMS) {
1799
1800
1801
1802 NumRegs = 0;
1803 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1804 Reg = MI.getOperand(I).getReg();
1805 if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
1806 NumRegs += 1;
1807 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
1808 NumRegs += 2;
1809 }
1810 }
1811 if (SPRRegs)
1813 else
1814 Binary |= NumRegs * 2;
1815 } else {
1818 [&](const MCOperand &LHS, const MCOperand &RHS) {
1819 return MRI.getEncodingValue(LHS.getReg()) <
1820 MRI.getEncodingValue(RHS.getReg());
1821 }));
1822 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1823 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1824 Binary |= 1 << RegNo;
1825 }
1826 }
1827
1829}
1830
1831
1832
1833unsigned ARMMCCodeEmitter::
1834getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1835 SmallVectorImpl &Fixups,
1836 const MCSubtargetInfo &STI) const {
1837 const MCOperand &Reg = MI.getOperand(Op);
1838 const MCOperand &Imm = MI.getOperand(Op + 1);
1839
1841 unsigned Align = 0;
1842
1843 switch (Imm.getImm()) {
1844 default: break;
1845 case 2:
1846 case 4:
1847 case 8: Align = 0x01; break;
1848 case 16: Align = 0x02; break;
1849 case 32: Align = 0x03; break;
1850 }
1851
1852 return RegNo | (Align << 4);
1853}
1854
1855
1856
1857unsigned ARMMCCodeEmitter::
1858getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1859 SmallVectorImpl &Fixups,
1860 const MCSubtargetInfo &STI) const {
1861 const MCOperand &Reg = MI.getOperand(Op);
1862 const MCOperand &Imm = MI.getOperand(Op + 1);
1863
1865 unsigned Align = 0;
1866
1867 switch (Imm.getImm()) {
1868 default: break;
1869 case 8:
1870 case 16:
1871 case 32:
1872 case 2: Align = 0x00; break;
1873 case 4: Align = 0x03; break;
1874 }
1875
1876 return RegNo | (Align << 4);
1877}
1878
1879
1880
1881
1882
1883
1884unsigned ARMMCCodeEmitter::
1885getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1886 SmallVectorImpl &Fixups,
1887 const MCSubtargetInfo &STI) const {
1888 const MCOperand &Reg = MI.getOperand(Op);
1889 const MCOperand &Imm = MI.getOperand(Op + 1);
1890
1892 unsigned Align = 0;
1893
1894 switch (Imm.getImm()) {
1895 default: break;
1896 case 2:
1897 case 4:
1898 case 8: Align = 0x01; break;
1899 case 16: Align = 0x03; break;
1900 }
1901
1902 return RegNo | (Align << 4);
1903}
1904
1905unsigned ARMMCCodeEmitter::
1906getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1907 SmallVectorImpl &Fixups,
1908 const MCSubtargetInfo &STI) const {
1909 const MCOperand &MO = MI.getOperand(Op);
1911 return 0x0D;
1913}
1914
1915unsigned ARMMCCodeEmitter::
1916getShiftRight8Imm(const MCInst &MI, unsigned Op,
1917 SmallVectorImpl &Fixups,
1918 const MCSubtargetInfo &STI) const {
1919 return 8 - MI.getOperand(Op).getImm();
1920}
1921
1922unsigned ARMMCCodeEmitter::
1923getShiftRight16Imm(const MCInst &MI, unsigned Op,
1924 SmallVectorImpl &Fixups,
1925 const MCSubtargetInfo &STI) const {
1926 return 16 - MI.getOperand(Op).getImm();
1927}
1928
1929unsigned ARMMCCodeEmitter::
1930getShiftRight32Imm(const MCInst &MI, unsigned Op,
1931 SmallVectorImpl &Fixups,
1932 const MCSubtargetInfo &STI) const {
1933 return 32 - MI.getOperand(Op).getImm();
1934}
1935
1936unsigned ARMMCCodeEmitter::
1937getShiftRight64Imm(const MCInst &MI, unsigned Op,
1938 SmallVectorImpl &Fixups,
1939 const MCSubtargetInfo &STI) const {
1940 return 64 - MI.getOperand(Op).getImm();
1941}
1942
1943void ARMMCCodeEmitter::encodeInstruction(const MCInst &MI,
1944 SmallVectorImpl &CB,
1945 SmallVectorImpl &Fixups,
1946 const MCSubtargetInfo &STI) const {
1947
1948 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1949 uint64_t TSFlags = Desc.TSFlags;
1951 return;
1952
1954 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1956 else
1958
1959 auto Endian =
1961 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1962 if (Size == 2) {
1964 } else if (isThumb(STI)) {
1965
1966
1969 } else {
1971 }
1972 ++MCNumEmitted;
1973}
1974
1975template <bool isNeg, ARM::Fixups fixup>
1976uint32_t
1977ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1978 SmallVectorImpl &Fixups,
1979 const MCSubtargetInfo &STI) const {
1980 const MCOperand MO = MI.getOperand(OpIdx);
1982 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1984}
1985
1986uint32_t
1987ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1988 SmallVectorImpl &Fixups,
1989 const MCSubtargetInfo &STI) const {
1990 const MCOperand MO = MI.getOperand(OpIdx);
1991 const MCOperand BranchMO = MI.getOperand(0);
1992
1998 addFixup(Fixups, 0, DiffExpr, Kind);
1999 return 0;
2000 }
2001
2004 assert(Diff == 4 || Diff == 2);
2005
2006 return Diff == 4;
2007}
2008
2009uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
2010 SmallVectorImpl &Fixups,
2011 const MCSubtargetInfo &STI)const {
2012 const MCOperand MO = MI.getOperand(OpIdx);
2013 assert(MO.isImm() && "Unexpected operand type!");
2014
2016 int Imm = 0;
2017
2018
2019
2020 unsigned PrevBit = 0;
2021 for (int i = 3; i >= 0; --i) {
2022 unsigned Bit = (Value >> i) & 1;
2023
2024
2025 if ((Value & ~(~0U << i)) == 0) {
2026 Imm |= (1 << i);
2027 break;
2028 }
2029
2030
2031 if (Bit != PrevBit)
2032 Imm |= (1 << i);
2033
2034 PrevBit = Bit;
2035 }
2036
2037 return Imm;
2038}
2039
2040uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
2041 const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups,
2042 const MCSubtargetInfo &STI) const {
2043
2044 const MCOperand MO = MI.getOperand(OpIdx);
2045 assert(MO.isImm() && "Unexpected operand type!");
2046
2047 switch (MO.getImm()) {
2048 default:
2049 assert(0 && "Unexpected Condition!");
2050 return 0;
2053 return 0;
2056 return 1;
2058 return 4;
2060 return 5;
2062 return 6;
2064 return 7;
2065 }
2066}
2067
2068uint32_t ARMMCCodeEmitter::
2069getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
2070 SmallVectorImpl &Fixups,
2071 const MCSubtargetInfo &STI) const {
2072 const MCOperand &MO = MI.getOperand(OpIdx);
2073 assert(MO.isImm() && "Unexpected operand type!");
2075}
2076
2077template
2078uint32_t ARMMCCodeEmitter::
2079getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
2080 SmallVectorImpl &Fixups,
2081 const MCSubtargetInfo &STI) const {
2082 const MCOperand MO = MI.getOperand(OpIdx);
2083 assert(MO.isImm() && "Unexpected operand type!");
2084
2086 return Value - start;
2087}
2088
2089#include "ARMGenMCCodeEmitter.inc"
2090
2093 return new ARMMCCodeEmitter(MCII, Ctx, true);
2094}
2095
2098 return new ARMMCCodeEmitter(MCII, Ctx, false);
2099}
unsigned const MachineRegisterInfo * MRI
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static bool isThumb(const MCSubtargetInfo &STI)
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
Definition ARMMCCodeEmitter.cpp:713
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
Definition ARMMCCodeEmitter.cpp:435
static int32_t encodeThumbBLOffset(int32_t offset)
Definition ARMMCCodeEmitter.cpp:635
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Definition ARMMCCodeEmitter.cpp:616
Function Alias Analysis false
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
static bool isReg(const MCInst &MI, unsigned OpNo)
MachineInstr unsigned OpIdx
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
@ Specifier
Expression with a relocation specifier.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegister getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint64_t getDFPImm() const
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
constexpr bool isValid() const
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
constexpr unsigned id() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
unsigned getAM2Offset(unsigned AM2Opc)
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
@ fixup_thumb_adr_pcrel_10
@ fixup_arm_thumb_upper_8_15
@ fixup_arm_thumb_lower_0_7
@ fixup_arm_pcrel_10_unscaled
@ fixup_arm_thumb_upper_0_7
@ fixup_bfcsel_else_target
@ fixup_arm_ldst_pcrel_12
@ fixup_arm_thumb_lower_8_15
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
FunctionAddr VTableAddr Value
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition ARMMCCodeEmitter.cpp:2091
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
unsigned M1(unsigned Val)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
uint16_t MCFixupKind
Extensible enumeration to represent the type of a fixup.
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
static Lanai::Fixups FixupKind(const MCExpr *Expr)
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
To bit_cast(const From &from) noexcept
DWARFExpression::Operation Op
unsigned M0(unsigned Val)
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition ARMMCCodeEmitter.cpp:2096