BreakFalseDeps.cpp Source File (original) (raw)

32using namespace llvm;

34namespace llvm {

37private:

44 std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;

51public:

52 static char ID;

56 }

62 }

69 }

71private:

84 bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,

85 unsigned Pref);

89 bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);

97};

99}

100

101#define DEBUG_TYPE "break-false-deps"

102

107

109

110bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,

111 unsigned Pref) {

112

113

114 if (MI->isRegTiedToDefOperand(OpIdx))

115 return false;

116

118 assert(MO.isUndef() && "Expected undef machine operand");

119

120

122 return false;

123

125

126

128 unsigned NumRoots = 0;

130 NumRoots++;

131 if (NumRoots > 1)

132 return false;

133 }

134 }

135

136

138 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);

139 assert(OpRC && "Not a valid register class");

140

141

142

144 if (CurrMO.isUndef() || !OpRC->contains(CurrMO.getReg()))

145 continue;

146

147

148 MO.setReg(CurrMO.getReg());

149 return true;

150 }

151

152

153

154 unsigned MaxClearance = 0;

155 unsigned MaxClearanceReg = OriginalReg;

159 if (Clearance <= MaxClearance)

160 continue;

161 MaxClearance = Clearance;

162 MaxClearanceReg = Reg;

163

164 if (MaxClearance > Pref)

165 break;

166 }

167

168

169 if (MaxClearanceReg != OriginalReg)

170 MO.setReg(MaxClearanceReg);

171

172 return false;

173}

174

175bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,

176 unsigned Pref) {

177 MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg();

179 LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);

180

181 if (Pref > Clearance) {

183 return true;

184 }

186 return false;

187}

188

190 assert(->isDebugInstr() && "Won't process debug values");

191

193

194

195

199 continue;

200

202 if (Pref) {

203 bool HadTrueDependency = pickBestRegisterForUndef(MI, i, Pref);

204

205

206

207 if (!HadTrueDependency && shouldBreakDependence(MI, i, Pref))

208 UndefReads.push_back(std::make_pair(MI, i));

209 }

210 }

211

212

213

215 return;

216

217 for (unsigned i = 0,

218 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();

219 i != e; ++i) {

222 continue;

224 continue;

225

227 if (Pref && shouldBreakDependence(MI, i, Pref))

229 }

230}

231

233 if (UndefReads.empty())

234 return;

235

236

237

239 return;

240

241

243

244

246

247 MachineInstr *UndefMI = UndefReads.back().first;

248 unsigned OpIdx = UndefReads.back().second;

249

251

253

254 if (UndefMI == &I) {

257

258 UndefReads.pop_back();

259 if (UndefReads.empty())

260 return;

261

262 UndefMI = UndefReads.back().first;

263 OpIdx = UndefReads.back().second;

264 }

265 }

266}

267

269 UndefReads.clear();

270

271

272

273

275 if (.isDebugInstr())

276 processDefs(&MI);

277 }

278 processUndefReads(MBB);

279}

280

283 return false;

284 MF = &mf;

287 RDA = &getAnalysis();

288

290

291 LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n");

292

293

294

297 (void)MBB ;

298

299

302 processBasicBlock(&MBB);

303

304 return false;

305}

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

This file implements the LivePhysRegs utility for tracking liveness of physical registers.

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

void setPreservesAll()

Set by analyses that do not transform their input at all.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

MachineFunctionProperties getRequiredProperties() const override

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

FunctionPass class - This class is used to implement most global optimizations.

bool skipFunction(const Function &F) const

Optional passes call this function to check whether the pass should be skipped.

bool hasMinSize() const

Optimize this function for minimum size (-Oz).

A set of physical registers with utility functions to track liveness when walking backward/forward th...

A set of live virtual registers and physical register units.

LaneBitmask contains(Register Reg) const

void init(const MachineRegisterInfo &MRI)

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

unsigned getNumDefs() const

Return the number of MachineOperands that are register definitions.

MCRegUnitRootIterator enumerates the root registers of a register unit.

bool isValid() const

Check if the iterator is at the end of the list.

iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const

Returns an iterator range over all regunits for Reg.

Wrapper class representing physical registers. Should be passed by value.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Properties which a MachineFunction may have at a given point in time.

MachineFunctionProperties & set(Property P)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

void setReg(Register Reg)

Change the register this operand corresponds to.

bool isRenamable() const

isRenamable - Returns true if this register may be renamed, i.e.

getReg - Returns the register number.

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This class provides the reaching def analysis.

int getClearance(MachineInstr *MI, Register Reg) const

Provides the clearance - the number of instructions since the closest reaching def instuction of Reg ...

void runOnMachineFunction(const MachineFunction &MF)

runOnFunction - Prepare to answer questions about MF.

ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const

getOrder - Returns the preferred allocation order for RC.

MCRegister asMCReg() const

Utility to check-convert this value to a MCRegister.

size_type count(ConstPtrType Ptr) const

count - Return 1 if the specified pointer is in the set, 0 otherwise.

TargetInstrInfo - Interface to description of machine instruction set.

virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const

Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...

virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const

Return the minimum clearance before an instruction that reads an unused register.

virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.

virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const

Given a machine instruction descriptor, returns the register class constraint for OpNum,...

bool contains(Register Reg) const

Return true if the specified register is included in this register class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual const TargetInstrInfo * getInstrInfo() const

Reg

All possible values of the reg field in the ModR/M byte.

This is an optimization pass for GlobalISel generic memory operations.

iterator_range< df_ext_iterator< T, SetTy > > depth_first_ext(const T &G, SetTy &S)

auto reverse(ContainerTy &&C)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

void initializeBreakFalseDepsPass(PassRegistry &)

FunctionPass * createBreakFalseDeps()

Creates Break False Dependencies pass.