GISelKnownBits.cpp Source File (original) (raw)

25#define DEBUG_TYPE "gisel-known-bits"

27using namespace llvm;

32 "Analysis for ComputingKnownBits", false, true)

35 : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),

36 DL(MF.getFunction().getDataLayout()), MaxDepth(MaxDepth) {}

40 switch (MI->getOpcode()) {

41 case TargetOpcode::COPY:

43 case TargetOpcode::G_ASSERT_ALIGN: {

45 return Align(MI->getOperand(2).getImm());

46 }

47 case TargetOpcode::G_FRAME_INDEX: {

48 int FrameIdx = MI->getOperand(1).getIndex();

50 }

51 case TargetOpcode::G_INTRINSIC:

52 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:

53 case TargetOpcode::G_INTRINSIC_CONVERGENT:

54 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:

55 default:

57 }

58}

61 assert(MI.getNumExplicitDefs() == 1 &&

62 "expected single return generic instruction");

64}

71 APInt DemandedElts =

74}

79 assert(ComputeKnownBitsCache.empty() && "Cache should have been cleared");

83 ComputeKnownBitsCache.clear();

84 return Known;

85}

91}

95}

101 dbgs() << "[" << Depth << "] Compute known bits: " << MI << "[" << Depth

102 << "] Computed for: " << MI << "[" << Depth << "] Known: 0x"

104 << "[" << Depth << "] Zero: 0x" << toString(Known.Zero, 16, false)

105 << "\n"

106 << "[" << Depth << "] One: 0x" << toString(Known.One, 16, false)

107 << "\n";

108}

109

110

111void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1,

113 const APInt &DemandedElts,

114 unsigned Depth) {

115

117

118

120 return;

121

124

125

127}

128

129

130

131

141}

142

144 const APInt &DemandedElts,

145 unsigned Depth) {

147 unsigned Opcode = MI.getOpcode();

149

150

151

152

155 return;

156 }

157

158#ifndef NDEBUG

162 "DemandedElt width should equal the fixed vector number of elements");

163 } else {

165 "DemandedElt width should be 1 for scalars or scalable vectors");

166 }

167#endif

168

170 auto CacheEntry = ComputeKnownBitsCache.find(R);

171 if (CacheEntry != ComputeKnownBitsCache.end()) {

172 Known = CacheEntry->second;

176 return;

177 }

179

180

181

182

183

184

185

186

187

189 return;

190

191 if (!DemandedElts)

192 return;

193

195

196 switch (Opcode) {

197 default:

200 break;

201 case TargetOpcode::G_BUILD_VECTOR: {

202

204 for (unsigned i = 0, e = MI.getNumOperands() - 1; i < e; ++i) {

205 if (!DemandedElts[i])

206 continue;

207

210

211

213

214

216 break;

217 }

218 break;

219 }

220 case TargetOpcode::COPY:

221 case TargetOpcode::G_PHI:

222 case TargetOpcode::PHI: {

225

226

227

228 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?");

229

230

231

232

233

234

235

236

237

239

240

241 for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {

243 Register SrcReg = Src.getReg();

244

245

246

247

248

249

250

251 if (SrcReg.isVirtual() && Src.getSubReg() == 0 &&

253

255 Depth + (Opcode != TargetOpcode::COPY));

258

259

261 break;

262 } else {

263

265 break;

266 }

267 }

268 break;

269 }

270 case TargetOpcode::G_CONSTANT: {

272 break;

273 }

274 case TargetOpcode::G_FRAME_INDEX: {

275 int FrameIdx = MI.getOperand(1).getIndex();

277 break;

278 }

279 case TargetOpcode::G_SUB: {

285 break;

286 }

287 case TargetOpcode::G_XOR: {

292

293 Known ^= Known2;

294 break;

295 }

296 case TargetOpcode::G_PTR_ADD: {

298 break;

299

300 LLT Ty = MRI.getType(MI.getOperand(1).getReg());

302 break;

303 [[fallthrough]];

304 }

305 case TargetOpcode::G_ADD: {

311 break;

312 }

313 case TargetOpcode::G_AND: {

314

319

320 Known &= Known2;

321 break;

322 }

323 case TargetOpcode::G_OR: {

324

329

330 Known |= Known2;

331 break;

332 }

333 case TargetOpcode::G_MUL: {

339 break;

340 }

341 case TargetOpcode::G_SELECT: {

342 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),

343 Known, DemandedElts, Depth + 1);

344 break;

345 }

346 case TargetOpcode::G_SMIN: {

347

354 break;

355 }

356 case TargetOpcode::G_SMAX: {

357

364 break;

365 }

366 case TargetOpcode::G_UMIN: {

369 DemandedElts, Depth + 1);

371 DemandedElts, Depth + 1);

373 break;

374 }

375 case TargetOpcode::G_UMAX: {

378 DemandedElts, Depth + 1);

380 DemandedElts, Depth + 1);

382 break;

383 }

384 case TargetOpcode::G_FCMP:

385 case TargetOpcode::G_ICMP: {

387 break;

389 Opcode == TargetOpcode::G_FCMP) ==

393 break;

394 }

395 case TargetOpcode::G_SEXT: {

398

399

401 break;

402 }

403 case TargetOpcode::G_ASSERT_SEXT:

404 case TargetOpcode::G_SEXT_INREG: {

407 Known = Known.sextInReg(MI.getOperand(2).getImm());

408 break;

409 }

410 case TargetOpcode::G_ANYEXT: {

414 break;

415 }

416 case TargetOpcode::G_LOAD: {

422 break;

423 }

424 case TargetOpcode::G_SEXTLOAD:

425 case TargetOpcode::G_ZEXTLOAD: {

427 break;

432 Known = Opcode == TargetOpcode::G_SEXTLOAD

435 break;

436 }

437 case TargetOpcode::G_ASHR: {

444 break;

445 }

446 case TargetOpcode::G_LSHR: {

453 break;

454 }

455 case TargetOpcode::G_SHL: {

462 break;

463 }

464 case TargetOpcode::G_INTTOPTR:

465 case TargetOpcode::G_PTRTOINT:

467 break;

468

469 [[fallthrough]];

470 case TargetOpcode::G_ASSERT_ZEXT:

471 case TargetOpcode::G_ZEXT:

472 case TargetOpcode::G_TRUNC: {

473 Register SrcReg = MI.getOperand(1).getReg();

475 unsigned SrcBitWidth;

476

477

478 if (Opcode == TargetOpcode::G_ASSERT_ZEXT)

479 SrcBitWidth = MI.getOperand(2).getImm();

480 else {

484 }

485 assert(SrcBitWidth && "SrcBitWidth can't be zero");

491 break;

492 }

493 case TargetOpcode::G_ASSERT_ALIGN: {

494 int64_t LogOfAlign = Log2_64(MI.getOperand(2).getImm());

495

496

497

498

501 break;

502 }

503 case TargetOpcode::G_MERGE_VALUES: {

504 unsigned NumOps = MI.getNumOperands();

506

507 for (unsigned I = 0; I != NumOps - 1; ++I) {

510 DemandedElts, Depth + 1);

511 Known.insertBits(SrcOpKnown, I * OpSize);

512 }

513 break;

514 }

515 case TargetOpcode::G_UNMERGE_VALUES: {

516 unsigned NumOps = MI.getNumOperands();

517 Register SrcReg = MI.getOperand(NumOps - 1).getReg();

519

521 return;

522

523

524 unsigned DstIdx = 0;

525 for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R;

526 ++DstIdx)

527 ;

528

529 APInt SubDemandedElts = DemandedElts;

532 SubDemandedElts =

534 }

535

538

540 Known = std::move(SrcOpKnown);

541 else

543 break;

544 }

545 case TargetOpcode::G_BSWAP: {

546 Register SrcReg = MI.getOperand(1).getReg();

549 break;

550 }

551 case TargetOpcode::G_BITREVERSE: {

552 Register SrcReg = MI.getOperand(1).getReg();

555 break;

556 }

557 case TargetOpcode::G_CTPOP: {

560

561

565

566

567 break;

568 }

569 case TargetOpcode::G_UBFX: {

570 KnownBits SrcOpKnown, OffsetKnown, WidthKnown;

578 break;

579 }

580 case TargetOpcode::G_SBFX: {

581 KnownBits SrcOpKnown, OffsetKnown, WidthKnown;

589

590

594 break;

595 }

596 case TargetOpcode::G_UADDO:

597 case TargetOpcode::G_UADDE:

598 case TargetOpcode::G_SADDO:

599 case TargetOpcode::G_SADDE:

600 case TargetOpcode::G_USUBO:

601 case TargetOpcode::G_USUBE:

602 case TargetOpcode::G_SSUBO:

603 case TargetOpcode::G_SSUBE:

604 case TargetOpcode::G_UMULO:

605 case TargetOpcode::G_SMULO: {

606 if (MI.getOperand(1).getReg() == R) {

607

608

613 }

614 break;

615 }

616 case TargetOpcode::G_CTLZ:

617 case TargetOpcode::G_CTLZ_ZERO_UNDEF: {

621

625 break;

626 }

627 }

628

630

631

632 ComputeKnownBitsCache[R] = Known;

633}

634

635

636unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1,

637 const APInt &DemandedElts,

638 unsigned Depth) {

639

641 if (Src1SignBits == 1)

642 return 1;

644}

645

646

647

648

650 unsigned TyBits) {

652 if (!Ranges)

653 return 1;

654

658 case TargetOpcode::G_SEXTLOAD:

660 break;

661 case TargetOpcode::G_ZEXTLOAD:

663 break;

664 default:

665 break;

666 }

667 }

668

671}

672

674 const APInt &DemandedElts,

675 unsigned Depth) {

677 unsigned Opcode = MI.getOpcode();

678

679 if (Opcode == TargetOpcode::G_CONSTANT)

680 return MI.getOperand(1).getCImm()->getValue().getNumSignBits();

681

683 return 1;

684

685 if (!DemandedElts)

686 return 1;

687

690

691

692

693

694

696 return 1;

697

698 unsigned FirstAnswer = 1;

699 switch (Opcode) {

700 case TargetOpcode::COPY: {

702 if (Src.getReg().isVirtual() && Src.getSubReg() == 0 &&

704

706 }

707

708 return 1;

709 }

710 case TargetOpcode::G_SEXT: {

711 Register Src = MI.getOperand(1).getReg();

715 }

716 case TargetOpcode::G_ASSERT_SEXT:

717 case TargetOpcode::G_SEXT_INREG: {

718

719 Register Src = MI.getOperand(1).getReg();

720 unsigned SrcBits = MI.getOperand(2).getImm();

721 unsigned InRegBits = TyBits - SrcBits + 1;

723 }

724 case TargetOpcode::G_LOAD: {

725 GLoad *Ld = cast(&MI);

726 if (DemandedElts != 1 || getDataLayout ().isLittleEndian())

727 break;

728

730 }

731 case TargetOpcode::G_SEXTLOAD: {

733

734

736 return 1;

737

739 if (NumBits != 1)

740 return NumBits;

741

742

745 }

746 case TargetOpcode::G_ZEXTLOAD: {

748

749

751 return 1;

752

754 if (NumBits != 1)

755 return NumBits;

756

757

760 }

761 case TargetOpcode::G_AND:

762 case TargetOpcode::G_OR:

763 case TargetOpcode::G_XOR: {

764 Register Src1 = MI.getOperand(1).getReg();

765 unsigned Src1NumSignBits =

767 if (Src1NumSignBits != 1) {

768 Register Src2 = MI.getOperand(2).getReg();

769 unsigned Src2NumSignBits =

771 FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits);

772 }

773 break;

774 }

775 case TargetOpcode::G_TRUNC: {

776 Register Src = MI.getOperand(1).getReg();

778

779

783 if (NumSrcSignBits > (NumSrcBits - DstTyBits))

784 return NumSrcSignBits - (NumSrcBits - DstTyBits);

785 break;

786 }

787 case TargetOpcode::G_SELECT: {

788 return computeNumSignBitsMin(MI.getOperand(2).getReg(),

789 MI.getOperand(3).getReg(), DemandedElts,

791 }

792 case TargetOpcode::G_SMIN:

793 case TargetOpcode::G_SMAX:

794 case TargetOpcode::G_UMIN:

795 case TargetOpcode::G_UMAX:

796

797 return computeNumSignBitsMin(MI.getOperand(1).getReg(),

798 MI.getOperand(2).getReg(), DemandedElts,

800 case TargetOpcode::G_SADDO:

801 case TargetOpcode::G_SADDE:

802 case TargetOpcode::G_UADDO:

803 case TargetOpcode::G_UADDE:

804 case TargetOpcode::G_SSUBO:

805 case TargetOpcode::G_SSUBE:

806 case TargetOpcode::G_USUBO:

807 case TargetOpcode::G_USUBE:

808 case TargetOpcode::G_SMULO:

809 case TargetOpcode::G_UMULO: {

810

811

812

813 if (MI.getOperand(1).getReg() == R) {

816 return TyBits;

817 }

818

819 break;

820 }

821 case TargetOpcode::G_FCMP:

822 case TargetOpcode::G_ICMP: {

823 bool IsFP = Opcode == TargetOpcode::G_FCMP;

824 if (TyBits == 1)

825 break;

828 return TyBits;

830 return TyBits - 1;

831 break;

832 }

833 case TargetOpcode::G_INTRINSIC:

834 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:

835 case TargetOpcode::G_INTRINSIC_CONVERGENT:

836 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:

837 default: {

838 unsigned NumBits =

840 if (NumBits > 1)

841 FirstAnswer = std::max(FirstAnswer, NumBits);

842 break;

843 }

844 }

845

846

847

851 Mask = Known.Zero;

852 } else if (Known.isNegative()) {

853 Mask = Known.One;

854 } else {

855

856 return FirstAnswer;

857 }

858

859

860

861 Mask <<= Mask.getBitWidth() - TyBits;

862 return std::max(FirstAnswer, Mask.countl_one());

863}

864

867 APInt DemandedElts =

870}

871

875}

876

878 return false;

879}

880

882 if (!Info) {

883 unsigned MaxDepth =

885 Info = std::make_unique(MF, MaxDepth);

886 }

887 return *Info;

888}

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

#define LLVM_ATTRIBUTE_UNUSED

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

static Function * getFunction(Constant *C)

#define DEBUG_TYPE

Provides analysis for querying information about KnownBits during GISel passes.

static unsigned computeNumSignBitsFromRangeMetadata(const GAnyLoad *Ld, unsigned TyBits)

Compute the known number of sign bits with attached range metadata in the memory operand.

static LLVM_ATTRIBUTE_UNUSED void dumpResult(const MachineInstr &MI, const KnownBits &Known, unsigned Depth)

Provides analysis for querying information about KnownBits during GISel passes.

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file describes how to lower LLVM code to machine code.

Class for arbitrary precision integers.

static APInt getAllOnes(unsigned numBits)

Return an APInt of a specified width with all bits set.

APInt zext(unsigned width) const

Zero extend to a new width.

static APInt getSignMask(unsigned BitWidth)

Get the SignMask for a specific bit width.

void setBitsFrom(unsigned loBit)

Set the top bits starting from loBit.

unsigned getBitWidth() const

Return the number of bits in the APInt.

unsigned getNumSignBits() const

Computes the number of leading bits of this APInt that are equal to its sign bit.

void clearLowBits(unsigned loBits)

Set bottom loBits bits to 0.

uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const

If this value is smaller than the specified limit, return it, otherwise return the limit value.

void setAllBits()

Set every bit to 1.

APInt shl(unsigned shiftAmt) const

Left-shift function.

static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)

Constructs an APInt value that has the bottom loBitsSet bits set.

void setLowBits(unsigned loBits)

Set the bottom loBits bits.

static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)

Constructs an APInt value that has a contiguous range of bits set.

Represent the analysis usage information of a pass.

void setPreservesAll()

Set by analyses that do not transform their input at all.

This class represents a range of values.

ConstantRange zeroExtend(uint32_t BitWidth) const

Return a new range in the specified integer type, which must be strictly larger than the current type...

APInt getSignedMin() const

Return the smallest signed value contained in the ConstantRange.

ConstantRange signExtend(uint32_t BitWidth) const

Return a new range in the specified integer type, which must be strictly larger than the current type...

APInt getSignedMax() const

Return the largest signed value contained in the ConstantRange.

uint32_t getBitWidth() const

Get the bit width of this ConstantRange.

bool isNonIntegralAddressSpace(unsigned AddrSpace) const

unsigned getIndexSizeInBits(unsigned AS) const

Size in bits of index used for address calculation in getelementptr.

Represents any generic load, including sign/zero extending variants.

const MDNode * getRanges() const

Returns the Ranges that describes the dereference.

To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

GISelKnownBits & get(MachineFunction &MF)

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const DataLayout & getDataLayout() const

virtual void computeKnownBitsImpl(Register R, KnownBits &Known, const APInt &DemandedElts, unsigned Depth=0)

Align computeKnownAlignment(Register R, unsigned Depth=0)

APInt getKnownOnes(Register R)

unsigned computeNumSignBits(Register R, const APInt &DemandedElts, unsigned Depth=0)

KnownBits getKnownBits(Register R)

bool maskedValueIsZero(Register Val, const APInt &Mask)

unsigned getMaxDepth() const

bool signBitIsZero(Register Op)

APInt getKnownZeroes(Register R)

constexpr unsigned getScalarSizeInBits() const

constexpr bool isValid() const

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

constexpr bool isPointer() const

constexpr unsigned getAddressSpace() const

constexpr bool isFixedVector() const

Returns true if the LLT is a fixed vector.

constexpr LLT getScalarType() const

TypeSize getValue() const

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

A description of a memory reference used in the backend.

LLT getMemoryType() const

Return the memory type of the memory reference.

const MDNode * getRanges() const

Return the range tag for the memory reference.

LocationSize getSizeInBits() const

Return the size in bits of the memory reference.

MachineOperand class - Representation of each machine instruction operand.

MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

LLT getType(Register Reg) const

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

BooleanContent getBooleanContents(bool isVec, bool isFloat) const

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...

@ ZeroOrOneBooleanContent

@ ZeroOrNegativeOneBooleanContent

virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const

Determine which of the bits of FrameIndex FIOp are known to be 0.

virtual unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const

This method can be implemented by targets that want to expose additional information about sign bits ...

virtual Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const

Determine the known alignment for the pointer value R.

virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

This is an optimization pass for GlobalISel generic memory operations.

int bit_width(T Value)

Returns the number of bits needed to represent Value if Value is nonzero.

unsigned Log2_64(uint64_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.

ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)

Parse out a conservative ConstantRange from !range metadata.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr unsigned BitWidth

static uint32_t extractBits(uint64_t Val, uint32_t Hi, uint32_t Lo)

const char * toString(DWARFSectionKind Kind)

void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)

Compute known bits from the range metadata.

This struct is a compact representation of a valid (non-zero power of two) alignment.

static KnownBits makeConstant(const APInt &C)

Create known bits from a known constant.

KnownBits anyextOrTrunc(unsigned BitWidth) const

Return known bits for an "any" extension or truncation of the value we're tracking.

KnownBits sextInReg(unsigned SrcBitWidth) const

Return known bits for a in-register sign extension of the value we're tracking.

static KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)

Compute known bits for smax(LHS, RHS).

bool isNonNegative() const

Returns true if this value is known to be non-negative.

static KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)

Compute known bits for ashr(LHS, RHS).

bool isUnknown() const

Returns true if we don't know any bits.

KnownBits byteSwap() const

unsigned countMaxPopulation() const

Returns the maximum number of bits that could be one.

KnownBits reverseBits() const

unsigned getBitWidth() const

Get the bit width of this value.

static KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)

Compute known bits for umax(LHS, RHS).

KnownBits zext(unsigned BitWidth) const

Return known bits for a zero extension of the value we're tracking.

static KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)

Compute known bits for lshr(LHS, RHS).

KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const

Return a subset of the known bits from [bitPosition,bitPosition+numBits).

KnownBits intersectWith(const KnownBits &RHS) const

Returns KnownBits information that is known to be true for both this and RHS.

KnownBits sext(unsigned BitWidth) const

Return known bits for a sign extension of the value we're tracking.

static KnownBits add(const KnownBits &LHS, const KnownBits &RHS, bool NSW=false, bool NUW=false)

Compute knownbits resulting from addition of LHS and RHS.

KnownBits zextOrTrunc(unsigned BitWidth) const

Return known bits for a zero extension or truncation of the value we're tracking.

APInt getMaxValue() const

Return the maximal unsigned value possible given these KnownBits.

static KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)

Compute known bits for smin(LHS, RHS).

APInt getMinValue() const

Return the minimal unsigned value possible given these KnownBits.

bool isNegative() const

Returns true if this value is known to be negative.

static KnownBits sub(const KnownBits &LHS, const KnownBits &RHS, bool NSW=false, bool NUW=false)

Compute knownbits resulting from subtraction of LHS and RHS.

unsigned countMaxLeadingZeros() const

Returns the maximum number of leading zero bits possible.

void insertBits(const KnownBits &SubBits, unsigned BitPosition)

Insert the bits from a smaller known bits starting at bitPosition.

static KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)

Compute known bits resulting from multiplying LHS and RHS.

KnownBits anyext(unsigned BitWidth) const

Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...

static KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)

Compute known bits for shl(LHS, RHS).

static KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)

Compute known bits for umin(LHS, RHS).