HexagonISelDAGToDAG.h Source File (original) (raw)

12#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H

13#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H

21#include

23namespace llvm {

33public:

47 updateAligna();

48 return true;

49 }

87 std::vector &OutOps) override;

115

116

117 #define GET_DAGISEL_DECL

118 #include "HexagonGenDAGISel.inc"

119

120private:

121

122

123

125

127 SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);

129 }

130

131 bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);

132 bool isAlignedMemNode(const MemSDNode *N) const;

133 bool isSmallStackStore(const StoreSDNode *N) const;

134 bool isPositiveHalfWord(const SDNode *N) const;

135 bool hasOneUse(const SDNode *N) const;

136

137

138 void PreprocessHvxISelDAG();

139 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);

140 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);

141 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);

142 void ppHoistZextI1(std::vector<SDNode*> &&Nodes);

143 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);

144

145 void SelectHvxExtractSubvector(SDNode *N);

146 void SelectHvxShuffle(SDNode *N);

147 void SelectHvxRor(SDNode *N);

148 void SelectHvxVAlign(SDNode *N);

149

150

151 void updateAligna();

152

156 int getWeight(SDNode *N);

157 int getHeight(SDNode *N);

159 SDValue factorOutPowerOf2(SDValue V, unsigned Power);

160 unsigned getUsesInFunction(const Value *V);

161 SDValue balanceSubTree(SDNode *N, bool Factorize = false);

162 void rebalanceAddressTrees();

163};

164

171}

172

173#endif

AMDGPU Register Bank Select

HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm, CodeGenOptLevel OptLevel)

static char ID

Definition HexagonISelDAGToDAG.h:167

void SelectAddSubCarry(SDNode *N)

void SelectConstant(SDNode *N)

void SelectIntrinsicWOChain(SDNode *N)

bool SelectNewCircIntrinsic(SDNode *IntN)

Generate a machine instruction node for the new circular buffer intrinsics.

bool tryLoadOfLoadIntrinsic(LoadSDNode *N)

void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)

void SelectExtractSubvector(SDNode *N)

void SelectVAlign(SDNode *N)

MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)

bool SelectAnyImm2(SDValue &N, SDValue &R)

bool SelectAnyImm(SDValue &N, SDValue &R)

void SelectV65GatherPred(SDNode *N)

bool SelectAnyImm0(SDValue &N, SDValue &R)

void SelectSHL(SDNode *N)

bool runOnMachineFunction(MachineFunction &MF) override

Definition HexagonISelDAGToDAG.h:41

void SelectIntrinsicWChain(SDNode *N)

void SelectV2Q(SDNode *N)

bool SelectAnyImm1(SDValue &N, SDValue &R)

void SelectConstantFP(SDNode *N)

bool DetectUseSxtw(SDValue &N, SDValue &R)

bool SelectBrevLdIntrinsic(SDNode *IntN)

void emitFunctionEntryCode() override

bool SelectAddrFI(SDValue &N, SDValue &R)

SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)

bool SelectAddrGP(SDValue &N, SDValue &R)

bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)

bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)

void SelectFrameIndex(SDNode *N)

bool SelectAnyImm3(SDValue &N, SDValue &R)

friend struct HvxSelector

Definition HexagonISelDAGToDAG.h:124

void SelectFDiv(SDNode *N)

void SelectStore(SDNode *N)

void SelectLoad(SDNode *N)

HexagonDAGToDAGISel()=delete

bool SelectAnyInt(SDValue &N, SDValue &R)

bool SelectAddrGA(SDValue &N, SDValue &R)

void PreprocessISelDAG() override

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...

void SelectTypecast(SDNode *N)

void SelectD2P(SDNode *N)

void SelectVAlignAddr(SDNode *N)

void SelectP2D(SDNode *N)

bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override

SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.

void SelectV65Gather(SDNode *N)

HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOptLevel OptLevel)

Definition HexagonISelDAGToDAG.h:36

bool ComplexPatternFuncMutatesDAG() const override

Return true if complex patterns for this target can mutate the DAG.

Definition HexagonISelDAGToDAG.h:51

void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)

void SelectHVXDualOutput(SDNode *N)

void SelectQ2V(SDNode *N)

const HexagonRegisterInfo & getRegisterInfo() const

const HexagonInstrInfo * getInstrInfo() const override

This class is used to represent ISD::LOAD nodes.

An SDNode that represents everything that will be needed to construct a MachineInstr.

This is an abstract virtual class for memory operations.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SelectionDAGISelLegacy(char &ID, std::unique_ptr< SelectionDAGISel > S)

SelectionDAGISel(TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)

virtual bool runOnMachineFunction(MachineFunction &mf)

This class is used to represent ISD::STORE nodes.

LLVM Value Representation.

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

DWARFExpression::Operation Op

This struct is a compact representation of a valid (non-zero power of two) alignment.