HexagonPeephole.cpp Source File (original) (raw)

51using namespace llvm;

53#define DEBUG_TYPE "hexagon-peephole"

57 cl::desc("Disable Peephole Optimization"));

60 cl::desc("Disable Optimization of PNotP"));

64 cl::desc("Disable Optimization of Sign/Zero Extends"));

69 cl::desc("Disable Optimization of extensions to i64."));

71namespace llvm {

74}

76namespace {

82 public:

83 static char ID;

86 }

91 return "Hexagon optimize redundant zero and size extends";

92 }

96 }

97 };

98}

100char HexagonPeephole::ID = 0;

101

102 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",

103 false, false)

104

106 if (skipFunction(MF.getFunction()))

107 return false;

108

109 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());

111 MRI = &MF.getRegInfo();

112

115

117

118

120 PeepholeMap.clear();

121 PeepholeDoubleRegsMap.clear();

122

123

125

126

128 assert(MI.getNumOperands() == 2);

131 Register DstReg = Dst.getReg();

132 Register SrcReg = Src.getReg();

133

135

136

137

138 PeepholeMap[DstReg] = SrcReg;

139 }

140 }

141

142

143

145 assert(MI.getNumOperands() == 3);

149 if (Src1.getImm() != 0)

150 continue;

151 Register DstReg = Dst.getReg();

153 PeepholeMap[DstReg] = SrcReg;

154 }

155

156

157

158

159

160

161 if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {

162 assert(MI.getNumOperands() == 3);

166 if (Src2.getImm() != 32)

167 continue;

168 Register DstReg = Dst.getReg();

170 PeepholeDoubleRegsMap[DstReg] =

171 std::make_pair(*&SrcReg, Hexagon::isub_hi);

172 }

173

174

175 if ( DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {

176 assert(MI.getNumOperands() == 2);

179 Register DstReg = Dst.getReg();

180 Register SrcReg = Src.getReg();

181

183

184

185

186 PeepholeMap[DstReg] = SrcReg;

187 }

188 }

189

190

191

193 assert(MI.getNumOperands() == 2);

196

197

198 if (Src.getSubReg() != Hexagon::isub_lo)

199 continue;

200

201 Register DstReg = Dst.getReg();

202 Register SrcReg = Src.getReg();

204

205 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {

206

207 MI.removeOperand(1);

209 } else {

211 PeepholeDoubleRegsMap.find(SrcReg);

212 if (DI != PeepholeDoubleRegsMap.end()) {

213 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;

214 MI.removeOperand(1);

216 PeepholeSrc.first, false , false ,

217 false , false , false ,

218 false , PeepholeSrc.second));

219 }

220 }

221 }

222 }

223

224

226 bool Done = false;

227 if (QII->isPredicated(MI)) {

231 if (RC0->getID() == Hexagon::PredRegsRegClassID) {

232

233

235

236 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {

237

238 MI.getOperand(0).setReg(PeepholeSrc);

239 MRI->clearKillFlags(PeepholeSrc);

240 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());

241 MI.setDesc(QII->get(NewOp));

243 }

244 }

245 }

246 }

247

249

250 unsigned Op = MI.getOpcode();

251 unsigned NewOp = 0;

252 unsigned PR = 1, S1 = 2, S2 = 3;

253

254 switch (Op) {

255 case Hexagon::C2_mux:

256 case Hexagon::C2_muxii:

257 NewOp = Op;

258 break;

259 case Hexagon::C2_muxri:

260 NewOp = Hexagon::C2_muxir;

261 break;

262 case Hexagon::C2_muxir:

263 NewOp = Hexagon::C2_muxri;

264 break;

265 }

266 if (NewOp) {

267 Register PSrc = MI.getOperand(PR).getReg();

268 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {

269 BuildMI(MBB, MI.getIterator(), MI.getDebugLoc(), QII->get(NewOp),

270 MI.getOperand(0).getReg())

272 .add(MI.getOperand(S2))

274 MRI->clearKillFlags(POrig);

275 MI.eraseFromParent();

276 }

277 }

278 }

279

280 }

281

282 }

283 }

284 return true;

285}

286

288 return new HexagonPeephole();

289}

unsigned const MachineRegisterInfo * MRI

This file defines the DenseMap class.

static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of extensions to i64."))

static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::desc("Disable Peephole Optimization"))

static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::desc("Disable Optimization of PNotP"))

static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of Sign/Zero Extends"))

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

Represent the analysis usage information of a pass.

This class represents an Operation in the Expression.

ValueT lookup(const_arg_type_t< KeyT > Val) const

lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...

iterator find(const_arg_type_t< KeyT > Val)

FunctionPass class - This class is used to implement most global optimizations.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

getReg - Returns the register number.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

StringRef - Represent a constant reference to a string, i.e.

unsigned getID() const

Return the register class ID number.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

FunctionPass * createHexagonPeephole()

void initializeHexagonPeepholePass(PassRegistry &)

DWARFExpression::Operation Op