LiveIntervals.cpp Source File (original) (raw)

40#include "llvm/Config/llvm-config.h"

51#include

52#include

53#include

54#include

55#include

56#include

58using namespace llvm;

60#define DEBUG_TYPE "regalloc"

69}

74 OS << "Live intervals for machine function: " << MF.getName() << ":\n";

77}

82 "Live Interval Analysis", false, false)

89 LIS.Indexes = &getAnalysis().getSI();

90 LIS.DomTree = &getAnalysis().getDomTree();

91 LIS.analyze(MF);

93 return false;

94}

96#ifndef NDEBUG

98 "precompute-phys-liveness", cl::Hidden,

99 cl::desc("Eagerly compute live intervals for all physreg units."));

100#else

102#endif

103

104namespace llvm {

105

109 "Use segment set for the computation of the live ranges of physregs."));

110

111}

112

122}

123

126}

127

129

130void LiveIntervals::clear() {

131

132 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)

134 VirtRegIntervals.clear();

135 RegMaskSlots.clear();

136 RegMaskBits.clear();

137 RegMaskBlocks.clear();

138

139 for (LiveRange *LR : RegUnitRanges)

140 delete LR;

141 RegUnitRanges.clear();

142

143

144 VNInfoAllocator.Reset();

145}

146

148 MF = &fn;

152

153 if (!LICalc)

154 LICalc = std::make_unique();

155

156

158

159 computeVirtRegs();

160 computeRegMasks();

161 computeLiveInRegUnits();

162

164

165

166 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)

168 }

169}

170

172 OS << "********** INTERVALS **********\n";

173

174

175 for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)

176 if (LiveRange *LR = RegUnitRanges[Unit])

178

179

180 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

184 }

185

186 OS << "RegMasks:";

188 OS << ' ' << Idx;

189 OS << '\n';

190

191 printInstrs(OS);

192}

193

194void LiveIntervals::printInstrs(raw_ostream &OS) const {

195 OS << "********** MACHINEINSTRS **********\n";

197}

198

199#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

201 printInstrs(dbgs());

202}

203#endif

204

205#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

207#endif

208

212}

213

214

215bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {

216 assert(LICalc && "LICalc not initialized.");

217 assert(LI.empty() && "Should only compute empty intervals.");

220 return computeDeadValues(LI, nullptr);

221}

222

223void LiveIntervals::computeVirtRegs() {

224 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

227 continue;

229 bool NeedSplit = computeVirtRegInterval(LI);

230 if (NeedSplit) {

233 }

234 }

235}

236

237void LiveIntervals::computeRegMasks() {

239

240

242 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];

243 RMB.first = RegMaskSlots.size();

244

245

249 }

250

251

252

253

258 }

259

262 if (!MO.isRegMask())

263 continue;

265 RegMaskBits.push_back(MO.getRegMask());

266 }

267 }

268

269

270

271

274 RegMaskSlots.push_back(

277 }

278

279

280 RMB.second = RegMaskSlots.size() - RMB.first;

281 }

282}

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {

299 assert(LICalc && "LICalc not initialized.");

301

302

303

304

305

306

307 bool IsReserved = false;

309 bool IsRootReserved = true;

312 LICalc->createDeadDefs(LR, Reg);

313

314

316 IsRootReserved = false;

317 }

318 IsReserved |= IsRootReserved;

319 }

321 "reserved computation mismatch");

322

323

324

325 if (!IsReserved) {

329 LICalc->extendToUses(LR, Reg);

330 }

331 }

332 }

333

334

337}

338

339

340

341

342void LiveIntervals::computeLiveInRegUnits() {

344 LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");

345

346

348

349

351

353 continue;

354

355

358 for (const auto &LI : MBB.liveins()) {

360 LiveRange *LR = RegUnitRanges[Unit];

361 if (!LR) {

362

365 }

367 (void)VNI;

369 }

370 }

372 }

373 LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");

374

375

376 for (unsigned Unit : NewRanges)

377 computeRegUnitRange(*RegUnitRanges[Unit], Unit);

378}

379

382 for (VNInfo *VNI : VNIs) {

384 continue;

387 }

388}

389

390void LiveIntervals::extendSegmentsToUses(LiveRange &Segments,

391 ShrinkToUsesWorkList &WorkList,

393

395

397

400 if (M.none())

401 return I;

403 if ((SR.LaneMask & M).any()) {

404 assert(SR.LaneMask == M && "Expecting lane masks to match exactly");

405 return SR;

406 }

407 }

409 };

410

412 const LiveRange &OldRange = getSubRange(LI, LaneMask);

413

414

415 while (!WorkList.empty()) {

417 VNInfo *VNI = WorkList.back().second;

418 WorkList.pop_back();

421

422

424 assert(ExtVNI == VNI && "Unexpected existing value number");

425 (void)ExtVNI;

426

427 if (!VNI->isPHIDef() || VNI->def != BlockStart ||

428 !UsedPHIs.insert(VNI).second)

429 continue;

430

432 if (!LiveOut.insert(Pred).second)

433 continue;

435

437 WorkList.push_back(std::make_pair(Stop, PVNI));

438 }

439 continue;

440 }

441

442

443 LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n');

445

446

448 if (!LiveOut.insert(Pred).second)

449 continue;

452 assert(OldVNI == VNI && "Wrong value out of predecessor");

453 (void)OldVNI;

454 WorkList.push_back(std::make_pair(Stop, VNI));

455 } else {

456#ifndef NDEBUG

457

458

460 "Missing value out of predecessor for main range");

464 "Missing value out of predecessor for subrange");

465#endif

466 }

467 }

468 }

469}

470

474 assert(li->reg().isVirtual() && "Can only shrink virtual registers");

475

476

477 bool NeedsCleanup = false;

480 if (S.empty())

481 NeedsCleanup = true;

482 }

483 if (NeedsCleanup)

485

486

488

489

492 if (UseMI.isDebugInstr() || UseMI .readsVirtualRegister(Reg))

493 continue;

497 if (!VNI) {

498

499

500

503 << "Warning: Instr claims to read non-existent value in "

504 << *li << '\n');

505 continue;

506 }

507

508

510 Idx = DefVNI->def;

511

512 WorkList.push_back(std::make_pair(Idx, VNI));

513 }

514

515

519

520

522

523

524 bool CanSeparate = computeDeadValues(*li, dead);

526 return CanSeparate;

527}

528

529bool LiveIntervals::computeDeadValues(LiveInterval &LI,

531 bool MayHaveSplitComponents = false;

532

535 continue;

538 assert(I != LI.end() && "Missing segment for VNI");

539

540

541

544 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {

546 MI->setRegisterDefReadUndef(VReg);

547 }

548 }

549

550 if (I->end != Def.getDeadSlot())

551 continue;

553

556 LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");

557 } else {

558

560 assert(MI && "No instruction defining live value");

561 MI->addRegisterDead(LI.reg(), TRI);

562

563 if (dead && MI->allDefsAreDead()) {

564 LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);

566 }

567 }

568 MayHaveSplitComponents = true;

569 }

570 return MayHaveSplitComponents;

571}

572

575 assert(Reg.isVirtual() && "Can only shrink virtual registers");

576

578

579

582

583 if (!MO.readsReg())

584 continue;

585

586 unsigned SubReg = MO.getSubReg();

589 if ((LaneMask & SR.LaneMask).none())

590 continue;

591 }

592

595 if (Idx == LastIdx)

596 continue;

597 LastIdx = Idx;

598

601

602

603 if (!VNI)

604 continue;

605

606

607

609 Idx = DefVNI->def;

610

611 WorkList.push_back(std::make_pair(Idx, VNI));

612 }

613

614

617 extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);

618

619

621

622

625 continue;

627 assert(Segment != nullptr && "Missing segment for VNI");

629 continue;

631

633 << " may separate interval\n");

636 }

637 }

638

640}

641

645 assert(LICalc && "LICalc not initialized.");

648 LICalc->extend(LR, Idx, 0, Undefs);

649}

650

655 if (!VNI)

656 return;

657

660

661

662 if (LRQ.endPoint() < MBBEnd) {

665 return;

666 }

667

668

670 if (EndPoints) EndPoints->push_back(MBBEnd);

671

672

673

674

676 VisitedTy Visited;

680 I != E;) {

682

683

685 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);

687 if (LRQ.valueIn() != VNI) {

688

689 I.skipChildren();

690 continue;

691 }

692

693

694 if (LRQ.endPoint() < MBBEnd) {

697 I.skipChildren();

698 continue;

699 }

700

701

703 if (EndPoints) EndPoints->push_back(MBBEnd);

704 ++I;

705 }

706 }

707}

708

709

710

711

712

714

716

717 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

720 continue;

723 continue;

724

725

727 if (!PhysReg)

728 continue;

729

730

731

735 auto [Unit, Bitmask] = *UI;

736

738 ArtificialLanes |= Bitmask;

740 if (RURange.empty())

741 continue;

742 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));

743 }

744

745

747 ++RI) {

748

749 if (RI->end.isBlock())

750 continue;

752 if ()

753 continue;

754

755

756

757

758

759

760

761

762

763 for (auto &RUP : RU) {

764 const LiveRange &RURange = *RUP.first;

766 if (I == RURange.end())

767 continue;

769 if (I == RURange.end() || I->start >= RI->end)

770 continue;

771

772 goto CancelKill;

773 }

774

776

777

778

779

780

781

782

783

784

785

786

789

790

791

792

793

794 DefinedLanesMask = ArtificialLanes;

797 if (Segment.start >= RI->end)

798 break;

799 if (Segment.end == RI->end) {

800 DefinedLanesMask |= SR.LaneMask;

801 break;

802 }

803 }

804 } else

806

807 bool IsFullWrite = false;

809 if (!MO.isReg() || MO.getReg() != Reg)

810 continue;

811 if (MO.isUse()) {

812

813 unsigned SubReg = MO.getSubReg();

816 if ((UseMask & ~DefinedLanesMask).any())

817 goto CancelKill;

818 } else if (MO.getSubReg() == 0) {

819

821 IsFullWrite = true;

822 }

823 }

824

825

826

827

828

829 if (!IsFullWrite) {

830

832 if (N != LI.end() && N->start == RI->end)

833 goto CancelKill;

834 }

835 }

836

837 MI->addRegisterKilled(Reg, nullptr);

838 continue;

839CancelKill:

840 MI->clearRegisterKills(Reg, nullptr);

841 }

842 }

843}

844

847 assert(!LI.empty() && "LiveInterval is empty.");

848

849

850

851

852

853

854

855

857 if (Start.isBlock())

858 return nullptr;

859

862 return nullptr;

863

864

865

868 return MBB1 == MBB2 ? MBB1 : nullptr;

869}

870

871bool

874 if (PHI->isUnused() || PHI ->isPHIDef())

875 continue;

877

879 return true;

882 return true;

883 }

884 return false;

885}

886

891 return getSpillWeight(isDef, isUse, MBFI, MI.getParent(), PSI);

892}

893

898 float Weight = isDef + isUse;

900

901

903 return Weight;

905}

906

916

917 return S;

918}

919

920

921

922

923

924

925

927 if (MI->getOpcode() != TargetOpcode::STATEPOINT)

928 return false;

931 return false;

936 return true;

937 }

938 return false;

939}

940

944 return false;

946

947

953 } else {

956 }

957

958

959

962

963

964 if (SlotI == SlotE)

965 return false;

966

967 bool Found = false;

968

969 auto unionBitMask = [&](unsigned Idx) {

970 if (!Found) {

971

972 UsableRegs.clear();

974 Found = true;

975 }

976

978 };

979 while (true) {

980 assert(*SlotI >= LiveI->start);

981

982 while (*SlotI < LiveI->end) {

983

984 unionBitMask(SlotI - Slots.begin());

985 if (++SlotI == SlotE)

986 return Found;

987 }

988

989 if (*SlotI == LiveI->end)

992 unionBitMask(SlotI++ - Slots.begin());

993

994

995 if (++LiveI == LiveE || SlotI == SlotE || *SlotI > LI.endIndex())

996 return Found;

997 while (LiveI->end < *SlotI)

998 ++LiveI;

999

1000 while (*SlotI < LiveI->start)

1001 if (++SlotI == SlotE)

1002 return Found;

1003 }

1004}

1005

1006

1007

1008

1009

1010

1012private:

1019 bool UpdateFlags;

1020

1021public:

1025 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),

1026 UpdateFlags(UpdateFlags) {}

1027

1028

1029

1030

1031

1033 if (UpdateFlags && MRI .isReservedRegUnit(Unit))

1036 }

1037

1038

1039

1041 LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": "

1042 << *MI);

1043 bool hasRegMask = false;

1045 if (MO.isRegMask())

1046 hasRegMask = true;

1047 if (!MO.isReg())

1048 continue;

1049 if (MO.isUse()) {

1050 if (!MO.readsReg())

1051 continue;

1052

1053

1054 MO.setIsKill(false);

1055 }

1056

1058 if (!Reg)

1059 continue;

1060 if (Reg.isVirtual()) {

1063 unsigned SubReg = MO.getSubReg();

1065 : MRI.getMaxLaneMaskForVReg(Reg);

1067 if ((S.LaneMask & LaneMask).none())

1068 continue;

1069 updateRange(S, Reg, S.LaneMask);

1070 }

1071 }

1073

1074

1075

1076

1077

1078

1080 unsigned SubReg = MO.getSubReg();

1082 : MRI.getMaxLaneMaskForVReg(Reg);

1084 if ((S.LaneMask & LaneMask).none() || LI.covers(S))

1085 continue;

1088 break;

1089 }

1090 }

1091

1092 continue;

1093 }

1094

1095

1096

1097 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))

1100 }

1101 if (hasRegMask)

1102 updateRegMaskSlots();

1103 }

1104

1105private:

1106

1107

1109 if (!Updated.insert(&LR).second)

1110 return;

1112 dbgs() << " ";

1113 if (Reg.isVirtual()) {

1115 if (LaneMask.any())

1117 } else {

1119 }

1120 dbgs() << ":\t" << LR << '\n';

1121 });

1123 handleMoveDown(LR);

1124 else

1125 handleMoveUp(LR, Reg, LaneMask);

1128 }

1129

1130

1131

1132 void handleMoveDown(LiveRange &LR) {

1134

1136

1137

1139 return;

1140

1142

1144

1146 return;

1147

1148

1149

1152 if (MOP.isReg() && MOP.isUse())

1153 MOP.setIsKill(false);

1154

1155

1159

1160

1163

1164 if (NewIdxIn == E ||

1168 }

1169

1170 OldIdxIn->end = Next->start;

1171 return;

1172 }

1173

1174

1175

1177 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());

1178

1179 if (!isKill)

1180 return;

1181

1182

1183 OldIdxOut = Next;

1185 return;

1186 } else {

1187 OldIdxOut = OldIdxIn;

1188 }

1189

1190

1191

1193 "No def?");

1194 VNInfo *OldIdxVNI = OldIdxOut->valno;

1195 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");

1196

1197

1198

1199 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());

1201 OldIdxVNI->def = NewIdxDef;

1202 OldIdxOut->start = OldIdxVNI->def;

1203 return;

1204 }

1205

1206

1207

1208

1209

1212 bool OldIdxDefIsDead = OldIdxOut->end.isDead();

1213 if (!OldIdxDefIsDead &&

1215

1217 if (OldIdxOut != LR.begin() &&

1219 OldIdxOut->start)) {

1220

1221

1223 DefVNI = OldIdxVNI;

1224 IPrev->end = OldIdxOut->end;

1225 } else {

1226

1228 assert(INext != E && "Must have following segment");

1229

1230

1231

1232

1233 DefVNI = OldIdxVNI;

1234 INext->start = OldIdxOut->end;

1235 INext->valno->def = INext->start;

1236 }

1237

1238 if (AfterNewIdx == E) {

1239

1240

1241

1242

1243 std::copy(std::next(OldIdxOut), E, OldIdxOut);

1244

1247 DefVNI);

1248 DefVNI->def = NewIdxDef;

1249

1251 Prev->end = NewIdxDef;

1252 } else {

1253

1254

1255

1256

1257 std::copy(std::next(OldIdxOut), std::next(AfterNewIdx), OldIdxOut);

1259

1261

1262

1264 *NewSegment = LiveRange::Segment(NewIdxDef, Prev->end, Prev->valno);

1265 Prev->valno->def = NewIdxDef;

1266

1268 DefVNI->def = Prev->start;

1269 } else {

1270

1271

1273 DefVNI->def = NewIdxDef;

1274 assert(DefVNI != AfterNewIdx->valno);

1275 }

1276 }

1277 return;

1278 }

1279

1280 if (AfterNewIdx != E &&

1282

1283

1284 assert(AfterNewIdx->valno != OldIdxVNI && "Multiple defs of value?");

1286 } else {

1287

1288

1289

1290

1291

1292 assert(AfterNewIdx != OldIdxOut && "Inconsistent iterators");

1293 std::copy(std::next(OldIdxOut), AfterNewIdx, OldIdxOut);

1294

1296 VNInfo *NewSegmentVNI = OldIdxVNI;

1297 NewSegmentVNI->def = NewIdxDef;

1299 NewSegmentVNI);

1300 }

1301 }

1302

1303

1304

1307

1309

1310

1312 return;

1313

1315

1317

1318

1319

1321 if (!isKill)

1322 return;

1323

1324

1325

1327 = std::max(OldIdxIn->start.getDeadSlot(),

1328 NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));

1329 OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, Reg, LaneMask);

1330

1331

1332 OldIdxOut = std::next(OldIdxIn);

1334 return;

1335 } else {

1336 OldIdxOut = OldIdxIn;

1337 OldIdxIn = OldIdxOut != LR.begin() ? std::prev(OldIdxOut) : E;

1338 }

1339

1340

1341

1343 "No def?");

1344 VNInfo *OldIdxVNI = OldIdxOut->valno;

1345 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");

1346 bool OldIdxDefIsDead = OldIdxOut->end.isDead();

1347

1348

1349 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());

1352 assert(NewIdxOut->valno != OldIdxVNI &&

1353 "Same value defined more than once?");

1354

1355 if (!OldIdxDefIsDead) {

1356

1357

1358 OldIdxVNI->def = NewIdxDef;

1359 OldIdxOut->start = NewIdxDef;

1361 } else {

1362

1364 }

1365 } else {

1366

1367

1368 if (!OldIdxDefIsDead) {

1369

1370 if (OldIdxIn != E &&

1372

1375 const SlotIndex SplitPos = NewIdxDef;

1376 OldIdxVNI = OldIdxIn->valno;

1377

1378 SlotIndex NewDefEndPoint = std::next(NewIdxIn)->end;

1380 if (OldIdxIn != LR.begin() &&

1382

1383

1384

1385

1386

1387

1388 NewDefEndPoint = std::min(OldIdxIn->start,

1389 std::next(NewIdxOut)->start);

1390 }

1391

1392

1393 OldIdxOut->valno->def = OldIdxIn->start;

1395 OldIdxOut->valno);

1396

1397

1398

1399

1400 std::copy_backward(NewIdxIn, OldIdxIn, OldIdxOut);

1401

1402

1406

1408 Next->valno);

1409

1411 Next->valno->def = SplitPos;

1412 } else {

1413

1414

1416 NewSegment->valno->def = SplitPos;

1417 }

1418 } else {

1419

1420 OldIdxOut->start = NewIdxDef;

1421 OldIdxVNI->def = NewIdxDef;

1423 OldIdxIn->end = NewIdxDef;

1424 }

1425 } else if (OldIdxIn != E

1428

1429

1430

1431

1432

1433

1434

1435

1436 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));

1437

1438

1439

1441 NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);

1443 NewIdxDef.getRegSlot(), (NewIdxOut + 1)->end, OldIdxVNI);

1444 OldIdxVNI->def = NewIdxDef;

1445

1446 for (auto *Idx = NewIdxOut + 2; Idx <= OldIdxOut; ++Idx)

1447 Idx->valno = OldIdxVNI;

1448

1449

1450

1453 if (MO->isReg() && !MO->isUse())

1454 MO->setIsDead(false);

1455 } else {

1456

1457

1458

1459

1460

1461 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));

1462

1464 VNInfo *NewSegmentVNI = OldIdxVNI;

1466 NewSegmentVNI);

1467 NewSegmentVNI->def = NewIdxDef;

1468 }

1469 }

1470 }

1471

1472 void updateRegMaskSlots() {

1475 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&

1476 "No RegMask at OldIdx.");

1478 assert((RI == LIS.RegMaskSlots.begin() ||

1480 "Cannot move regmask instruction above another call");

1481 assert((std::next(RI) == LIS.RegMaskSlots.end() ||

1483 "Cannot move regmask instruction below another call");

1484 }

1485

1486

1489 if (Reg.isVirtual()) {

1492 if (MO.isUndef())

1493 continue;

1494 unsigned SubReg = MO.getSubReg();

1495 if (SubReg != 0 && LaneMask.any()

1496 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())

1497 continue;

1498

1501 if (InstSlot > LastUse && InstSlot < OldIdx)

1503 }

1504 return LastUse;

1505 }

1506

1507

1508

1509 assert(Before < OldIdx && "Expected upwards move");

1512

1513

1514

1518 if (MI->getParent() == MBB)

1519 MII = MI;

1520

1522 while (MII != Begin) {

1523 if ((--MII)->isDebugOrPseudoInstr())

1524 continue;

1526

1527

1530

1531

1533 if (MO->isReg() && !MO->isUndef() && MO->getReg().isPhysical() &&

1534 TRI.hasRegUnit(MO->getReg(), Reg))

1535 return Idx.getRegSlot();

1536 }

1537

1539 }

1540};

1541

1543

1544

1545 assert((.isBundled() || MI.getOpcode() == TargetOpcode::BUNDLE) &&

1546 "Cannot move instruction in bundle");

1552 "Cannot handle moves across basic block boundaries.");

1553

1554 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);

1556}

1557

1559 bool UpdateFlags) {

1560 assert((BundleStart.getOpcode() == TargetOpcode::BUNDLE) &&

1561 "Bundle start is not a bundle");

1565

1567 I++;

1568 while (I != BundleEnd) {

1570 continue;

1574 I++;

1575 }

1576 for (SlotIndex OldIndex : ToProcess) {

1577 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);

1579 }

1580

1581

1584 if (!MO.isReg())

1585 continue;

1587 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) {

1591 MO.setIsDead();

1592 }

1593 }

1594}

1595

1603 if (LII != LR.end() && LII->start < EndIdx) {

1604 lastUseIdx = LII->end;

1605 } else if (LII == LR.begin()) {

1606

1607

1608 } else {

1609 --LII;

1610 }

1611

1613 --I;

1615 if (MI.isDebugOrPseudoInstr())

1616 continue;

1617

1621

1622

1623

1625 if (!MO.isReg() || MO.getReg() != Reg)

1626 continue;

1627

1628 unsigned SubReg = MO.getSubReg();

1630 if ((Mask & LaneMask).none())

1631 continue;

1632

1633 if (MO.isDef()) {

1634 if (!isStartValid) {

1635 if (LII->end.isDead()) {

1637 if (LII != LR.begin())

1638 --LII;

1639 } else {

1641 LII->valno->def = instrIdx.getRegSlot();

1642 if (MO.getSubReg() && !MO.isUndef())

1644 else

1646 continue;

1647 }

1648 }

1649

1650 if (!lastUseIdx.isValid()) {

1655 } else if (LII->start != instrIdx.getRegSlot()) {

1659 }

1660

1661 if (MO.getSubReg() && !MO.isUndef())

1663 else

1665 } else if (MO.isUse()) {

1666

1667

1668

1669 if (!isEndValid && !LII->end.isBlock())

1671 if (!lastUseIdx.isValid())

1673 }

1674 }

1675 }

1676

1678 if (!isStartValid && LII->end.isDead())

1680}

1681

1682void

1687

1688

1689 while (Begin != MBB->begin() && !Indexes->hasIndex(*std::prev(Begin)))

1690 --Begin;

1693

1697 else

1699

1701

1702

1705 --I;

1707 if (MI.isDebugOrPseudoInstr())

1708 continue;

1710 if (MO.isReg() && MO.getReg().isVirtual()) {

1712 if (MO.getSubReg() && hasInterval(Reg) &&

1713 MRI->shouldTrackSubRegLiveness(Reg)) {

1716

1717

1718

1720 } else if (MO.isDef()) {

1721

1722

1723 unsigned SubReg = MO.getSubReg();

1727 return SR.LaneMask == Mask;

1728 })) {

1730 }

1731 }

1732 }

1735

1737 }

1738 }

1739 }

1740 }

1741

1742 for (Register Reg : RegsToRepair) {

1743 if (!Reg.isVirtual())

1744 continue;

1745

1747

1749 continue;

1750

1752 repairOldRegInRange(Begin, End, EndIdx, S, Reg, S.LaneMask);

1754

1755 repairOldRegInRange(Begin, End, EndIdx, LI, Reg);

1756 }

1757}

1758

1764 }

1765}

1766

1768

1769

1771 if (VNI != nullptr) {

1774 }

1775

1776

1778 if (VNInfo *SVNI = S.getVNInfoAt(Pos))

1779 if (SVNI->def.getBaseIndex() == Pos.getBaseIndex())

1780 S.removeValNo(SVNI);

1781 }

1783}

1784

1788 unsigned NumComp = ConEQ.Classify(LI);

1789 if (NumComp <= 1)

1790 return;

1791 LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');

1793 for (unsigned I = 1; I < NumComp; ++I) {

1794 Register NewVReg = MRI->cloneVirtualRegister(Reg);

1797 }

1799}

1800

1802 assert(LICalc && "LICalc not initialized.");

1804 LICalc->constructMainRangeFromSubranges(LI);

1805}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

block Block Frequency Analysis

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is Live

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

A common definition of LaneBitmask for use in TableGen and CodeGen.

static cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))

static bool hasLiveThroughUse(const MachineInstr *MI, Register Reg)

Check whether use of reg in MI is live-through.

static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)

unsigned const TargetRegisterInfo * TRI

std::pair< uint64_t, uint64_t > Interval

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

Toolkit used by handleMove to trim or extend live intervals.

HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)

void updateAllRanges(MachineInstr *MI)

Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.

LiveRange * getRegUnitLI(unsigned Unit)

A container for analyses that lazily runs them and caches their results.

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequiredTransitiveID(char &ID)

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

void setPreservesCFG()

This function should be called by the pass, iff they do not:

AnalysisUsage & addRequiredTransitive()

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

void resize(unsigned N, bool t=false)

resize - Grow or shrink the bitvector.

void clear()

clear - Removes all bits from the bitvector.

void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.

void Reset()

Deallocate all but the current slab and reset the current pointer to the beginning of it,...

ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...

void Distribute(LiveInterval &LI, LiveInterval *LIV[], MachineRegisterInfo &MRI)

Distribute values in LI into a separate LiveIntervals for each connected component.

unsigned Classify(const LiveRange &LR)

Classify the values in LR into connected components.

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

void removeEmptySubRanges()

Removes all subranges without any segments (subranges without segments are not considered valid and s...

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const

For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...

Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

LiveIntervalsWrapperPass()

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)

Update live intervals for instructions in a range of iterators.

bool hasInterval(Register Reg) const

SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const

Return the first index in the given basic block.

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction associated with the given index.

bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const

Returns true if VNI is killed by any PHI-def values in LI.

bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)

Test if LI is live across any register mask instructions, and compute a bit mask of physical register...

void handleMove(MachineInstr &MI, bool UpdateFlags=false)

Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.

SlotIndexes * getSlotIndexes() const

ArrayRef< const uint32_t * > getRegMaskBits() const

Returns an array of register mask pointers corresponding to getRegMaskSlots().

LiveInterval & getOrCreateEmptyInterval(Register Reg)

Return an existing interval for Reg.

void addKillFlags(const VirtRegMap *)

Add kill flags to any instruction that kills a virtual register.

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

VNInfo::Allocator & getVNInfoAllocator()

ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const

Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).

SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const

Return the last index in the given basic block.

static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI, ProfileSummaryInfo *PSI=nullptr)

Calculate the spill weight to assign to a single instruction.

ArrayRef< SlotIndex > getRegMaskSlots() const

Returns a sorted array of slot indices of all instructions with register mask operands.

LiveRange & getRegUnit(unsigned Unit)

Return the live range for register unit Unit.

ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const

Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...

LiveRange * getCachedRegUnit(unsigned Unit)

Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...

LiveInterval & getInterval(Register Reg)

void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)

If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.

void removeInterval(Register Reg)

Interval removal.

void handleMoveIntoNewBundle(MachineInstr &BundleStart, bool UpdateFlags=false)

Update intervals of operands of all instructions in the newly created bundle specified by BundleStart...

MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const

If LI is confined to a single basic block, return a pointer to that block.

void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)

Remove value number and related live segments of LI and its subranges that start at position Pos.

LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)

Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.

bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)

After removing some uses of a register, shrink its live range to just the remaining uses.

void constructMainRangeFromSubranges(LiveInterval &LI)

For live interval LI with correct SubRanges construct matching information for the main live range.

LiveInterval & createEmptyInterval(Register Reg)

Interval creation.

void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)

Extend the live range LR to reach all points in Indices.

void print(raw_ostream &O) const

Implement the dump method.

void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)

Remove value numbers and related live segments starting at position Pos that are part of any liverang...

void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)

Split separate components in LiveInterval LI into separate intervals.

MachineBasicBlock * getMBBFromIndex(SlotIndex index) const

LiveInterval & createAndComputeVirtRegInterval(Register Reg)

Result of a LiveRange query.

VNInfo * valueOutOrDead() const

Returns the value alive at the end of the instruction, if any.

bool isDeadDef() const

Return true if this instruction has a dead def.

VNInfo * valueIn() const

Return the value that is live-in to the instruction.

VNInfo * valueDefined() const

Return the value defined by this instruction, if any.

SlotIndex endPoint() const

Return the end point of the last live range segment to interact with the instruction,...

static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)

A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...

This class represents the liveness of a register, stack slot, etc.

iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

iterator_range< vni_iterator > vnis()

VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)

createDeadDef - Make sure the range has a value defined at Def.

bool covers(const LiveRange &Other) const

Returns true if all segments of the Other live range are completely covered by this live range.

iterator advanceTo(iterator I, SlotIndex Pos)

advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...

void removeValNo(VNInfo *ValNo)

removeValNo - Remove all the segments defined by the specified value#.

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

VNInfo * getVNInfoBefore(SlotIndex Idx) const

getVNInfoBefore - Return the VNInfo that is live up to but not necessarily including Idx,...

bool verify() const

Walk the range and assert if any invariants fail to hold.

SlotIndex beginIndex() const

beginIndex - Return the lowest numbered slot covered.

SlotIndex endIndex() const

endNumber - return the maximum point of the range of the whole, exclusive.

bool hasAtLeastOneValue() const

VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)

getNextValue - Create a new value number and return it.

iterator FindSegmentContaining(SlotIndex Idx)

Return an iterator to the segment that contains the specified index, or end() if there is none.

void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)

Remove the specified interval from this live range.

void flushSegmentSet()

Flush segment set into the regular segment vector.

VNInfo * getVNInfoAt(SlotIndex Idx) const

getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.

iterator find(SlotIndex Pos)

find - Return an iterator pointing to the first segment that ends after Pos, or end().

MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.

bool isValid() const

Returns true if this iterator is not yet at the end.

MCRegUnitRootIterator enumerates the root registers of a register unit.

bool isValid() const

Check if the iterator is at the end of the list.

unsigned getNumRegUnits() const

Return the number of (native) register units in the target.

bool isArtificialRegUnit(MCRegUnit Unit) const

Returns true when the given register unit is considered artificial.

iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const

Returns an iterator range over all regunits for Reg.

iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, including Reg.

unsigned getNumRegs() const

Return the number of registers this target has (useful for sizing arrays holding per register informa...

Wrapper class representing physical registers. Should be passed by value.

bool isValid() const

isValid - Returns true until all the operands have been visited.

MIBundleOperands - Iterate over all operands in a bundle of machine instructions.

unsigned pred_size() const

bool isEHPad() const

Returns true if the block is a landing pad.

iterator_range< livein_iterator > liveins() const

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

bool livein_empty() const

const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const

Get the clobber mask for the start of this basic block.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

iterator_range< succ_iterator > successors()

iterator_range< pred_iterator > predecessors()

const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const

Get the clobber mask for the end of the basic block.

MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...

double getBlockFreqRelativeToEntryBlock(const MachineBasicBlock *MBB) const

Compute the frequency of the block, relative to the entry block.

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

unsigned getNumBlockIDs() const

getNumBlockIDs - Return the number of MBB ID's allocated.

void print(raw_ostream &OS, const SlotIndexes *=nullptr) const

print - Print out the MachineFunction in a format suitable for debugging to the specified stream.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

iterator_range< mop_iterator > operands()

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const

bool subRegLivenessEnabled() const

bool isReserved(MCRegister PhysReg) const

isReserved - Returns true when PhysReg is a reserved register.

bool reg_nodbg_empty(Register RegNo) const

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const

Returns true if liveness for register class RC should be tracked at the subregister level.

iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const

LaneBitmask getMaxLaneMaskForVReg(Register Reg) const

Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...

bool isReservedRegUnit(unsigned Unit) const

Returns true when the given register unit is considered reserved.

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

bool reg_empty(Register RegNo) const

reg_empty - Return true if there are no instructions using or defining the specified register (it may...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Analysis providing profile information.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

SlotIndex - An opaque wrapper around machine indexes.

static bool isSameInstr(SlotIndex A, SlotIndex B)

isSameInstr - Return true if A and B refer to the same instruction.

bool isBlock() const

isBlock - Returns true if this is a block boundary slot.

SlotIndex getDeadSlot() const

Returns the dead def kill slot for the current instruction.

static bool isEarlierInstr(SlotIndex A, SlotIndex B)

isEarlierInstr - Return true if A refers to an instruction earlier than B.

bool isValid() const

Returns true if this is a valid index.

static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)

Return true if A refers to the same instruction as B or an earlier one.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getPrevSlot() const

Returns the previous slot in the index list.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)

Insert the given machine instruction into the mapping.

void removeMachineInstrFromMaps(MachineInstr &MI, bool AllowBundled=false)

Removes machine instruction (bundle) MI from the mapping.

MachineBasicBlock * getMBBFromIndex(SlotIndex index) const

Returns the basic block which the given index falls in.

void repairIndexesInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End)

Repair indexes after adding and removing instructions.

const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const

Return the (start,end) range of the given basic block number.

SlotIndex getMBBEndIdx(unsigned Num) const

Returns the last index in the given basic block number.

SlotIndex getNextNonNullIndex(SlotIndex Index)

Returns the next non-null index, if one exists.

SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const

Returns the base index for the given instruction.

SlotIndex getMBBStartIdx(unsigned Num) const

Returns the first index in the given basic block number.

bool hasIndex(const MachineInstr &instr) const

Returns true if the given machine instr is mapped to an index, otherwise returns false.

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction for the given index, or null if the given index has no instruction associated...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void swap(SmallVectorImpl &RHS)

typename SuperClass::iterator iterator

void push_back(const T &Elt)

pointer data()

Return a pointer to the vector's buffer, even if empty().

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

MI-level Statepoint operands.

unsigned getNumDeoptArgsIdx() const

Get index of Number Deopt Arguments operand.

uint64_t getFlags() const

Return the statepoint flags.

unsigned getNumGCPtrIdx()

Get index of number of GC pointers.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const

Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...

LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const

Return a bitmask representing the parts of a register that are covered by SubIdx.

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual const TargetInstrInfo * getInstrInfo() const

VNInfo - Value Number Information.

void markUnused()

Mark this value as unused.

bool isUnused() const

Returns true if this value is unused.

unsigned id

The ID number of this value.

SlotIndex def

The index of the defining instruction.

bool isPHIDef() const

Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

self_iterator getIterator()

A range adaptor for a pair of iterators.

This class implements an extremely fast bulk output stream that can only output to a stream.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

Reg

All possible values of the reg field in the ModR/M byte.

initializer< Ty > init(const Ty &Val)

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)

void erase(Container &C, ValueType V)

Wrapper function to remove a value from a container:

char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)

Returns an iterator pointing beyond the bundle containing I.

const float huge_valf

Use this rather than HUGE_VALF; the latter causes warnings on MSVC.

cl::opt< bool > UseSegmentSetForPhysRegs

void initializeLiveIntervalsWrapperPassPass(PassRegistry &)

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

@ DeoptLiveIn

Mark the deopt arguments associated with the statepoint as only being "live-in".

iterator_range< MIBundleOperands > mi_bundle_ops(MachineInstr &MI)

df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

char & LiveIntervalsID

LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.

Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

A special type used by analysis passes to provide an address that identifies that particular analysis...

static constexpr LaneBitmask getAll()

constexpr bool any() const

static constexpr LaneBitmask getNone()

This represents a simple continuous liveness interval for a value.