LiveIntervals.cpp Source File (original) (raw)

40#include "llvm/Config/llvm-config.h"

51#include

52#include

53#include

54#include

55#include

56#include

58using namespace llvm;

60#define DEBUG_TYPE "regalloc"

74 OS << "Live intervals for machine function: " << MF.getName() << ":\n";

77}

82 "Live Interval Analysis", false, false)

91 LIS.analyze(MF);

93 return false;

94}

96#ifndef NDEBUG

98 "precompute-phys-liveness", cl::Hidden,

99 cl::desc("Eagerly compute live intervals for all physreg units."));

100#else

102#endif

103

107 "Use segment set for the computation of the live ranges of physregs."));

108

119

123

125

128 MachineFunctionAnalysisManager::Invalidator &Inv) {

130

132 return true;

133

134

135

138}

139

140void LiveIntervals::clear() {

141

142 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)

144 VirtRegIntervals.clear();

145 RegMaskSlots.clear();

146 RegMaskBits.clear();

147 RegMaskBlocks.clear();

148

149 for (LiveRange *LR : RegUnitRanges)

150 delete LR;

151 RegUnitRanges.clear();

152

153

154 VNInfoAllocator.Reset();

155}

156

158 MF = &fn;

162

163 if (!LICalc)

164 LICalc = std::make_unique();

165

166

167 VirtRegIntervals.resize(MRI->getNumVirtRegs());

168

169 computeVirtRegs();

170 computeRegMasks();

171 computeLiveInRegUnits();

172

174

175

176 for (MCRegUnit Unit : TRI->regunits())

178 }

179}

180

182 OS << "********** INTERVALS **********\n";

183

184

185 for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)

186 if (LiveRange *LR = RegUnitRanges[Unit])

187 OS << printRegUnit(static_cast(Unit), TRI) << ' ' << *LR

188 << '\n';

189

190

191 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

195 }

196

197 OS << "RegMasks:";

198 for (SlotIndex Idx : RegMaskSlots)

199 OS << ' ' << Idx;

200 OS << '\n';

201

202 printInstrs(OS);

203}

204

205void LiveIntervals::printInstrs(raw_ostream &OS) const {

206 OS << "********** MACHINEINSTRS **********\n";

207 MF->print(OS, Indexes);

208}

209

210#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

212 printInstrs(dbgs());

213}

214#endif

215

216#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

218#endif

219

223}

224

225

226bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {

227 assert(LICalc && "LICalc not initialized.");

228 assert(LI.empty() && "Should only compute empty intervals.");

230 LICalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg()));

231 return computeDeadValues(LI, nullptr);

232}

233

234void LiveIntervals::computeVirtRegs() {

235 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

237 if (MRI->reg_nodbg_empty(Reg))

238 continue;

240 bool NeedSplit = computeVirtRegInterval(LI);

241 if (NeedSplit) {

244 }

245 }

246}

247

248void LiveIntervals::computeRegMasks() {

249 RegMaskBlocks.resize(MF->getNumBlockIDs());

250

251

252 for (const MachineBasicBlock &MBB : *MF) {

253 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];

254 RMB.first = RegMaskSlots.size();

255

256

258 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));

259 RegMaskBits.push_back(Mask);

260 }

261

262

263

264

266 if (auto *Mask = TRI->getCustomEHPadPreservedMask(*MBB.getParent())) {

267 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));

268 RegMaskBits.push_back(Mask);

269 }

270

271 for (const MachineInstr &MI : MBB) {

272 for (const MachineOperand &MO : MI.operands()) {

273 if (!MO.isRegMask())

274 continue;

275 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());

276 RegMaskBits.push_back(MO.getRegMask());

277 }

278 }

279

280

281

282

285 RegMaskSlots.push_back(

286 Indexes->getInstructionIndex(MBB.back()).getRegSlot());

287 RegMaskBits.push_back(Mask);

288 }

289

290

291 RMB.second = RegMaskSlots.size() - RMB.first;

292 }

293}

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309void LiveIntervals::computeRegUnitRange(LiveRange &LR, MCRegUnit Unit) {

310 assert(LICalc && "LICalc not initialized.");

312

313

314

315

316

317

318 bool IsReserved = false;

319 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {

320 bool IsRootReserved = true;

321 for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {

322 if (!MRI->reg_empty(Reg))

323 LICalc->createDeadDefs(LR, Reg);

324

325

326 if (!MRI->isReserved(Reg))

327 IsRootReserved = false;

328 }

329 IsReserved |= IsRootReserved;

330 }

331 assert(IsReserved == MRI->isReservedRegUnit(Unit) &&

332 "reserved computation mismatch");

333

334

335

336 if (!IsReserved) {

337 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {

338 for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {

339 if (!MRI->reg_empty(Reg))

340 LICalc->extendToUses(LR, Reg);

341 }

342 }

343 }

344

345

348}

349

350

351

352

353void LiveIntervals::computeLiveInRegUnits() {

354 RegUnitRanges.resize(TRI->getNumRegUnits());

355 LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");

356

357

359

360

361 for (const MachineBasicBlock &MBB : *MF) {

362

364 continue;

365

366

367 SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);

369 for (const auto &LI : MBB.liveins()) {

370 for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {

371 LiveRange *LR = RegUnitRanges[static_cast<unsigned>(Unit)];

372 if (!LR) {

373

374 LR = RegUnitRanges[static_cast<unsigned>(Unit)] =

377 }

379 (void)VNI;

381 }

382 }

384 }

385 LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");

386

387

388 for (MCRegUnit Unit : NewRanges)

389 computeRegUnitRange(*RegUnitRanges[static_cast<unsigned>(Unit)], Unit);

390}

391

394 for (VNInfo *VNI : VNIs) {

396 continue;

399 }

400}

401

402void LiveIntervals::extendSegmentsToUses(LiveRange &Segments,

403 ShrinkToUsesWorkList &WorkList,

405

406 SmallPtrSet<VNInfo*, 8> UsedPHIs;

407

408 SmallPtrSet<const MachineBasicBlock*, 16> LiveOut;

409

410 auto getSubRange = [](const LiveInterval &I, LaneBitmask M)

412 if (M.none())

413 return I;

414 for (const LiveInterval::SubRange &SR : I.subranges()) {

415 if ((SR.LaneMask & M).any()) {

416 assert(SR.LaneMask == M && "Expecting lane masks to match exactly");

417 return SR;

418 }

419 }

421 };

422

424 const LiveRange &OldRange = getSubRange(LI, LaneMask);

425

426

427 while (!WorkList.empty()) {

428 SlotIndex Idx = WorkList.back().first;

429 VNInfo *VNI = WorkList.back().second;

430 WorkList.pop_back();

431 const MachineBasicBlock *MBB = Indexes->getMBBFromIndex(Idx.getPrevSlot());

432 SlotIndex BlockStart = Indexes->getMBBStartIdx(MBB);

433

434

435 if (VNInfo *ExtVNI = Segments.extendInBlock(BlockStart, Idx)) {

436 assert(ExtVNI == VNI && "Unexpected existing value number");

437 (void)ExtVNI;

438

439 if (!VNI->isPHIDef() || VNI->def != BlockStart ||

440 !UsedPHIs.insert(VNI).second)

441 continue;

442

443 for (const MachineBasicBlock *Pred : MBB->predecessors()) {

444 if (!LiveOut.insert(Pred).second)

445 continue;

446 SlotIndex Stop = Indexes->getMBBEndIdx(Pred);

447

449 WorkList.push_back(std::make_pair(Stop, PVNI));

450 }

451 continue;

452 }

453

454

455 LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n');

456 Segments.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));

457

458

459 for (const MachineBasicBlock *Pred : MBB->predecessors()) {

460 if (!LiveOut.insert(Pred).second)

461 continue;

462 SlotIndex Stop = Indexes->getMBBEndIdx(Pred);

464 assert(OldVNI == VNI && "Wrong value out of predecessor");

465 (void)OldVNI;

466 WorkList.push_back(std::make_pair(Stop, VNI));

467 } else {

468#ifndef NDEBUG

469

470

472 "Missing value out of predecessor for main range");

476 "Missing value out of predecessor for subrange");

477#endif

478 }

479 }

480 }

481}

482

486 assert(li->reg().isVirtual() && "Can only shrink virtual registers");

487

488

489 bool NeedsCleanup = false;

492 if (S.empty())

493 NeedsCleanup = true;

494 }

495 if (NeedsCleanup)

497

498

499 ShrinkToUsesWorkList WorkList;

500

501

504 if (UseMI.isDebugInstr() || UseMI .readsVirtualRegister(Reg))

505 continue;

509 if (!VNI) {

510

511

512

515 << "Warning: Instr claims to read non-existent value in "

516 << *li << '\n');

517 continue;

518 }

519

520

522 Idx = DefVNI->def;

523

524 WorkList.push_back(std::make_pair(Idx, VNI));

525 }

526

527

531

532

534

535

536 bool CanSeparate = computeDeadValues(*li, dead);

538 return CanSeparate;

539}

540

541bool LiveIntervals::computeDeadValues(LiveInterval &LI,

543 bool MayHaveSplitComponents = false;

544

547 continue;

550 assert(I != LI.end() && "Missing segment for VNI");

551

552

553

555 if (MRI->shouldTrackSubRegLiveness(VReg)) {

556 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {

558 MI->setRegisterDefReadUndef(VReg);

559 }

560 }

561

562 if (I->end != Def.getDeadSlot())

563 continue;

565

568 LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");

569 } else {

570

572 assert(MI && "No instruction defining live value");

573 MI->addRegisterDead(LI.reg(), TRI);

574

575 if (dead && MI->allDefsAreDead()) {

576 LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);

578 }

579 }

580 MayHaveSplitComponents = true;

581 }

582 return MayHaveSplitComponents;

583}

584

587 assert(Reg.isVirtual() && "Can only shrink virtual registers");

588

589 ShrinkToUsesWorkList WorkList;

590

591

593 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {

594

595 if (!MO.readsReg())

596 continue;

597

598 unsigned SubReg = MO.getSubReg();

601 if ((LaneMask & SR.LaneMask).none())

602 continue;

603 }

604

607 if (Idx == LastIdx)

608 continue;

609 LastIdx = Idx;

610

613

614

615 if (!VNI)

616 continue;

617

618

619

621 Idx = DefVNI->def;

622

623 WorkList.push_back(std::make_pair(Idx, VNI));

624 }

625

626

629 extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);

630

631

633

634

637 continue;

639 assert(Segment != nullptr && "Missing segment for VNI");

641 continue;

643

645 << " may separate interval\n");

648 }

649 }

650

652}

653

657 assert(LICalc && "LICalc not initialized.");

660 LICalc->extend(LR, Idx, 0, Undefs);

661}

662

666

667

668

670 if (!VNI)

671 return;

672

674 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);

675

676

677 if (LRQ.endPoint() < MBBEnd) {

680 return;

681 }

682

683

685 if (EndPoints) EndPoints->push_back(MBBEnd);

686

687

688

689

691 VisitedTy Visited;

695 I != E;) {

697

698

700 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);

702 if (LRQ.valueIn() != VNI) {

703

704 I.skipChildren();

705 continue;

706 }

707

708

709 if (LRQ.endPoint() < MBBEnd) {

712 I.skipChildren();

713 continue;

714 }

715

716

718 if (EndPoints) EndPoints->push_back(MBBEnd);

719 ++I;

720 }

721 }

722}

723

724

725

726

727

729

731

732 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

734 if (MRI->reg_nodbg_empty(Reg))

735 continue;

738 continue;

739

740

742 if (!PhysReg)

743 continue;

744

745

746

750 auto [Unit, Bitmask] = *UI;

751

752 if (TRI->isArtificialRegUnit(Unit))

753 ArtificialLanes |= Bitmask;

755 if (RURange.empty())

756 continue;

757 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));

758 }

759

760

762 ++RI) {

763

764 if (RI->end.isBlock())

765 continue;

767 if ()

768 continue;

769

770

771

772

773

774

775

776

777

778 for (auto &RUP : RU) {

779 const LiveRange &RURange = *RUP.first;

781 if (I == RURange.end())

782 continue;

784 if (I == RURange.end() || I->start >= RI->end)

785 continue;

786

787 goto CancelKill;

788 }

789

790 if (MRI->subRegLivenessEnabled()) {

791

792

793

794

795

796

797

798

799

800

801

804

805

806

807

808

809 DefinedLanesMask = ArtificialLanes;

812 if (Segment.start >= RI->end)

813 break;

814 if (Segment.end == RI->end) {

815 DefinedLanesMask |= SR.LaneMask;

816 break;

817 }

818 }

819 } else

821

822 bool IsFullWrite = false;

824 if (!MO.isReg() || MO.getReg() != Reg)

825 continue;

826 if (MO.isUse()) {

827

828 unsigned SubReg = MO.getSubReg();

830 : MRI->getMaxLaneMaskForVReg(Reg);

831 if ((UseMask & ~DefinedLanesMask).any())

832 goto CancelKill;

833 } else if (MO.getSubReg() == 0) {

834

836 IsFullWrite = true;

837 }

838 }

839

840

841

842

843

844 if (!IsFullWrite) {

845

847 if (N != LI.end() && N->start == RI->end)

848 goto CancelKill;

849 }

850 }

851

852 MI->addRegisterKilled(Reg, nullptr);

853 continue;

854CancelKill:

855 MI->clearRegisterKills(Reg, nullptr);

856 }

857 }

858}

859

862 assert(!LI.empty() && "LiveInterval is empty.");

863

864

865

866

867

868

869

870

872 if (Start.isBlock())

873 return nullptr;

874

877 return nullptr;

878

879

880

883 return MBB1 == MBB2 ? MBB1 : nullptr;

884}

885

886bool

889 if (PHI->isUnused() || PHI ->isPHIDef())

890 continue;

892

894 return true;

896 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(Pred)))

897 return true;

898 }

899 return false;

900}

901

908

913 float Weight = isDef + isUse;

914 const auto *MF = MBB->getParent();

915

916

918 return Weight;

920}

921

934

935

936

937

938

939

940

942 if (MI->getOpcode() != TargetOpcode::STATEPOINT)

943 return false;

946 return false;

948 ++Idx) {

951 return true;

952 }

953 return false;

954}

955

959 return false;

961

962

968 } else {

971 }

972

973

974

977

978

979 if (SlotI == SlotE)

980 return false;

981

982 bool Found = false;

983

984 auto unionBitMask = [&](unsigned Idx) {

985 if (!Found) {

986

987 UsableRegs.clear();

988 UsableRegs.resize(TRI->getNumRegs(), true);

989 Found = true;

990 }

991

993 };

994 while (true) {

995 assert(*SlotI >= LiveI->start);

996

997 while (*SlotI < LiveI->end) {

998

999 unionBitMask(SlotI - Slots.begin());

1000 if (++SlotI == SlotE)

1001 return Found;

1002 }

1003

1004 if (*SlotI == LiveI->end)

1007 unionBitMask(SlotI++ - Slots.begin());

1008

1009

1010 if (++LiveI == LiveE || SlotI == SlotE || *SlotI > LI.endIndex())

1011 return Found;

1012 while (LiveI->end < *SlotI)

1013 ++LiveI;

1014

1015 while (*SlotI < LiveI->start)

1016 if (++SlotI == SlotE)

1017 return Found;

1018 }

1019}

1020

1021

1022

1023

1024

1025

1027private:

1028 LiveIntervals& LIS;

1034 bool UpdateFlags;

1035

1036public:

1040 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),

1041 UpdateFlags(UpdateFlags) {}

1042

1043

1044

1045

1046

1048 if (UpdateFlags && !MRI.isReservedRegUnit(Unit))

1049 return &LIS.getRegUnit(Unit);

1050 return LIS.getCachedRegUnit(Unit);

1051 }

1052

1053

1054

1056 LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": "

1057 << *MI);

1058 bool hasRegMask = false;

1060 if (MO.isRegMask())

1061 hasRegMask = true;

1062 if (!MO.isReg())

1063 continue;

1064 if (MO.isUse()) {

1065 if (!MO.readsReg())

1066 continue;

1067

1068

1069 MO.setIsKill(false);

1070 }

1071

1073 if (!Reg)

1074 continue;

1075 if (Reg.isVirtual()) {

1078 unsigned SubReg = MO.getSubReg();

1080 : MRI.getMaxLaneMaskForVReg(Reg);

1082 if ((S.LaneMask & LaneMask).none())

1083 continue;

1085 }

1086 }

1088

1089

1090

1091

1092

1093

1095 unsigned SubReg = MO.getSubReg();

1097 : MRI.getMaxLaneMaskForVReg(Reg);

1099 if ((S.LaneMask & LaneMask).none() || LI.covers(S))

1100 continue;

1102 LIS.constructMainRangeFromSubranges(LI);

1103 break;

1104 }

1105 }

1106

1107 continue;

1108 }

1109

1110

1111

1112 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))

1115 }

1116 if (hasRegMask)

1117 updateRegMaskSlots();

1118 }

1119

1120private:

1121

1122

1125 if (!Updated.insert(&LR).second)

1126 return;

1128 dbgs() << " ";

1131 if (LaneMask.any())

1133 } else {

1135 }

1136 dbgs() << ":\t" << LR << '\n';

1137 });

1139 handleMoveDown(LR);

1140 else

1141 handleMoveUp(LR, VRegOrUnit, LaneMask);

1144 }

1145

1146

1147

1148 void handleMoveDown(LiveRange &LR) {

1150

1152

1153

1155 return;

1156

1158

1160

1162 return;

1163

1164

1165

1166 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))

1167 for (MachineOperand &MOP : mi_bundle_ops(*KillMI))

1168 if (MOP.isReg() && MOP.isUse())

1169 MOP.setIsKill(false);

1170

1171

1175

1176

1179

1180 if (NewIdxIn == E ||

1183 Prev->end = NewIdx.getRegSlot();

1184 }

1185

1186 OldIdxIn->end = Next->start;

1187 return;

1188 }

1189

1190

1191

1193 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());

1194

1195 if (!isKill)

1196 return;

1197

1198

1199 OldIdxOut = Next;

1201 return;

1202 } else {

1203 OldIdxOut = OldIdxIn;

1204 }

1205

1206

1207

1209 "No def?");

1210 VNInfo *OldIdxVNI = OldIdxOut->valno;

1211 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");

1212

1213

1214

1215 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());

1217 OldIdxVNI->def = NewIdxDef;

1218 OldIdxOut->start = OldIdxVNI->def;

1219 return;

1220 }

1221

1222

1223

1224

1225

1227 = LR.advanceTo(OldIdxOut, NewIdx.getRegSlot());

1228 bool OldIdxDefIsDead = OldIdxOut->end.isDead();

1229 if (!OldIdxDefIsDead &&

1231

1232 VNInfo *DefVNI;

1233 if (OldIdxOut != LR.begin() &&

1235 OldIdxOut->start)) {

1236

1237

1239 DefVNI = OldIdxVNI;

1240 IPrev->end = OldIdxOut->end;

1241 } else {

1242

1244 assert(INext != E && "Must have following segment");

1245

1246

1247

1248

1249 DefVNI = OldIdxVNI;

1250 INext->start = OldIdxOut->end;

1251 INext->valno->def = INext->start;

1252 }

1253

1254 if (AfterNewIdx == E) {

1255

1256

1257

1258

1259 std::copy(std::next(OldIdxOut), E, OldIdxOut);

1260

1262 *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),

1263 DefVNI);

1264 DefVNI->def = NewIdxDef;

1265

1267 Prev->end = NewIdxDef;

1268 } else {

1269

1270

1271

1272

1273 std::copy(std::next(OldIdxOut), std::next(AfterNewIdx), OldIdxOut);

1275

1277

1278

1280 *NewSegment = LiveRange::Segment(NewIdxDef, Prev->end, Prev->valno);

1281 Prev->valno->def = NewIdxDef;

1282

1283 *Prev = LiveRange::Segment(Prev->start, NewIdxDef, DefVNI);

1284 DefVNI->def = Prev->start;

1285 } else {

1286

1287

1288 *Prev = LiveRange::Segment(NewIdxDef, AfterNewIdx->start, DefVNI);

1289 DefVNI->def = NewIdxDef;

1290 assert(DefVNI != AfterNewIdx->valno);

1291 }

1292 }

1293 return;

1294 }

1295

1296 if (AfterNewIdx != E &&

1298

1299

1300 assert(AfterNewIdx->valno != OldIdxVNI && "Multiple defs of value?");

1302 } else {

1303

1304

1305

1306

1307

1308 assert(AfterNewIdx != OldIdxOut && "Inconsistent iterators");

1309 std::copy(std::next(OldIdxOut), AfterNewIdx, OldIdxOut);

1310

1312 VNInfo *NewSegmentVNI = OldIdxVNI;

1313 NewSegmentVNI->def = NewIdxDef;

1314 *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),

1315 NewSegmentVNI);

1316 }

1317 }

1318

1319

1320

1321 void handleMoveUp(LiveRange &LR, VirtRegOrUnit VRegOrUnit,

1322 LaneBitmask LaneMask) {

1324

1326

1327

1329 return;

1330

1332

1334

1335

1336

1338 if (!isKill)

1339 return;

1340

1341

1342

1343 SlotIndex DefBeforeOldIdx

1344 = std::max(OldIdxIn->start.getDeadSlot(),

1345 NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));

1346 OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, VRegOrUnit, LaneMask);

1347

1348

1349 OldIdxOut = std::next(OldIdxIn);

1351 return;

1352 } else {

1353 OldIdxOut = OldIdxIn;

1354 OldIdxIn = OldIdxOut != LR.begin() ? std::prev(OldIdxOut) : E;

1355 }

1356

1357

1358

1360 "No def?");

1361 VNInfo *OldIdxVNI = OldIdxOut->valno;

1362 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");

1363 bool OldIdxDefIsDead = OldIdxOut->end.isDead();

1364

1365

1366 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());

1369 assert(NewIdxOut->valno != OldIdxVNI &&

1370 "Same value defined more than once?");

1371

1372 if (!OldIdxDefIsDead) {

1373

1374

1375 OldIdxVNI->def = NewIdxDef;

1376 OldIdxOut->start = NewIdxDef;

1378 } else {

1379

1381 }

1382 } else {

1383

1384

1385 if (!OldIdxDefIsDead) {

1386

1387 if (OldIdxIn != E &&

1389

1391 assert(NewIdxIn == LR.find(NewIdx.getBaseIndex()));

1392 const SlotIndex SplitPos = NewIdxDef;

1393 OldIdxVNI = OldIdxIn->valno;

1394

1395 SlotIndex NewDefEndPoint = std::next(NewIdxIn)->end;

1397 if (OldIdxIn != LR.begin() &&

1399

1400

1401

1402

1403

1404

1405 NewDefEndPoint = std::min(OldIdxIn->start,

1406 std::next(NewIdxOut)->start);

1407 }

1408

1409

1410 OldIdxOut->valno->def = OldIdxIn->start;

1411 *OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,

1412 OldIdxOut->valno);

1413

1414

1415

1416

1417 std::copy_backward(NewIdxIn, OldIdxIn, OldIdxOut);

1418

1419

1423

1424 *NewSegment = LiveRange::Segment(Next->start, SplitPos,

1425 Next->valno);

1426

1427 *Next = LiveRange::Segment(SplitPos, NewDefEndPoint, OldIdxVNI);

1428 Next->valno->def = SplitPos;

1429 } else {

1430

1431

1432 *NewSegment = LiveRange::Segment(SplitPos, Next->start, OldIdxVNI);

1433 NewSegment->valno->def = SplitPos;

1434 }

1435 } else {

1436

1437 OldIdxOut->start = NewIdxDef;

1438 OldIdxVNI->def = NewIdxDef;

1440 OldIdxIn->end = NewIdxDef;

1441 }

1442 } else if (OldIdxIn != E

1445

1446

1447

1448

1449

1450

1451

1452

1453 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));

1454

1455

1456

1457 *NewIdxOut = LiveRange::Segment(

1458 NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);

1459 *(NewIdxOut + 1) = LiveRange::Segment(

1460 NewIdxDef.getRegSlot(), (NewIdxOut + 1)->end, OldIdxVNI);

1461 OldIdxVNI->def = NewIdxDef;

1462

1463 for (auto *Idx = NewIdxOut + 2; Idx <= OldIdxOut; ++Idx)

1464 Idx->valno = OldIdxVNI;

1465

1466

1467

1468 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(NewIdx))

1469 for (MIBundleOperands MO(*KillMI); MO.isValid(); ++MO)

1470 if (MO->isReg() && !MO->isUse())

1471 MO->setIsDead(false);

1472 } else {

1473

1474

1475

1476

1477

1478 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));

1479

1481 VNInfo *NewSegmentVNI = OldIdxVNI;

1482 *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),

1483 NewSegmentVNI);

1484 NewSegmentVNI->def = NewIdxDef;

1485 }

1486 }

1487 }

1488

1489 void updateRegMaskSlots() {

1492 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&

1493 "No RegMask at OldIdx.");

1494 *RI = NewIdx.getRegSlot();

1495 assert((RI == LIS.RegMaskSlots.begin() ||

1497 "Cannot move regmask instruction above another call");

1498 assert((std::next(RI) == LIS.RegMaskSlots.end() ||

1500 "Cannot move regmask instruction below another call");

1501 }

1502

1503

1504 SlotIndex findLastUseBefore(SlotIndex Before, VirtRegOrUnit VRegOrUnit,

1505 LaneBitmask LaneMask) {

1507 SlotIndex LastUse = Before;

1508 for (MachineOperand &MO :

1509 MRI.use_nodbg_operands(VRegOrUnit.asVirtualReg())) {

1510 if (MO.isUndef())

1511 continue;

1512 unsigned SubReg = MO.getSubReg();

1513 if (SubReg != 0 && LaneMask.any()

1514 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())

1515 continue;

1516

1517 const MachineInstr &MI = *MO.getParent();

1518 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);

1519 if (InstSlot > LastUse && InstSlot < OldIdx)

1521 }

1522 return LastUse;

1523 }

1524

1525

1526

1527 assert(Before < OldIdx && "Expected upwards move");

1528 SlotIndexes *Indexes = LIS.getSlotIndexes();

1530

1531

1532

1536 if (MI->getParent() == MBB)

1537 MII = MI;

1538

1540 while (MII != Begin) {

1541 if ((--MII)->isDebugOrPseudoInstr())

1542 continue;

1544

1545

1547 return Before;

1548

1549

1550 for (MIBundleOperands MO(*MII); MO.isValid(); ++MO)

1551 if (MO->isReg() && !MO->isUndef() && MO->getReg().isPhysical() &&

1552 TRI.hasRegUnit(MO->getReg(), VRegOrUnit.asMCRegUnit()))

1554 }

1555

1556 return Before;

1557 }

1558};

1559

1561

1562

1563 assert((.isBundled() || MI.getOpcode() == TargetOpcode::BUNDLE) &&

1564 "Cannot move instruction in bundle");

1565 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);

1566 Indexes->removeMachineInstrFromMaps(MI);

1567 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);

1570 "Cannot handle moves across basic block boundaries.");

1571

1572 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);

1574}

1575

1577 bool UpdateFlags) {

1578 assert((BundleStart.getOpcode() == TargetOpcode::BUNDLE) &&

1579 "Bundle start is not a bundle");

1581 const SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(BundleStart);

1583

1585 I++;

1586 while (I != BundleEnd) {

1587 if (!Indexes->hasIndex(*I))

1588 continue;

1589 SlotIndex OldIndex = Indexes->getInstructionIndex(*I, true);

1591 Indexes->removeMachineInstrFromMaps(*I, true);

1592 I++;

1593 }

1594 for (SlotIndex OldIndex : ToProcess) {

1595 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);

1597 }

1598

1599

1602 if (!MO.isReg())

1603 continue;

1605 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) {

1609 MO.setIsDead();

1610 }

1611 }

1612}

1613

1621 if (LII != LR.end() && LII->start < EndIdx) {

1622 lastUseIdx = LII->end;

1623 } else if (LII == LR.begin()) {

1624

1625

1626 } else {

1627 --LII;

1628 }

1629

1631 --I;

1632 MachineInstr &MI = *I;

1633 if (MI.isDebugOrPseudoInstr())

1634 continue;

1635

1639

1640

1641

1642 for (const MachineOperand &MO : MI.operands()) {

1643 if (!MO.isReg() || MO.getReg() != Reg)

1644 continue;

1645

1646 unsigned SubReg = MO.getSubReg();

1647 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);

1648 if ((Mask & LaneMask).none())

1649 continue;

1650

1651 if (MO.isDef()) {

1652 if (!isStartValid) {

1653 if (LII->end.isDead()) {

1655 if (LII != LR.begin())

1656 --LII;

1657 } else {

1659 LII->valno->def = instrIdx.getRegSlot();

1660 if (MO.getSubReg() && !MO.isUndef())

1662 else

1663 lastUseIdx = SlotIndex();

1664 continue;

1665 }

1666 }

1667

1668 if (!lastUseIdx.isValid()) {

1670 LiveRange::Segment S(instrIdx.getRegSlot(),

1673 } else if (LII->start != instrIdx.getRegSlot()) {

1675 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);

1677 }

1678

1679 if (MO.getSubReg() && !MO.isUndef())

1681 else

1682 lastUseIdx = SlotIndex();

1683 } else if (MO.isUse()) {

1684

1685

1686

1687 if (!isEndValid && !LII->end.isBlock())

1689 if (!lastUseIdx.isValid())

1691 }

1692 }

1693 }

1694

1696 if (!isStartValid && LII->end.isDead())

1698}

1699

1700void

1705

1706

1707 while (Begin != MBB->begin() && !Indexes->hasIndex(*std::prev(Begin)))

1708 --Begin;

1709 while (End != MBB->end() && !Indexes->hasIndex(*End))

1710 ++End;

1711

1713 if (End == MBB->end())

1715 else

1717

1718 Indexes->repairIndexesInRange(MBB, Begin, End);

1719

1720

1723 --I;

1725 if (MI.isDebugOrPseudoInstr())

1726 continue;

1728 if (MO.isReg() && MO.getReg().isVirtual()) {

1730 if (MO.getSubReg() && hasInterval(Reg) &&

1731 MRI->shouldTrackSubRegLiveness(Reg)) {

1734

1735

1736

1738 } else if (MO.isDef()) {

1739

1740

1741 unsigned SubReg = MO.getSubReg();

1745 return SR.LaneMask == Mask;

1746 })) {

1748 }

1749 }

1750 }

1753

1755 }

1756 }

1757 }

1758 }

1759

1760 for (Register Reg : RegsToRepair) {

1761 if (!Reg.isVirtual())

1762 continue;

1763

1765

1767 continue;

1768

1770 repairOldRegInRange(Begin, End, EndIdx, S, Reg, S.LaneMask);

1772

1773 repairOldRegInRange(Begin, End, EndIdx, LI, Reg);

1774 }

1775}

1776

1778 for (MCRegUnit Unit : TRI->regunits(Reg)) {

1782 }

1783}

1784

1786

1787

1789 if (VNI != nullptr) {

1792 }

1793

1794

1796 if (VNInfo *SVNI = S.getVNInfoAt(Pos))

1797 if (SVNI->def.getBaseIndex() == Pos.getBaseIndex())

1798 S.removeValNo(SVNI);

1799 }

1801}

1802

1806 unsigned NumComp = ConEQ.Classify(LI);

1807 if (NumComp <= 1)

1808 return;

1809 LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');

1811 for (unsigned I = 1; I < NumComp; ++I) {

1812 Register NewVReg = MRI->cloneVirtualRegister(Reg);

1815 }

1817}

1818

1820 assert(LICalc && "LICalc not initialized.");

1822 LICalc->constructMainRangeFromSubranges(LI);

1823}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

A common definition of LaneBitmask for use in TableGen and CodeGen.

static cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))

static bool hasLiveThroughUse(const MachineInstr *MI, Register Reg)

Check whether use of reg in MI is live-through.

Definition LiveIntervals.cpp:941

static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)

Definition LiveIntervals.cpp:392

std::pair< uint64_t, uint64_t > Interval

Promote Memory to Register

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

SI Optimize VGPR LiveRange

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

Toolkit used by handleMove to trim or extend live intervals.

Definition LiveIntervals.cpp:1026

HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)

Definition LiveIntervals.cpp:1037

LiveRange * getRegUnitLI(MCRegUnit Unit)

Definition LiveIntervals.cpp:1047

void updateAllRanges(MachineInstr *MI)

Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.

Definition LiveIntervals.cpp:1055

This templated class represents "all analyses that operate over " (e....

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

LLVM_ABI AnalysisUsage & addRequiredTransitiveID(char &ID)

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

AnalysisUsage & addRequiredTransitive()

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

void resize(unsigned N, bool t=false)

resize - Grow or shrink the bitvector.

void clear()

clear - Removes all bits from the bitvector.

void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.

ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...

LLVM_ABI void Distribute(LiveInterval &LI, LiveInterval *LIV[], MachineRegisterInfo &MRI)

Distribute values in LI into a separate LiveIntervals for each connected component.

LLVM_ABI unsigned Classify(const LiveRange &LR)

Classify the values in LR into connected components.

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

LLVM_ABI void removeEmptySubRanges()

Removes all subranges without any segments (subranges without segments are not considered valid and s...

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

LLVM_ABI void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const

For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...

LLVM_ABI Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition LiveIntervals.cpp:65

LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition LiveIntervals.cpp:72

bool runOnMachineFunction(MachineFunction &) override

Pass entry point; Calculates LiveIntervals.

Definition LiveIntervals.cpp:88

LiveIntervalsWrapperPass()

Definition LiveIntervals.cpp:120

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

Definition LiveIntervals.cpp:109

LLVM_ABI ~LiveIntervals()

Definition LiveIntervals.cpp:124

LLVM_ABI void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)

Update live intervals for instructions in a range of iterators.

Definition LiveIntervals.cpp:1701

bool hasInterval(Register Reg) const

SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const

Return the first index in the given basic block.

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction associated with the given index.

LLVM_ABI bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const

Returns true if VNI is killed by any PHI-def values in LI.

Definition LiveIntervals.cpp:887

LLVM_ABI bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)

Test if LI is live across any register mask instructions, and compute a bit mask of physical register...

Definition LiveIntervals.cpp:956

LLVM_ABI void handleMove(MachineInstr &MI, bool UpdateFlags=false)

Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.

Definition LiveIntervals.cpp:1560

SlotIndexes * getSlotIndexes() const

ArrayRef< const uint32_t * > getRegMaskBits() const

Returns an array of register mask pointers corresponding to getRegMaskSlots().

LiveInterval & getOrCreateEmptyInterval(Register Reg)

Return an existing interval for Reg.

LLVM_ABI void addKillFlags(const VirtRegMap *)

Add kill flags to any instruction that kills a virtual register.

Definition LiveIntervals.cpp:728

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

LLVM_ABI bool invalidate(MachineFunction &MF, const PreservedAnalyses &PA, MachineFunctionAnalysisManager::Invalidator &Inv)

Definition LiveIntervals.cpp:126

VNInfo::Allocator & getVNInfoAllocator()

ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const

Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).

SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const

Return the last index in the given basic block.

static LLVM_ABI float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI, ProfileSummaryInfo *PSI=nullptr)

Calculate the spill weight to assign to a single instruction.

Definition LiveIntervals.cpp:902

ArrayRef< SlotIndex > getRegMaskSlots() const

Returns a sorted array of slot indices of all instructions with register mask operands.

ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const

Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...

LiveInterval & getInterval(Register Reg)

friend class LiveIntervalsAnalysis

LLVM_ABI void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)

If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.

Definition LiveIntervals.cpp:663

void removeInterval(Register Reg)

Interval removal.

LLVM_ABI void handleMoveIntoNewBundle(MachineInstr &BundleStart, bool UpdateFlags=false)

Update intervals of operands of all instructions in the newly created bundle specified by BundleStart...

Definition LiveIntervals.cpp:1576

LiveRange & getRegUnit(MCRegUnit Unit)

Return the live range for register unit Unit.

LLVM_ABI MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const

If LI is confined to a single basic block, return a pointer to that block.

Definition LiveIntervals.cpp:861

LiveRange * getCachedRegUnit(MCRegUnit Unit)

Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...

LLVM_ABI void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)

Remove value number and related live segments of LI and its subranges that start at position Pos.

Definition LiveIntervals.cpp:1785

LLVM_ABI LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)

Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.

Definition LiveIntervals.cpp:923

LLVM_ABI bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)

After removing some uses of a register, shrink its live range to just the remaining uses.

Definition LiveIntervals.cpp:483

LLVM_ABI void constructMainRangeFromSubranges(LiveInterval &LI)

For live interval LI with correct SubRanges construct matching information for the main live range.

Definition LiveIntervals.cpp:1819

LiveInterval & createEmptyInterval(Register Reg)

Interval creation.

LLVM_ABI void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)

Extend the live range LR to reach all points in Indices.

Definition LiveIntervals.cpp:654

LLVM_ABI void dump() const

Definition LiveIntervals.cpp:217

LLVM_ABI void print(raw_ostream &O) const

Implement the dump method.

Definition LiveIntervals.cpp:181

LLVM_ABI void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)

Remove value numbers and related live segments starting at position Pos that are part of any liverang...

Definition LiveIntervals.cpp:1777

LLVM_ABI void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)

Split separate components in LiveInterval LI into separate intervals.

Definition LiveIntervals.cpp:1803

MachineBasicBlock * getMBBFromIndex(SlotIndex index) const

LiveInterval & createAndComputeVirtRegInterval(Register Reg)

Result of a LiveRange query.

VNInfo * valueOutOrDead() const

Returns the value alive at the end of the instruction, if any.

bool isDeadDef() const

Return true if this instruction has a dead def.

VNInfo * valueIn() const

Return the value that is live-in to the instruction.

VNInfo * valueDefined() const

Return the value defined by this instruction, if any.

SlotIndex endPoint() const

Return the end point of the last live range segment to interact with the instruction,...

static LLVM_ABI bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)

A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...

This class represents the liveness of a register, stack slot, etc.

LLVM_ABI iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

Segments::iterator iterator

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

iterator_range< vni_iterator > vnis()

Segments::const_iterator const_iterator

LLVM_ABI VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)

createDeadDef - Make sure the range has a value defined at Def.

LLVM_ABI bool covers(const LiveRange &Other) const

Returns true if all segments of the Other live range are completely covered by this live range.

iterator advanceTo(iterator I, SlotIndex Pos)

advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...

LLVM_ABI void removeValNo(VNInfo *ValNo)

removeValNo - Remove all the segments defined by the specified value#.

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

VNInfo * getVNInfoBefore(SlotIndex Idx) const

getVNInfoBefore - Return the VNInfo that is live up to but not necessarily including Idx,...

bool verify() const

Walk the range and assert if any invariants fail to hold.

SlotIndex beginIndex() const

beginIndex - Return the lowest numbered slot covered.

SlotIndex endIndex() const

endNumber - return the maximum point of the range of the whole, exclusive.

bool hasAtLeastOneValue() const

VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)

getNextValue - Create a new value number and return it.

iterator FindSegmentContaining(SlotIndex Idx)

Return an iterator to the segment that contains the specified index, or end() if there is none.

LLVM_ABI void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)

Remove the specified interval from this live range.

LLVM_ABI void flushSegmentSet()

Flush segment set into the regular segment vector.

VNInfo * getVNInfoAt(SlotIndex Idx) const

getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.

LLVM_ABI iterator find(SlotIndex Pos)

find - Return an iterator pointing to the first segment that ends after Pos, or end().

MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.

bool isValid() const

Returns true if this iterator is not yet at the end.

Wrapper class representing physical registers. Should be passed by value.

unsigned pred_size() const

bool isEHPad() const

Returns true if the block is a landing pad.

iterator_range< livein_iterator > liveins() const

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

bool livein_empty() const

LLVM_ABI const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const

Get the clobber mask for the start of this basic block.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

iterator_range< succ_iterator > successors()

iterator_range< pred_iterator > predecessors()

MachineInstrBundleIterator< MachineInstr > iterator

LLVM_ABI const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const

Get the clobber mask for the end of the basic block.

MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...

double getBlockFreqRelativeToEntryBlock(const MachineBasicBlock *MBB) const

Compute the frequency of the block, relative to the entry block.

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass(char &ID)

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

void print(raw_ostream &OS, const SlotIndexes *=nullptr) const

print - Print out the MachineFunction in a format suitable for debugging to the specified stream.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

AnalysisType & getAnalysis() const

getAnalysis() - This function is used by subclasses to get to the analysis information ...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

PreservedAnalysisChecker getChecker() const

Build a checker for this PreservedAnalyses and the specified analysis type.

Analysis providing profile information.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

SlotIndex - An opaque wrapper around machine indexes.

static bool isSameInstr(SlotIndex A, SlotIndex B)

isSameInstr - Return true if A and B refer to the same instruction.

bool isBlock() const

isBlock - Returns true if this is a block boundary slot.

SlotIndex getDeadSlot() const

Returns the dead def kill slot for the current instruction.

static bool isEarlierInstr(SlotIndex A, SlotIndex B)

isEarlierInstr - Return true if A refers to an instruction earlier than B.

bool isValid() const

Returns true if this is a valid index.

static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)

Return true if A refers to the same instruction as B or an earlier one.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getPrevSlot() const

Returns the previous slot in the index list.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

MachineBasicBlock * getMBBFromIndex(SlotIndex index) const

Returns the basic block which the given index falls in.

SlotIndex getNextNonNullIndex(SlotIndex Index)

Returns the next non-null index, if one exists.

SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const

Returns the base index for the given instruction.

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction for the given index, or null if the given index has no instruction associated...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void swap(SmallVectorImpl &RHS)

typename SuperClass::iterator iterator

void push_back(const T &Elt)

pointer data()

Return a pointer to the vector's buffer, even if empty().

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

MI-level Statepoint operands.

unsigned getNumDeoptArgsIdx() const

Get index of Number Deopt Arguments operand.

uint64_t getFlags() const

Return the statepoint flags.

LLVM_ABI unsigned getNumGCPtrIdx()

Get index of number of GC pointers.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

VNInfo - Value Number Information.

void markUnused()

Mark this value as unused.

bool isUnused() const

Returns true if this value is unused.

unsigned id

The ID number of this value.

SlotIndex def

The index of the defining instruction.

bool isPHIDef() const

Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

Wrapper class representing a virtual register or register unit.

constexpr bool isVirtualReg() const

constexpr MCRegUnit asMCRegUnit() const

constexpr Register asVirtualReg() const

self_iterator getIterator()

A range adaptor for a pair of iterators.

This class implements an extremely fast bulk output stream that can only output to a stream.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

initializer< Ty > init(const Ty &Val)

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

LLVM_ABI cl::opt< bool > UseSegmentSetForPhysRegs

LLVM_ABI char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

LLVM_ABI void initializeLiveIntervalsWrapperPassPass(PassRegistry &)

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

void erase(Container &C, ValueType V)

Wrapper function to remove a value from a container:

LLVM_ABI char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)

Returns an iterator pointing beyond the bundle containing I.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

LLVM_ABI const float huge_valf

Use this rather than HUGE_VALF; the latter causes warnings on MSVC.

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

FunctionAddr VTableAddr Next

@ DeoptLiveIn

Mark the deopt arguments associated with the statepoint as only being "live-in".

iterator_range< MIBundleOperands > mi_bundle_ops(MachineInstr &MI)

df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

LLVM_ABI char & LiveIntervalsID

LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.

Definition LiveIntervals.cpp:80

LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

A special type used by analysis passes to provide an address that identifies that particular analysis...

static constexpr LaneBitmask getAll()

constexpr bool any() const

static constexpr LaneBitmask getNone()

This represents a simple continuous liveness interval for a value.