LiveIntervals.cpp Source File (original) (raw)

40#include "llvm/Config/llvm-config.h"

51#include

52#include

53#include

54#include

55#include

56#include

58using namespace llvm;

60#define DEBUG_TYPE "regalloc"

69}

74 OS << "Live intervals for machine function: " << MF.getName() << ":\n";

77}

82 "Live Interval Analysis", false, false)

89 LIS.Indexes = &getAnalysis().getSI();

90 LIS.DomTree = &getAnalysis().getDomTree();

91 LIS.analyze(MF);

93 return false;

94}

96#ifndef NDEBUG

98 "precompute-phys-liveness", cl::Hidden,

99 cl::desc("Eagerly compute live intervals for all physreg units."));

100#else

102#endif

103

104namespace llvm {

105

109 "Use segment set for the computation of the live ranges of physregs."));

110

111}

112

122}

123

126}

127

129

134

136 return true;

137

138

139

142}

143

144void LiveIntervals::clear() {

145

146 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)

148 VirtRegIntervals.clear();

149 RegMaskSlots.clear();

150 RegMaskBits.clear();

151 RegMaskBlocks.clear();

152

153 for (LiveRange *LR : RegUnitRanges)

154 delete LR;

155 RegUnitRanges.clear();

156

157

158 VNInfoAllocator.Reset();

159}

160

162 MF = &fn;

166

167 if (!LICalc)

168 LICalc = std::make_unique();

169

170

172

173 computeVirtRegs();

174 computeRegMasks();

175 computeLiveInRegUnits();

176

178

179

180 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)

182 }

183}

184

186 OS << "********** INTERVALS **********\n";

187

188

189 for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)

190 if (LiveRange *LR = RegUnitRanges[Unit])

192

193

194 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

198 }

199

200 OS << "RegMasks:";

202 OS << ' ' << Idx;

203 OS << '\n';

204

205 printInstrs(OS);

206}

207

208void LiveIntervals::printInstrs(raw_ostream &OS) const {

209 OS << "********** MACHINEINSTRS **********\n";

211}

212

213#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

215 printInstrs(dbgs());

216}

217#endif

218

219#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

221#endif

222

226}

227

228

229bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {

230 assert(LICalc && "LICalc not initialized.");

231 assert(LI.empty() && "Should only compute empty intervals.");

234 return computeDeadValues(LI, nullptr);

235}

236

237void LiveIntervals::computeVirtRegs() {

238 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

241 continue;

243 bool NeedSplit = computeVirtRegInterval(LI);

244 if (NeedSplit) {

247 }

248 }

249}

250

251void LiveIntervals::computeRegMasks() {

253

254

256 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];

257 RMB.first = RegMaskSlots.size();

258

259

263 }

264

265

266

267

272 }

273

276 if (!MO.isRegMask())

277 continue;

279 RegMaskBits.push_back(MO.getRegMask());

280 }

281 }

282

283

284

285

288 RegMaskSlots.push_back(

291 }

292

293

294 RMB.second = RegMaskSlots.size() - RMB.first;

295 }

296}

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {

313 assert(LICalc && "LICalc not initialized.");

315

316

317

318

319

320

321 bool IsReserved = false;

323 bool IsRootReserved = true;

326 LICalc->createDeadDefs(LR, Reg);

327

328

330 IsRootReserved = false;

331 }

332 IsReserved |= IsRootReserved;

333 }

335 "reserved computation mismatch");

336

337

338

339 if (!IsReserved) {

343 LICalc->extendToUses(LR, Reg);

344 }

345 }

346 }

347

348

351}

352

353

354

355

356void LiveIntervals::computeLiveInRegUnits() {

358 LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");

359

360

362

363

365

367 continue;

368

369

372 for (const auto &LI : MBB.liveins()) {

374 LiveRange *LR = RegUnitRanges[Unit];

375 if (!LR) {

376

379 }

381 (void)VNI;

383 }

384 }

386 }

387 LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");

388

389

390 for (unsigned Unit : NewRanges)

391 computeRegUnitRange(*RegUnitRanges[Unit], Unit);

392}

393

396 for (VNInfo *VNI : VNIs) {

398 continue;

401 }

402}

403

404void LiveIntervals::extendSegmentsToUses(LiveRange &Segments,

405 ShrinkToUsesWorkList &WorkList,

407

409

411

414 if (M.none())

415 return I;

417 if ((SR.LaneMask & M).any()) {

418 assert(SR.LaneMask == M && "Expecting lane masks to match exactly");

419 return SR;

420 }

421 }

423 };

424

426 const LiveRange &OldRange = getSubRange(LI, LaneMask);

427

428

429 while (!WorkList.empty()) {

431 VNInfo *VNI = WorkList.back().second;

432 WorkList.pop_back();

435

436

438 assert(ExtVNI == VNI && "Unexpected existing value number");

439 (void)ExtVNI;

440

441 if (!VNI->isPHIDef() || VNI->def != BlockStart ||

442 !UsedPHIs.insert(VNI).second)

443 continue;

444

446 if (!LiveOut.insert(Pred).second)

447 continue;

449

451 WorkList.push_back(std::make_pair(Stop, PVNI));

452 }

453 continue;

454 }

455

456

457 LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n');

459

460

462 if (!LiveOut.insert(Pred).second)

463 continue;

466 assert(OldVNI == VNI && "Wrong value out of predecessor");

467 (void)OldVNI;

468 WorkList.push_back(std::make_pair(Stop, VNI));

469 } else {

470#ifndef NDEBUG

471

472

474 "Missing value out of predecessor for main range");

478 "Missing value out of predecessor for subrange");

479#endif

480 }

481 }

482 }

483}

484

488 assert(li->reg().isVirtual() && "Can only shrink virtual registers");

489

490

491 bool NeedsCleanup = false;

494 if (S.empty())

495 NeedsCleanup = true;

496 }

497 if (NeedsCleanup)

499

500

502

503

506 if (UseMI.isDebugInstr() || UseMI .readsVirtualRegister(Reg))

507 continue;

511 if (!VNI) {

512

513

514

517 << "Warning: Instr claims to read non-existent value in "

518 << *li << '\n');

519 continue;

520 }

521

522

524 Idx = DefVNI->def;

525

526 WorkList.push_back(std::make_pair(Idx, VNI));

527 }

528

529

533

534

536

537

538 bool CanSeparate = computeDeadValues(*li, dead);

540 return CanSeparate;

541}

542

543bool LiveIntervals::computeDeadValues(LiveInterval &LI,

545 bool MayHaveSplitComponents = false;

546

549 continue;

552 assert(I != LI.end() && "Missing segment for VNI");

553

554

555

558 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {

560 MI->setRegisterDefReadUndef(VReg);

561 }

562 }

563

564 if (I->end != Def.getDeadSlot())

565 continue;

567

570 LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");

571 } else {

572

574 assert(MI && "No instruction defining live value");

575 MI->addRegisterDead(LI.reg(), TRI);

576

577 if (dead && MI->allDefsAreDead()) {

578 LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);

580 }

581 }

582 MayHaveSplitComponents = true;

583 }

584 return MayHaveSplitComponents;

585}

586

589 assert(Reg.isVirtual() && "Can only shrink virtual registers");

590

592

593

596

597 if (!MO.readsReg())

598 continue;

599

600 unsigned SubReg = MO.getSubReg();

603 if ((LaneMask & SR.LaneMask).none())

604 continue;

605 }

606

609 if (Idx == LastIdx)

610 continue;

611 LastIdx = Idx;

612

615

616

617 if (!VNI)

618 continue;

619

620

621

623 Idx = DefVNI->def;

624

625 WorkList.push_back(std::make_pair(Idx, VNI));

626 }

627

628

631 extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);

632

633

635

636

639 continue;

641 assert(Segment != nullptr && "Missing segment for VNI");

643 continue;

645

647 << " may separate interval\n");

650 }

651 }

652

654}

655

659 assert(LICalc && "LICalc not initialized.");

662 LICalc->extend(LR, Idx, 0, Undefs);

663}

664

669 if (!VNI)

670 return;

671

674

675

676 if (LRQ.endPoint() < MBBEnd) {

679 return;

680 }

681

682

684 if (EndPoints) EndPoints->push_back(MBBEnd);

685

686

687

688

690 VisitedTy Visited;

694 I != E;) {

696

697

699 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);

701 if (LRQ.valueIn() != VNI) {

702

703 I.skipChildren();

704 continue;

705 }

706

707

708 if (LRQ.endPoint() < MBBEnd) {

711 I.skipChildren();

712 continue;

713 }

714

715

717 if (EndPoints) EndPoints->push_back(MBBEnd);

718 ++I;

719 }

720 }

721}

722

723

724

725

726

728

730

731 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

734 continue;

737 continue;

738

739

741 if (!PhysReg)

742 continue;

743

744

745

749 auto [Unit, Bitmask] = *UI;

750

752 ArtificialLanes |= Bitmask;

754 if (RURange.empty())

755 continue;

756 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));

757 }

758

759

761 ++RI) {

762

763 if (RI->end.isBlock())

764 continue;

766 if ()

767 continue;

768

769

770

771

772

773

774

775

776

777 for (auto &RUP : RU) {

778 const LiveRange &RURange = *RUP.first;

780 if (I == RURange.end())

781 continue;

783 if (I == RURange.end() || I->start >= RI->end)

784 continue;

785

786 goto CancelKill;

787 }

788

790

791

792

793

794

795

796

797

798

799

800

803

804

805

806

807

808 DefinedLanesMask = ArtificialLanes;

811 if (Segment.start >= RI->end)

812 break;

813 if (Segment.end == RI->end) {

814 DefinedLanesMask |= SR.LaneMask;

815 break;

816 }

817 }

818 } else

820

821 bool IsFullWrite = false;

823 if (!MO.isReg() || MO.getReg() != Reg)

824 continue;

825 if (MO.isUse()) {

826

827 unsigned SubReg = MO.getSubReg();

830 if ((UseMask & ~DefinedLanesMask).any())

831 goto CancelKill;

832 } else if (MO.getSubReg() == 0) {

833

835 IsFullWrite = true;

836 }

837 }

838

839

840

841

842

843 if (!IsFullWrite) {

844

846 if (N != LI.end() && N->start == RI->end)

847 goto CancelKill;

848 }

849 }

850

851 MI->addRegisterKilled(Reg, nullptr);

852 continue;

853CancelKill:

854 MI->clearRegisterKills(Reg, nullptr);

855 }

856 }

857}

858

861 assert(!LI.empty() && "LiveInterval is empty.");

862

863

864

865

866

867

868

869

871 if (Start.isBlock())

872 return nullptr;

873

876 return nullptr;

877

878

879

882 return MBB1 == MBB2 ? MBB1 : nullptr;

883}

884

885bool

888 if (PHI->isUnused() || PHI ->isPHIDef())

889 continue;

891

893 return true;

896 return true;

897 }

898 return false;

899}

900

905 return getSpillWeight(isDef, isUse, MBFI, MI.getParent(), PSI);

906}

907

912 float Weight = isDef + isUse;

914

915

917 return Weight;

919}

920

930

931 return S;

932}

933

934

935

936

937

938

939

941 if (MI->getOpcode() != TargetOpcode::STATEPOINT)

942 return false;

945 return false;

950 return true;

951 }

952 return false;

953}

954

958 return false;

960

961

967 } else {

970 }

971

972

973

976

977

978 if (SlotI == SlotE)

979 return false;

980

981 bool Found = false;

982

983 auto unionBitMask = [&](unsigned Idx) {

984 if (!Found) {

985

986 UsableRegs.clear();

988 Found = true;

989 }

990

992 };

993 while (true) {

994 assert(*SlotI >= LiveI->start);

995

996 while (*SlotI < LiveI->end) {

997

998 unionBitMask(SlotI - Slots.begin());

999 if (++SlotI == SlotE)

1000 return Found;

1001 }

1002

1003 if (*SlotI == LiveI->end)

1006 unionBitMask(SlotI++ - Slots.begin());

1007

1008

1009 if (++LiveI == LiveE || SlotI == SlotE || *SlotI > LI.endIndex())

1010 return Found;

1011 while (LiveI->end < *SlotI)

1012 ++LiveI;

1013

1014 while (*SlotI < LiveI->start)

1015 if (++SlotI == SlotE)

1016 return Found;

1017 }

1018}

1019

1020

1021

1022

1023

1024

1026private:

1033 bool UpdateFlags;

1034

1035public:

1039 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),

1040 UpdateFlags(UpdateFlags) {}

1041

1042

1043

1044

1045

1047 if (UpdateFlags && MRI .isReservedRegUnit(Unit))

1050 }

1051

1052

1053

1055 LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": "

1056 << *MI);

1057 bool hasRegMask = false;

1059 if (MO.isRegMask())

1060 hasRegMask = true;

1061 if (!MO.isReg())

1062 continue;

1063 if (MO.isUse()) {

1064 if (!MO.readsReg())

1065 continue;

1066

1067

1068 MO.setIsKill(false);

1069 }

1070

1072 if (!Reg)

1073 continue;

1074 if (Reg.isVirtual()) {

1077 unsigned SubReg = MO.getSubReg();

1079 : MRI.getMaxLaneMaskForVReg(Reg);

1081 if ((S.LaneMask & LaneMask).none())

1082 continue;

1084 }

1085 }

1087

1088

1089

1090

1091

1092

1094 unsigned SubReg = MO.getSubReg();

1096 : MRI.getMaxLaneMaskForVReg(Reg);

1098 if ((S.LaneMask & LaneMask).none() || LI.covers(S))

1099 continue;

1102 break;

1103 }

1104 }

1105

1106 continue;

1107 }

1108

1109

1110

1111 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))

1114 }

1115 if (hasRegMask)

1116 updateRegMaskSlots();

1117 }

1118

1119private:

1120

1121

1124 if (!Updated.insert(&LR).second)

1125 return;

1127 dbgs() << " ";

1130 if (LaneMask.any())

1132 } else {

1134 }

1135 dbgs() << ":\t" << LR << '\n';

1136 });

1138 handleMoveDown(LR);

1139 else

1140 handleMoveUp(LR, VRegOrUnit, LaneMask);

1143 }

1144

1145

1146

1147 void handleMoveDown(LiveRange &LR) {

1149

1151

1152

1154 return;

1155

1157

1159

1161 return;

1162

1163

1164

1167 if (MOP.isReg() && MOP.isUse())

1168 MOP.setIsKill(false);

1169

1170

1174

1175

1178

1179 if (NewIdxIn == E ||

1183 }

1184

1185 OldIdxIn->end = Next->start;

1186 return;

1187 }

1188

1189

1190

1192 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());

1193

1194 if (!isKill)

1195 return;

1196

1197

1198 OldIdxOut = Next;

1200 return;

1201 } else {

1202 OldIdxOut = OldIdxIn;

1203 }

1204

1205

1206

1208 "No def?");

1209 VNInfo *OldIdxVNI = OldIdxOut->valno;

1210 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");

1211

1212

1213

1214 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());

1216 OldIdxVNI->def = NewIdxDef;

1217 OldIdxOut->start = OldIdxVNI->def;

1218 return;

1219 }

1220

1221

1222

1223

1224

1227 bool OldIdxDefIsDead = OldIdxOut->end.isDead();

1228 if (!OldIdxDefIsDead &&

1230

1232 if (OldIdxOut != LR.begin() &&

1234 OldIdxOut->start)) {

1235

1236

1238 DefVNI = OldIdxVNI;

1239 IPrev->end = OldIdxOut->end;

1240 } else {

1241

1243 assert(INext != E && "Must have following segment");

1244

1245

1246

1247

1248 DefVNI = OldIdxVNI;

1249 INext->start = OldIdxOut->end;

1250 INext->valno->def = INext->start;

1251 }

1252

1253 if (AfterNewIdx == E) {

1254

1255

1256

1257

1258 std::copy(std::next(OldIdxOut), E, OldIdxOut);

1259

1262 DefVNI);

1263 DefVNI->def = NewIdxDef;

1264

1266 Prev->end = NewIdxDef;

1267 } else {

1268

1269

1270

1271

1272 std::copy(std::next(OldIdxOut), std::next(AfterNewIdx), OldIdxOut);

1274

1276

1277

1279 *NewSegment = LiveRange::Segment(NewIdxDef, Prev->end, Prev->valno);

1280 Prev->valno->def = NewIdxDef;

1281

1283 DefVNI->def = Prev->start;

1284 } else {

1285

1286

1288 DefVNI->def = NewIdxDef;

1289 assert(DefVNI != AfterNewIdx->valno);

1290 }

1291 }

1292 return;

1293 }

1294

1295 if (AfterNewIdx != E &&

1297

1298

1299 assert(AfterNewIdx->valno != OldIdxVNI && "Multiple defs of value?");

1301 } else {

1302

1303

1304

1305

1306

1307 assert(AfterNewIdx != OldIdxOut && "Inconsistent iterators");

1308 std::copy(std::next(OldIdxOut), AfterNewIdx, OldIdxOut);

1309

1311 VNInfo *NewSegmentVNI = OldIdxVNI;

1312 NewSegmentVNI->def = NewIdxDef;

1314 NewSegmentVNI);

1315 }

1316 }

1317

1318

1319

1323

1325

1326

1328 return;

1329

1331

1333

1334

1335

1337 if (!isKill)

1338 return;

1339

1340

1341

1343 = std::max(OldIdxIn->start.getDeadSlot(),

1344 NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));

1345 OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, VRegOrUnit, LaneMask);

1346

1347

1348 OldIdxOut = std::next(OldIdxIn);

1350 return;

1351 } else {

1352 OldIdxOut = OldIdxIn;

1353 OldIdxIn = OldIdxOut != LR.begin() ? std::prev(OldIdxOut) : E;

1354 }

1355

1356

1357

1359 "No def?");

1360 VNInfo *OldIdxVNI = OldIdxOut->valno;

1361 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");

1362 bool OldIdxDefIsDead = OldIdxOut->end.isDead();

1363

1364

1365 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());

1368 assert(NewIdxOut->valno != OldIdxVNI &&

1369 "Same value defined more than once?");

1370

1371 if (!OldIdxDefIsDead) {

1372

1373

1374 OldIdxVNI->def = NewIdxDef;

1375 OldIdxOut->start = NewIdxDef;

1377 } else {

1378

1380 }

1381 } else {

1382

1383

1384 if (!OldIdxDefIsDead) {

1385

1386 if (OldIdxIn != E &&

1388

1391 const SlotIndex SplitPos = NewIdxDef;

1392 OldIdxVNI = OldIdxIn->valno;

1393

1394 SlotIndex NewDefEndPoint = std::next(NewIdxIn)->end;

1396 if (OldIdxIn != LR.begin() &&

1398

1399

1400

1401

1402

1403

1404 NewDefEndPoint = std::min(OldIdxIn->start,

1405 std::next(NewIdxOut)->start);

1406 }

1407

1408

1409 OldIdxOut->valno->def = OldIdxIn->start;

1411 OldIdxOut->valno);

1412

1413

1414

1415

1416 std::copy_backward(NewIdxIn, OldIdxIn, OldIdxOut);

1417

1418

1422

1424 Next->valno);

1425

1427 Next->valno->def = SplitPos;

1428 } else {

1429

1430

1432 NewSegment->valno->def = SplitPos;

1433 }

1434 } else {

1435

1436 OldIdxOut->start = NewIdxDef;

1437 OldIdxVNI->def = NewIdxDef;

1439 OldIdxIn->end = NewIdxDef;

1440 }

1441 } else if (OldIdxIn != E

1444

1445

1446

1447

1448

1449

1450

1451

1452 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));

1453

1454

1455

1457 NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);

1459 NewIdxDef.getRegSlot(), (NewIdxOut + 1)->end, OldIdxVNI);

1460 OldIdxVNI->def = NewIdxDef;

1461

1462 for (auto *Idx = NewIdxOut + 2; Idx <= OldIdxOut; ++Idx)

1463 Idx->valno = OldIdxVNI;

1464

1465

1466

1469 if (MO->isReg() && !MO->isUse())

1470 MO->setIsDead(false);

1471 } else {

1472

1473

1474

1475

1476

1477 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));

1478

1480 VNInfo *NewSegmentVNI = OldIdxVNI;

1482 NewSegmentVNI);

1483 NewSegmentVNI->def = NewIdxDef;

1484 }

1485 }

1486 }

1487

1488 void updateRegMaskSlots() {

1491 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&

1492 "No RegMask at OldIdx.");

1494 assert((RI == LIS.RegMaskSlots.begin() ||

1496 "Cannot move regmask instruction above another call");

1497 assert((std::next(RI) == LIS.RegMaskSlots.end() ||

1499 "Cannot move regmask instruction below another call");

1500 }

1501

1502

1509 if (MO.isUndef())

1510 continue;

1511 unsigned SubReg = MO.getSubReg();

1512 if (SubReg != 0 && LaneMask.any()

1513 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())

1514 continue;

1515

1518 if (InstSlot > LastUse && InstSlot < OldIdx)

1520 }

1521 return LastUse;

1522 }

1523

1524

1525

1526 assert(Before < OldIdx && "Expected upwards move");

1529

1530

1531

1535 if (MI->getParent() == MBB)

1536 MII = MI;

1537

1539 while (MII != Begin) {

1540 if ((--MII)->isDebugOrPseudoInstr())

1541 continue;

1543

1544

1547

1548

1550 if (MO->isReg() && !MO->isUndef() && MO->getReg().isPhysical() &&

1551 TRI.hasRegUnit(MO->getReg(), VRegOrUnit.asMCRegUnit()))

1552 return Idx.getRegSlot();

1553 }

1554

1556 }

1557};

1558

1560

1561

1562 assert((.isBundled() || MI.getOpcode() == TargetOpcode::BUNDLE) &&

1563 "Cannot move instruction in bundle");

1569 "Cannot handle moves across basic block boundaries.");

1570

1571 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);

1573}

1574

1576 bool UpdateFlags) {

1577 assert((BundleStart.getOpcode() == TargetOpcode::BUNDLE) &&

1578 "Bundle start is not a bundle");

1582

1584 I++;

1585 while (I != BundleEnd) {

1587 continue;

1591 I++;

1592 }

1593 for (SlotIndex OldIndex : ToProcess) {

1594 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);

1596 }

1597

1598

1601 if (!MO.isReg())

1602 continue;

1604 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) {

1608 MO.setIsDead();

1609 }

1610 }

1611}

1612

1620 if (LII != LR.end() && LII->start < EndIdx) {

1621 lastUseIdx = LII->end;

1622 } else if (LII == LR.begin()) {

1623

1624

1625 } else {

1626 --LII;

1627 }

1628

1630 --I;

1632 if (MI.isDebugOrPseudoInstr())

1633 continue;

1634

1638

1639

1640

1642 if (!MO.isReg() || MO.getReg() != Reg)

1643 continue;

1644

1645 unsigned SubReg = MO.getSubReg();

1647 if ((Mask & LaneMask).none())

1648 continue;

1649

1650 if (MO.isDef()) {

1651 if (!isStartValid) {

1652 if (LII->end.isDead()) {

1654 if (LII != LR.begin())

1655 --LII;

1656 } else {

1658 LII->valno->def = instrIdx.getRegSlot();

1659 if (MO.getSubReg() && !MO.isUndef())

1661 else

1663 continue;

1664 }

1665 }

1666

1667 if (!lastUseIdx.isValid()) {

1672 } else if (LII->start != instrIdx.getRegSlot()) {

1676 }

1677

1678 if (MO.getSubReg() && !MO.isUndef())

1680 else

1682 } else if (MO.isUse()) {

1683

1684

1685

1686 if (!isEndValid && !LII->end.isBlock())

1688 if (!lastUseIdx.isValid())

1690 }

1691 }

1692 }

1693

1695 if (!isStartValid && LII->end.isDead())

1697}

1698

1699void

1704

1705

1706 while (Begin != MBB->begin() && !Indexes->hasIndex(*std::prev(Begin)))

1707 --Begin;

1710

1714 else

1716

1718

1719

1722 --I;

1724 if (MI.isDebugOrPseudoInstr())

1725 continue;

1727 if (MO.isReg() && MO.getReg().isVirtual()) {

1729 if (MO.getSubReg() && hasInterval(Reg) &&

1730 MRI->shouldTrackSubRegLiveness(Reg)) {

1733

1734

1735

1737 } else if (MO.isDef()) {

1738

1739

1740 unsigned SubReg = MO.getSubReg();

1744 return SR.LaneMask == Mask;

1745 })) {

1747 }

1748 }

1749 }

1752

1754 }

1755 }

1756 }

1757 }

1758

1759 for (Register Reg : RegsToRepair) {

1760 if (!Reg.isVirtual())

1761 continue;

1762

1764

1766 continue;

1767

1769 repairOldRegInRange(Begin, End, EndIdx, S, Reg, S.LaneMask);

1771

1772 repairOldRegInRange(Begin, End, EndIdx, LI, Reg);

1773 }

1774}

1775

1781 }

1782}

1783

1785

1786

1788 if (VNI != nullptr) {

1791 }

1792

1793

1795 if (VNInfo *SVNI = S.getVNInfoAt(Pos))

1796 if (SVNI->def.getBaseIndex() == Pos.getBaseIndex())

1797 S.removeValNo(SVNI);

1798 }

1800}

1801

1805 unsigned NumComp = ConEQ.Classify(LI);

1806 if (NumComp <= 1)

1807 return;

1808 LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');

1810 for (unsigned I = 1; I < NumComp; ++I) {

1811 Register NewVReg = MRI->cloneVirtualRegister(Reg);

1814 }

1816}

1817

1819 assert(LICalc && "LICalc not initialized.");

1821 LICalc->constructMainRangeFromSubranges(LI);

1822}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

block Block Frequency Analysis

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is Live

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

A common definition of LaneBitmask for use in TableGen and CodeGen.

static cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))

static bool hasLiveThroughUse(const MachineInstr *MI, Register Reg)

Check whether use of reg in MI is live-through.

static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)

unsigned const TargetRegisterInfo * TRI

std::pair< uint64_t, uint64_t > Interval

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

Toolkit used by handleMove to trim or extend live intervals.

HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)

void updateAllRanges(MachineInstr *MI)

Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.

LiveRange * getRegUnitLI(unsigned Unit)

This templated class represents "all analyses that operate over " (e....

API to communicate dependencies between analyses during invalidation.

bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA)

Trigger the invalidation of some other analysis pass if not already handled and return whether it was...

A container for analyses that lazily runs them and caches their results.

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequiredTransitiveID(char &ID)

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

void setPreservesCFG()

This function should be called by the pass, iff they do not:

AnalysisUsage & addRequiredTransitive()

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

void resize(unsigned N, bool t=false)

resize - Grow or shrink the bitvector.

void clear()

clear - Removes all bits from the bitvector.

void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.

void Reset()

Deallocate all but the current slab and reset the current pointer to the beginning of it,...

ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...

void Distribute(LiveInterval &LI, LiveInterval *LIV[], MachineRegisterInfo &MRI)

Distribute values in LI into a separate LiveIntervals for each connected component.

unsigned Classify(const LiveRange &LR)

Classify the values in LR into connected components.

A live range for subregisters.

LiveInterval - This class represents the liveness of a register, or stack slot.

void removeEmptySubRanges()

Removes all subranges without any segments (subranges without segments are not considered valid and s...

bool hasSubRanges() const

Returns true if subregister liveness information is available.

iterator_range< subrange_iterator > subranges()

void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const

For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...

Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

LiveIntervalsWrapperPass()

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)

Update live intervals for instructions in a range of iterators.

bool hasInterval(Register Reg) const

SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const

Return the first index in the given basic block.

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction associated with the given index.

bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const

Returns true if VNI is killed by any PHI-def values in LI.

bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)

Test if LI is live across any register mask instructions, and compute a bit mask of physical register...

void handleMove(MachineInstr &MI, bool UpdateFlags=false)

Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.

SlotIndexes * getSlotIndexes() const

ArrayRef< const uint32_t * > getRegMaskBits() const

Returns an array of register mask pointers corresponding to getRegMaskSlots().

LiveInterval & getOrCreateEmptyInterval(Register Reg)

Return an existing interval for Reg.

void addKillFlags(const VirtRegMap *)

Add kill flags to any instruction that kills a virtual register.

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

bool invalidate(MachineFunction &MF, const PreservedAnalyses &PA, MachineFunctionAnalysisManager::Invalidator &Inv)

VNInfo::Allocator & getVNInfoAllocator()

ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const

Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBBNum).

SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const

Return the last index in the given basic block.

static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI, ProfileSummaryInfo *PSI=nullptr)

Calculate the spill weight to assign to a single instruction.

ArrayRef< SlotIndex > getRegMaskSlots() const

Returns a sorted array of slot indices of all instructions with register mask operands.

LiveRange & getRegUnit(unsigned Unit)

Return the live range for register unit Unit.

ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const

Returns a sorted array of slot indices of all instructions with register mask operands in the basic b...

LiveRange * getCachedRegUnit(unsigned Unit)

Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...

LiveInterval & getInterval(Register Reg)

void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)

If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.

void removeInterval(Register Reg)

Interval removal.

void handleMoveIntoNewBundle(MachineInstr &BundleStart, bool UpdateFlags=false)

Update intervals of operands of all instructions in the newly created bundle specified by BundleStart...

MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const

If LI is confined to a single basic block, return a pointer to that block.

void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)

Remove value number and related live segments of LI and its subranges that start at position Pos.

LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)

Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.

bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)

After removing some uses of a register, shrink its live range to just the remaining uses.

void constructMainRangeFromSubranges(LiveInterval &LI)

For live interval LI with correct SubRanges construct matching information for the main live range.

LiveInterval & createEmptyInterval(Register Reg)

Interval creation.

void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)

Extend the live range LR to reach all points in Indices.

void print(raw_ostream &O) const

Implement the dump method.

void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)

Remove value numbers and related live segments starting at position Pos that are part of any liverang...

void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)

Split separate components in LiveInterval LI into separate intervals.

MachineBasicBlock * getMBBFromIndex(SlotIndex index) const

LiveInterval & createAndComputeVirtRegInterval(Register Reg)

Result of a LiveRange query.

VNInfo * valueOutOrDead() const

Returns the value alive at the end of the instruction, if any.

bool isDeadDef() const

Return true if this instruction has a dead def.

VNInfo * valueIn() const

Return the value that is live-in to the instruction.

VNInfo * valueDefined() const

Return the value defined by this instruction, if any.

SlotIndex endPoint() const

Return the end point of the last live range segment to interact with the instruction,...

static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)

A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...

This class represents the liveness of a register, stack slot, etc.

iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

const Segment * getSegmentContaining(SlotIndex Idx) const

Return the segment that contains the specified index, or null if there is none.

iterator_range< vni_iterator > vnis()

VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)

createDeadDef - Make sure the range has a value defined at Def.

bool covers(const LiveRange &Other) const

Returns true if all segments of the Other live range are completely covered by this live range.

iterator advanceTo(iterator I, SlotIndex Pos)

advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...

void removeValNo(VNInfo *ValNo)

removeValNo - Remove all the segments defined by the specified value#.

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

VNInfo * getVNInfoBefore(SlotIndex Idx) const

getVNInfoBefore - Return the VNInfo that is live up to but not necessarily including Idx,...

bool verify() const

Walk the range and assert if any invariants fail to hold.

SlotIndex beginIndex() const

beginIndex - Return the lowest numbered slot covered.

SlotIndex endIndex() const

endNumber - return the maximum point of the range of the whole, exclusive.

bool hasAtLeastOneValue() const

VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)

getNextValue - Create a new value number and return it.

iterator FindSegmentContaining(SlotIndex Idx)

Return an iterator to the segment that contains the specified index, or end() if there is none.

void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)

Remove the specified interval from this live range.

void flushSegmentSet()

Flush segment set into the regular segment vector.

VNInfo * getVNInfoAt(SlotIndex Idx) const

getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.

iterator find(SlotIndex Pos)

find - Return an iterator pointing to the first segment that ends after Pos, or end().

MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.

bool isValid() const

Returns true if this iterator is not yet at the end.

MCRegUnitRootIterator enumerates the root registers of a register unit.

bool isValid() const

Check if the iterator is at the end of the list.

unsigned getNumRegUnits() const

Return the number of (native) register units in the target.

bool isArtificialRegUnit(MCRegUnit Unit) const

Returns true when the given register unit is considered artificial.

iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const

Returns an iterator range over all regunits for Reg.

iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, including Reg.

unsigned getNumRegs() const

Return the number of registers this target has (useful for sizing arrays holding per register informa...

Wrapper class representing physical registers. Should be passed by value.

bool isValid() const

isValid - Returns true until all the operands have been visited.

MIBundleOperands - Iterate over all operands in a bundle of machine instructions.

unsigned pred_size() const

bool isEHPad() const

Returns true if the block is a landing pad.

iterator_range< livein_iterator > liveins() const

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

bool livein_empty() const

const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const

Get the clobber mask for the start of this basic block.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

iterator_range< succ_iterator > successors()

iterator_range< pred_iterator > predecessors()

const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const

Get the clobber mask for the end of the basic block.

MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...

double getBlockFreqRelativeToEntryBlock(const MachineBasicBlock *MBB) const

Compute the frequency of the block, relative to the entry block.

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

unsigned getNumBlockIDs() const

getNumBlockIDs - Return the number of MBB ID's allocated.

void print(raw_ostream &OS, const SlotIndexes *=nullptr) const

print - Print out the MachineFunction in a format suitable for debugging to the specified stream.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

iterator_range< mop_iterator > operands()

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const

bool subRegLivenessEnabled() const

bool isReserved(MCRegister PhysReg) const

isReserved - Returns true when PhysReg is a reserved register.

bool reg_nodbg_empty(Register RegNo) const

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const

Returns true if liveness for register class RC should be tracked at the subregister level.

iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const

LaneBitmask getMaxLaneMaskForVReg(Register Reg) const

Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...

bool isReservedRegUnit(unsigned Unit) const

Returns true when the given register unit is considered reserved.

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

bool reg_empty(Register RegNo) const

reg_empty - Return true if there are no instructions using or defining the specified register (it may...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

PreservedAnalysisChecker getChecker() const

Build a checker for this PreservedAnalyses and the specified analysis type.

Analysis providing profile information.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

SlotIndex - An opaque wrapper around machine indexes.

static bool isSameInstr(SlotIndex A, SlotIndex B)

isSameInstr - Return true if A and B refer to the same instruction.

bool isBlock() const

isBlock - Returns true if this is a block boundary slot.

SlotIndex getDeadSlot() const

Returns the dead def kill slot for the current instruction.

static bool isEarlierInstr(SlotIndex A, SlotIndex B)

isEarlierInstr - Return true if A refers to an instruction earlier than B.

bool isValid() const

Returns true if this is a valid index.

static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)

Return true if A refers to the same instruction as B or an earlier one.

SlotIndex getBaseIndex() const

Returns the base index for associated with this index.

SlotIndex getPrevSlot() const

Returns the previous slot in the index list.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)

Insert the given machine instruction into the mapping.

void removeMachineInstrFromMaps(MachineInstr &MI, bool AllowBundled=false)

Removes machine instruction (bundle) MI from the mapping.

MachineBasicBlock * getMBBFromIndex(SlotIndex index) const

Returns the basic block which the given index falls in.

void repairIndexesInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End)

Repair indexes after adding and removing instructions.

const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const

Return the (start,end) range of the given basic block number.

SlotIndex getMBBEndIdx(unsigned Num) const

Returns the last index in the given basic block number.

SlotIndex getNextNonNullIndex(SlotIndex Index)

Returns the next non-null index, if one exists.

SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const

Returns the base index for the given instruction.

SlotIndex getMBBStartIdx(unsigned Num) const

Returns the first index in the given basic block number.

bool hasIndex(const MachineInstr &instr) const

Returns true if the given machine instr is mapped to an index, otherwise returns false.

MachineInstr * getInstructionFromIndex(SlotIndex index) const

Returns the instruction for the given index, or null if the given index has no instruction associated...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void swap(SmallVectorImpl &RHS)

typename SuperClass::iterator iterator

void push_back(const T &Elt)

pointer data()

Return a pointer to the vector's buffer, even if empty().

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

MI-level Statepoint operands.

unsigned getNumDeoptArgsIdx() const

Get index of Number Deopt Arguments operand.

uint64_t getFlags() const

Return the statepoint flags.

unsigned getNumGCPtrIdx()

Get index of number of GC pointers.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const

Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...

LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const

Return a bitmask representing the parts of a register that are covered by SubIdx.

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual const TargetInstrInfo * getInstrInfo() const

VNInfo - Value Number Information.

void markUnused()

Mark this value as unused.

bool isUnused() const

Returns true if this value is unused.

unsigned id

The ID number of this value.

SlotIndex def

The index of the defining instruction.

bool isPHIDef() const

Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...

MCRegister getPhys(Register virtReg) const

returns the physical register mapped to the specified virtual register

Wrapper class representing a virtual register or register unit.

constexpr bool isVirtualReg() const

constexpr MCRegUnit asMCRegUnit() const

constexpr Register asVirtualReg() const

self_iterator getIterator()

A range adaptor for a pair of iterators.

This class implements an extremely fast bulk output stream that can only output to a stream.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

Reg

All possible values of the reg field in the ModR/M byte.

initializer< Ty > init(const Ty &Val)

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

char & MachineDominatorsID

MachineDominators - This pass is a machine dominators analysis pass.

Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)

void erase(Container &C, ValueType V)

Wrapper function to remove a value from a container:

char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)

Returns an iterator pointing beyond the bundle containing I.

const float huge_valf

Use this rather than HUGE_VALF; the latter causes warnings on MSVC.

cl::opt< bool > UseSegmentSetForPhysRegs

void initializeLiveIntervalsWrapperPassPass(PassRegistry &)

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

@ DeoptLiveIn

Mark the deopt arguments associated with the statepoint as only being "live-in".

iterator_range< MIBundleOperands > mi_bundle_ops(MachineInstr &MI)

df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

char & LiveIntervalsID

LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.

Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

A special type used by analysis passes to provide an address that identifies that particular analysis...

static constexpr LaneBitmask getAll()

constexpr bool any() const

static constexpr LaneBitmask getNone()

This represents a simple continuous liveness interval for a value.