MipsDisassembler.cpp Source File (original) (raw)

29#include

30#include

32using namespace llvm;

35#define DEBUG_TYPE "mips-disassembler"

39namespace {

42 bool IsMicroMips;

43 bool IsBigEndian;

45public:

48 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),

49 IsBigEndian(IsBigEndian) {}

51 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }

52 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }

53 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }

55 bool hasMips32r6() const {

56 return STI.hasFeature(Mips::FeatureMips32r6);

57 }

59 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }

61 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }

63 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }

65 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }

67 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }

69 bool hasCOP3() const {

71 return !hasMips32() && !hasMips3();

72 }

77};

79}

84 return new MipsDisassembler(STI, Ctx, true);

85}

90 return new MipsDisassembler(STI, Ctx, false);

91}

105

108 return RegInfo->getRegClass(RC).getRegister(RegNo);

109}

113

114 if (RegNo != 29)

118}

119

123 if (RegNo > 30 || RegNo % 2)

125

129}

130

134 if (RegNo >= 4)

136

140}

141

145 if (RegNo >= 4)

147

151}

152

156 if (RegNo >= 4)

158

162}

163

167 if (RegNo > 31)

169

173}

174

178 if (RegNo > 31)

180

184}

185

189 if (RegNo > 31)

191

195}

196

200 if (RegNo > 31)

202

206}

207

211 if (RegNo > 7)

213

217}

218

222 if (RegNo > 31)

224

228}

229

233 if (RegNo > 31)

235

239}

240

244 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,

245 Mips::S5, Mips::S6, Mips::S7, Mips::FP};

246 unsigned RegNum;

247

249

250

251 if (RegLst == 0)

253

254 RegNum = RegLst & 0xf;

255

256

257 if (RegNum > 9)

259

260 for (unsigned i = 0; i < RegNum; i++)

262

263 if (RegLst & 0x10)

265

267}

268

272 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};

273 unsigned RegLst;

275 default:

277 break;

278 case Mips::LWM16_MMR6:

279 case Mips::SWM16_MMR6:

281 break;

282 }

283 unsigned RegNum = RegLst & 0x3;

284

285 for (unsigned i = 0; i <= RegNum; i++)

287

289

291}

292

293template

296 using DecodeFN =

298

299

300

302 unsigned NSize = 0;

303 DecodeFN RegDecoder = nullptr;

304 if ((tmp & 0x18) == 0x00) {

305 NSize = 4;

307 } else if ((tmp & 0x1c) == 0x10) {

308 NSize = 3;

310 } else if ((tmp & 0x1e) == 0x18) {

311 NSize = 2;

313 } else if ((tmp & 0x1f) == 0x1c) {

314 NSize = 1;

316 } else

318

319 assert(NSize != 0 && RegDecoder != nullptr);

320

321

325

328

331

335

337

339}

340

341template

348 Rs)));

350 Rs)));

352

354}

355

356template

362 Rs)));

364 Rs)));

366

368}

369

370template

374

375

376

377

378

379

380

381

382

383

387 bool HasRs = false;

388

389 if (Rs >= Rt) {

390 MI.setOpcode(Mips::BOVC);

391 HasRs = true;

392 } else if (Rs != 0 && Rs < Rt) {

393 MI.setOpcode(Mips::BEQC);

394 HasRs = true;

395 } else

396 MI.setOpcode(Mips::BEQZALC);

397

398 if (HasRs)

400 Rs)));

401

403 Rt)));

405

407}

408

409template

415 int64_t Imm = 0;

416

417 if (Rs >= Rt) {

418 MI.setOpcode(Mips::BOVC_MMR6);

420 Rt)));

422 Rs)));

424 } else if (Rs != 0 && Rs < Rt) {

425 MI.setOpcode(Mips::BEQC_MMR6);

427 Rs)));

429 Rt)));

431 } else {

432 MI.setOpcode(Mips::BEQZALC_MMR6);

434 Rt)));

436 }

437

439

441}

442

443template

447

448

449

450

451

452

453

454

455

456

460 bool HasRs = false;

461

462 if (Rs >= Rt) {

463 MI.setOpcode(Mips::BNVC);

464 HasRs = true;

465 } else if (Rs != 0 && Rs < Rt) {

466 MI.setOpcode(Mips::BNEC);

467 HasRs = true;

468 } else

469 MI.setOpcode(Mips::BNEZALC);

470

471 if (HasRs)

473 Rs)));

474

476 Rt)));

478

480}

481

482template

488 int64_t Imm = 0;

489

490 if (Rs >= Rt) {

491 MI.setOpcode(Mips::BNVC_MMR6);

493 Rt)));

495 Rs)));

497 } else if (Rs != 0 && Rs < Rt) {

498 MI.setOpcode(Mips::BNEC_MMR6);

500 Rs)));

502 Rt)));

504 } else {

505 MI.setOpcode(Mips::BNEZALC_MMR6);

507 Rt)));

509 }

510

512

514}

515

516template

520

521

522

523

524

525

526

530 bool HasRs = false;

531

532 if (Rt == 0)

534 else if (Rs == 0)

535 MI.setOpcode(Mips::BGTZC_MMR6);

536 else if (Rs == Rt)

537 MI.setOpcode(Mips::BLTZC_MMR6);

538 else {

539 MI.setOpcode(Mips::BLTC_MMR6);

540 HasRs = true;

541 }

542

543 if (HasRs)

545 Rs)));

546

548 Rt)));

549

551

553}

554

555template

559

560

561

562

563

564

565

569 bool HasRs = false;

570

571 if (Rt == 0)

573 else if (Rs == 0)

574 MI.setOpcode(Mips::BLEZC_MMR6);

575 else if (Rs == Rt)

576 MI.setOpcode(Mips::BGEZC_MMR6);

577 else {

578 HasRs = true;

579 MI.setOpcode(Mips::BGEC_MMR6);

580 }

581

582 if (HasRs)

584 Rs)));

585

587 Rt)));

588

590

592}

593

594template

598

599

600

601

602

603

604

605

606

607

608

612 bool HasRs = false;

613

614 if (Rt == 0)

616 else if (Rs == 0)

617 MI.setOpcode(Mips::BLEZC);

618 else if (Rs == Rt)

619 MI.setOpcode(Mips::BGEZC);

620 else {

621 HasRs = true;

622 MI.setOpcode(Mips::BGEC);

623 }

624

625 if (HasRs)

627 Rs)));

628

630 Rt)));

631

633

635}

636

637template

641

642

643

644

645

646

647

648

649

650

651

652 bool HasRs = false;

653

657

658 if (Rt == 0)

660 else if (Rs == 0)

661 MI.setOpcode(Mips::BGTZC);

662 else if (Rs == Rt)

663 MI.setOpcode(Mips::BLTZC);

664 else {

665 MI.setOpcode(Mips::BLTC);

666 HasRs = true;

667 }

668

669 if (HasRs)

671 Rs)));

672

674 Rt)));

675

677

679}

680

681template

685

686

687

688

689

690

691

692

693

694

695

699 bool HasRs = false;

700 bool HasRt = false;

701

702 if (Rt == 0) {

703 MI.setOpcode(Mips::BGTZ);

704 HasRs = true;

705 } else if (Rs == 0) {

706 MI.setOpcode(Mips::BGTZALC);

707 HasRt = true;

708 } else if (Rs == Rt) {

709 MI.setOpcode(Mips::BLTZALC);

710 HasRs = true;

711 } else {

712 MI.setOpcode(Mips::BLTUC);

713 HasRs = true;

714 HasRt = true;

715 }

716

717 if (HasRs)

719 Rs)));

720

721 if (HasRt)

723 Rt)));

724

726

728}

729

730template

734

735

736

737

738

739

740

741

742

743

744

748 bool HasRs = false;

749

750 if (Rt == 0)

752 else if (Rs == 0)

753 MI.setOpcode(Mips::BLEZALC);

754 else if (Rs == Rt)

755 MI.setOpcode(Mips::BGEZALC);

756 else {

757 HasRs = true;

758 MI.setOpcode(Mips::BGEUC);

759 }

760

761 if (HasRs)

763 Rs)));

765 Rt)));

766

768

770}

771

772

773

774template

779 unsigned Size = 0;

780 unsigned Pos = 0;

781

782 switch (MI.getOpcode()) {

783 case Mips::DEXT:

784 Pos = Lsb;

785 Size = Msbd + 1;

786 break;

787 case Mips::DEXTM:

788 Pos = Lsb;

789 Size = Msbd + 1 + 32;

790 break;

791 case Mips::DEXTU:

792 Pos = Lsb + 32;

793 Size = Msbd + 1;

794 break;

795 default:

797 }

798

799 MI.setOpcode(Mips::DEXT);

800

803

804 MI.addOperand(

806 MI.addOperand(

810

812}

813

814

815

816template

821 unsigned Size = 0;

822 unsigned Pos = 0;

823

824 switch (MI.getOpcode()) {

825 case Mips::DINS:

826 Pos = Lsb;

827 Size = Msbd + 1 - Pos;

828 break;

829 case Mips::DINSM:

830 Pos = Lsb;

831 Size = Msbd + 33 - Pos;

832 break;

833 case Mips::DINSU:

834 Pos = Lsb + 32;

835

836

837 Size = Msbd + 33 - Pos;

838 break;

839 default:

841 }

842

845

846 MI.setOpcode(Mips::DINS);

847 MI.addOperand(

849 MI.addOperand(

853

855}

856

857

858template

863 MI.addOperand(

865 MI.addOperand(

867 MI.addOperand(

870}

871

877

881 if (RegNo > 31)

883

887}

888

898

908

918

919

920

921

927

933

939

945

955

959 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())

961

963}

964

970

974 if (RegNo > 31)

976

980}

981

985 if (RegNo > 31)

987

991}

992

996 if (RegNo > 31)

1001}

1002

1006 if (RegNo > 7)

1011}

1012

1016 if (RegNo > 31)

1018

1022}

1023

1029

1032

1033 if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 ||

1036

1040

1042}

1043

1049

1052

1053 if (Inst.getOpcode() == Mips::SCE)

1055

1059

1061}

1062

1079

1094

1110

1126

1142

1155

1169

1182

1189

1192

1195

1196

1197

1198

1199

1200

1201

1202

1204 {

1205 default:

1206 assert(false && "Unexpected instruction");

1208 break;

1209 case Mips::LD_B:

1210 case Mips::ST_B:

1212 break;

1213 case Mips::LD_H:

1214 case Mips::ST_H:

1216 break;

1217 case Mips::LD_W:

1218 case Mips::ST_W:

1220 break;

1221 case Mips::LD_D:

1222 case Mips::ST_D:

1224 break;

1225 }

1226

1228}

1229

1233 unsigned Offset = Insn & 0xf;

1236

1238 case Mips::LBU16_MM:

1239 case Mips::LHU16_MM:

1240 case Mips::LW16_MM:

1244 break;

1245 case Mips::SB16_MM:

1246 case Mips::SB16_MMR6:

1247 case Mips::SH16_MM:

1248 case Mips::SH16_MMR6:

1249 case Mips::SW16_MM:

1250 case Mips::SW16_MMR6:

1254 break;

1255 }

1256

1260

1262 case Mips::LBU16_MM:

1265 else

1267 break;

1268 case Mips::SB16_MM:

1269 case Mips::SB16_MMR6:

1271 break;

1272 case Mips::LHU16_MM:

1273 case Mips::SH16_MM:

1274 case Mips::SH16_MMR6:

1276 break;

1277 case Mips::LW16_MM:

1278 case Mips::SW16_MM:

1279 case Mips::SW16_MMR6:

1281 break;

1282 }

1283

1285}

1286

1290 unsigned Offset = Insn & 0x1F;

1292

1294

1298

1300}

1301

1305 unsigned Offset = Insn & 0x7F;

1307

1309

1313

1315}

1316

1322 case Mips::LWM16_MMR6:

1323 case Mips::SWM16_MMR6:

1325 break;

1326 default:

1328 break;

1329 }

1330

1334

1337

1339}

1340

1347

1350

1351 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)

1353

1357

1359}

1360

1367

1370

1372 case Mips::SWM32_MM:

1373 case Mips::LWM32_MM:

1379 break;

1380 case Mips::SC_MM:

1382 [[fallthrough]];

1383 default:

1385 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)

1387

1390 }

1391

1393}

1394

1411

1427

1431

1432

1436

1439

1443

1445}

1446

1462

1478

1495

1512

1519

1520 MCRegister Rt = getReg(Decoder, Mips::GPR32RegClassID, RtNo);

1522

1523 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){

1525 }

1526

1530

1532}

1533

1541

1549

1557

1566

1575

1584

1592

1600

1608

1617

1625

1633

1639 else if (Value == 0x7)

1641 else

1644}

1645

1649 if (Value == 0x7F)

1651 else

1654}

1655

1662

1663template <unsigned Bits, int Offset, int Scale>

1667 Value &= ((1 << Bits) - 1);

1671}

1672

1673template <unsigned Bits, int Offset = 0, int ScaleBy = 1>

1681

1682template <unsigned Bits, int Offset>

1689

1692

1693

1694

1696 int Size = (int) Insn - Pos + 1;

1699}

1700

1707

1714

1717 int32_t DecodedValue;

1718 switch (Insn) {

1719 case 0: DecodedValue = 256; break;

1720 case 1: DecodedValue = 257; break;

1721 case 510: DecodedValue = -258; break;

1722 case 511: DecodedValue = -257; break;

1724 }

1727}

1728

1732

1734 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,

1735 16, 31, 32, 63, 64, 255, 32768, 65535};

1738}

1739

1743 switch (RegPair) {

1744 default:

1746 case 0:

1749 break;

1750 case 1:

1753 break;

1754 case 2:

1757 break;

1758 case 3:

1761 break;

1762 case 4:

1765 break;

1766 case 5:

1769 break;

1770 case 6:

1773 break;

1774 case 7:

1777 break;

1778 }

1779

1781}

1782

1790

1791 unsigned RegRs;

1792 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())

1795 else

1800

1805

1807}

1808

1815

1816template

1820

1821

1822

1823

1824

1825

1826

1829 InsnType Imm = 0;

1830 bool HasRs = false;

1831 bool HasRt = false;

1832

1833 if (Rt == 0)

1835 else if (Rs == 0) {

1836 MI.setOpcode(Mips::BGTZALC_MMR6);

1837 HasRt = true;

1839 }

1840 else if (Rs == Rt) {

1841 MI.setOpcode(Mips::BLTZALC_MMR6);

1842 HasRs = true;

1844 }

1845 else {

1846 MI.setOpcode(Mips::BLTUC_MMR6);

1847 HasRs = true;

1848 HasRt = true;

1850 }

1851

1852 if (HasRs)

1853 MI.addOperand(

1855

1856 if (HasRt)

1857 MI.addOperand(

1859

1861

1863}

1864

1865template

1869

1870

1871

1872

1873

1874

1875

1878 InsnType Imm = 0;

1879 bool HasRs = false;

1880

1881 if (Rt == 0)

1883 else if (Rs == 0) {

1884 MI.setOpcode(Mips::BLEZALC_MMR6);

1886 }

1887 else if (Rs == Rt) {

1888 MI.setOpcode(Mips::BGEZALC_MMR6);

1890 }

1891 else {

1892 HasRs = true;

1893 MI.setOpcode(Mips::BGEUC_MMR6);

1895 }

1896

1897 if (HasRs)

1898 MI.addOperand(

1900 MI.addOperand(

1902

1904

1906}

1907

1908

1909

1910

1916

1917#include "MipsGenDisassemblerTables.inc"

1918

1919

1920

1923 bool IsBigEndian) {

1924

1925 if (Bytes.size() < 2) {

1928 }

1929

1930 if (IsBigEndian) {

1931 Insn = (Bytes[0] << 8) | Bytes[1];

1932 } else {

1933 Insn = (Bytes[1] << 8) | Bytes[0];

1934 }

1935

1937}

1938

1939

1940

1943 bool IsBigEndian, bool IsMicroMips) {

1944

1945 if (Bytes.size() < 4) {

1948 }

1949

1950

1951

1952

1953

1954

1955

1956

1957

1958 if (IsBigEndian) {

1959

1960 Insn =

1961 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);

1962 } else {

1963 if (IsMicroMips) {

1964 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |

1965 (Bytes[1] << 24);

1966 } else {

1967 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |

1968 (Bytes[3] << 24);

1969 }

1970 }

1971

1973}

1974

1979 uint32_t Insn;

1982

1983 if (IsMicroMips) {

1987

1988 if (hasMips32r6()) {

1990 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");

1991

1992

1993 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,

1998 }

1999 }

2000

2001 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");

2002

2003

2004 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,

2005 this, STI);

2009 }

2010

2014

2015 if (hasMips32r6()) {

2017 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");

2018

2019 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,

2024 }

2025 }

2026

2027 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");

2028

2029 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,

2030 this, STI);

2034 }

2035

2036 if (isFP64()) {

2037 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");

2038 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,

2043 }

2044 }

2045

2046

2047

2048

2049

2050

2053 }

2054

2055

2056

2057

2061

2062

2064

2065 if (hasCOP3()) {

2066 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");

2068 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);

2071 }

2072

2073 if (hasMips32r6() && isGP64()) {

2075 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");

2076 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,

2080 }

2081

2082 if (hasMips32r6() && isPTR64()) {

2084 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");

2085 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,

2089 }

2090

2091 if (hasMips32r6()) {

2092 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");

2093 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,

2097 }

2098

2099 if (hasMips2() && isPTR64()) {

2101 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");

2102 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,

2106 }

2107

2108 if (hasCnMips()) {

2109 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");

2110 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this,

2111 STI);

2114 }

2115

2116 if (hasCnMipsP()) {

2117 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");

2118 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address,

2119 this, STI);

2122 }

2123

2124 if (isGP64()) {

2125 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");

2126 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this,

2127 STI);

2130 }

2131

2132 if (isFP64()) {

2134 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");

2135 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address,

2136 this, STI);

2139 }

2140

2141 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");

2142

2144 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);

2147

2149}

MCDisassembler::DecodeStatus DecodeStatus

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

#define LLVM_EXTERNAL_VISIBILITY

static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1656

static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1496

static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1701

static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1044

static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:638

static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:241

static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)

Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.

Definition MipsDisassembler.cpp:1941

static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1558

static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1626

static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:982

static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:993

static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:230

static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1003

static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1095

static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)

Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.

Definition MipsDisassembler.cpp:1921

static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:889

static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1675

static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1809

static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:910

static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1542

static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1341

static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1783

static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:859

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

Definition MipsDisassembler.cpp:106

static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:556

static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:817

static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1183

static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1111

static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:873

static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:186

static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1576

static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:110

static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1412

static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1080

static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1156

static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1063

static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1715

static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1447

static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1665

static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1361

static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:775

static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:900

static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1646

static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition MipsDisassembler.cpp:87

static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1708

static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1463

static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:940

static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:595

static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:219

static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1534

static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1317

static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:682

static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1601

static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:410

static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1911

static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1593

static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1729

static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:197

static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:934

static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1230

static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition MipsDisassembler.cpp:81

static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:946

static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:164

static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:444

static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1740

static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:342

static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1567

static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1609

static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:120

static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:357

static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:153

static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1513

static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:142

static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1170

static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:956

static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1683

static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:269

static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:371

static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1287

static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1634

static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:208

static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:175

static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1428

static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1127

static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1395

static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:928

static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1585

static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:971

static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:878

static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1866

static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1618

static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:483

static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1143

static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1550

static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:131

static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1479

static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1817

static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:517

static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:965

static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1690

static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:731

static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1024

static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1013

static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:922

static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:294

static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)

Definition MipsDisassembler.cpp:1302

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()

Definition MipsDisassembler.cpp:94

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

void addOperand(const MCOperand Op)

const MCOperand & getOperand(unsigned i) const

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheMips64Target()

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Target & getTheMips64elTarget()

Target & getTheMipselTarget()

constexpr int32_t SignExtend32(uint32_t X)

Sign-extend the number in the bottom B bits of X to a 32-bit integer.

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

Target & getTheMipsTarget()

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.