MipsMCCodeEmitter.cpp Source File (original) (raw)

32#include

33#include

35using namespace llvm;

37#define DEBUG_TYPE "mccodeemitter"

39#define GET_INSTRMAP_INFO

40#include "MipsGenInstrInfo.inc"

41#undef GET_INSTRMAP_INFO

43namespace llvm {

55}

59 bool PCRel = false;

60 switch (Kind) {

76 PCRel = true;

77 }

79}

88 if (Shift <= 31)

89 return;

90 Shift -= 32;

96 default:

99 case Mips::DSLL:

101 return;

102 case Mips::DSRL:

104 return;

105 case Mips::DSRA:

107 return;

108 case Mips::DROTR:

110 return;

111 }

112}

113

114

115void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {

116

117

120

121 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);

122 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);

123

124 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||

125 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {

126 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");

127 if (Reg0 < Reg1)

128 return;

129 } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {

130 if (Reg0 >= Reg1)

131 return;

132 } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||

133 Inst.getOpcode() == Mips::BOVC_MMR6) {

134 if (Reg1 >= Reg0)

135 return;

136 } else

138

141}

142

143bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {

144 return STI.hasFeature(Mips::FeatureMicroMips);

145}

146

147bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {

148 return STI.hasFeature(Mips::FeatureMips32r6);

149}

150

154

155

156

161

162

163

164

166 switch (MI.getOpcode()) {

167

168 case Mips::DSLL:

169 case Mips::DSRL:

170 case Mips::DSRA:

171 case Mips::DROTR:

173 break;

174

175 case Mips::BEQC:

176 case Mips::BNEC:

177 case Mips::BEQC64:

178 case Mips::BNEC64:

179 case Mips::BOVC:

180 case Mips::BOVC_MMR6:

181 case Mips::BNVC:

182 case Mips::BNVC_MMR6:

183 LowerCompactBranch(TmpInst);

184 }

185

186 size_t N = Fixups.size();

188

189

190

191

192 const unsigned Opcode = TmpInst.getOpcode();

193 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&

194 (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)

195 llvm_unreachable("unimplemented opcode in encodeInstruction()");

196

197 int NewOpcode = -1;

198 if (isMicroMips(STI)) {

199 if (isMips32r6(STI)) {

200 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);

201 if (NewOpcode == -1)

202 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);

203 }

204 else

205 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);

206

207

208 if (NewOpcode == -1)

209 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);

210

211 if (NewOpcode != -1) {

212 if (Fixups.size() > N)

213 Fixups.pop_back();

214

217 }

218

219 if (((MI.getOpcode() == Mips::MOVEP_MM) ||

220 (MI.getOpcode() == Mips::MOVEP_MMR6))) {

222 Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);

223 }

224 }

225

227

228

229 unsigned Size = Desc.getSize();

232

233 auto Endian =

235 if (Size == 2) {

237 } else if (IsLittleEndian && isMicroMips(STI)) {

240 } else {

242 }

243}

244

245

246

247

252 const MCOperand &MO = MI.getOperand(OpNo);

253

254

256

258 "getBranchTargetOpValue expects only expressions or immediates");

259

263 return 0;

264}

265

266

267

268

273 const MCOperand &MO = MI.getOperand(OpNo);

274

275

277

279 "getBranchTargetOpValue expects only expressions or immediates");

280

284 return 0;

285}

286

287

288

289

294 const MCOperand &MO = MI.getOperand(OpNo);

295

296

298 return MO.getImm() >> 1;

299

301 "getBranchTargetOpValueMMR6 expects only expressions or immediates");

302

306 return 0;

307}

308

309

310

311

316 const MCOperand &MO = MI.getOperand(OpNo);

317

318

320 return MO.getImm() >> 2;

321

323 "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");

324

328 return 0;

329}

330

331

332

333

338 const MCOperand &MO = MI.getOperand(OpNo);

339

340

342

344 "getBranchTargetOpValueMM expects only expressions or immediates");

345

348 return 0;

349}

350

351

352

353

358 const MCOperand &MO = MI.getOperand(OpNo);

359

360

362

364 "getBranchTargetOpValuePC10 expects only expressions or immediates");

365

368 return 0;

369}

370

371

372

373

378 const MCOperand &MO = MI.getOperand(OpNo);

379

380

382

384 "getBranchTargetOpValueMM expects only expressions or immediates");

385

388 return 0;

389}

390

391

392

393

398 const MCOperand &MO = MI.getOperand(OpNo);

399

400

402

404 "getBranchTarget21OpValue expects only expressions or immediates");

405

409 return 0;

410}

411

412

413

414

419 const MCOperand &MO = MI.getOperand(OpNo);

420

421

423

425 "getBranchTarget21OpValueMM expects only expressions or immediates");

426

430 return 0;

431}

432

433

434

435

440 const MCOperand &MO = MI.getOperand(OpNo);

441

442

444

446 "getBranchTarget26OpValue expects only expressions or immediates");

447

451 return 0;

452}

453

454

455

456

460 const MCOperand &MO = MI.getOperand(OpNo);

461

462

464 return MO.getImm() >> 1;

465

467 "getBranchTarget26OpValueMM expects only expressions or immediates");

468

472 return 0;

473}

474

475

476

477

482 const MCOperand &MO = MI.getOperand(OpNo);

483

485

487 "getJumpOffset16OpValue expects only expressions or an immediate");

488

493 return 0;

494}

495

496

497

498

503 const MCOperand &MO = MI.getOperand(OpNo);

504

506

508 "getJumpTargetOpValue expects only expressions or an immediate");

509

512 return 0;

513}

514

519 const MCOperand &MO = MI.getOperand(OpNo);

520

522

524 "getJumpTargetOpValueMM expects only expressions or an immediate");

525

528 return 0;

529}

530

535 const MCOperand &MO = MI.getOperand(OpNo);

536 if (MO.isImm()) {

537

539 assert((Res & 3) == 0);

540 return Res >> 2;

541 }

542

544 "getUImm5Lsl2Encoding expects only expressions or an immediate");

545

546 return 0;

547}

548

553 const MCOperand &MO = MI.getOperand(OpNo);

554 if (MO.isImm()) {

556 return Value >> 2;

557 }

558

559 return 0;

560}

561

566 const MCOperand &MO = MI.getOperand(OpNo);

567 if (MO.isImm()) {

569 return Value >> 2;

570 }

571

572 return 0;

573}

574

579 const MCOperand &MO = MI.getOperand(OpNo);

580 if (MO.isImm()) {

581 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;

582 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));

583 }

584

585 return 0;

586}

587

594

596 switch (MipsExpr->getSpecifier()) {

600 break;

602

603

604 return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI);

607 break;

610 break;

614 break;

618 break;

622 break;

626 break;

630 break;

634 break;

637 break;

640 break;

644 break;

648 break;

651 break;

653

657 else

660 break;

664 break;

668 break;

670

674 else

677 break;

680 break;

683 break;

687 break;

691 break;

695 break;

699 break;

703 break;

704 }

706 return 0;

707 }

708

709 Ctx.reportError(Expr->getLoc(), "expected an immediate");

710 return 0;

711}

712

713

714

719 if (MO.isReg()) {

721 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);

722 return RegNo;

723 } else if (MO.isImm()) {

724 return static_cast<unsigned>(MO.getImm());

727 }

728

729

732}

733

739 assert(MO.isExpr() && "getImmOpValue expects only expressions or immediates");

741 int64_t Res;

742 if (Expr->evaluateAsAbsolute(Res))

743 return Res;

747 return 0;

748 }

750}

751

752

753

754template

758

759 assert(MI.getOperand(OpNo).isReg());

761 << 16;

763

764

765 OffBits >>= ShiftAmount;

766

767 return (OffBits & 0xFFFF) | RegBits;

768}

769

774

775 assert(MI.getOperand(OpNo).isReg());

777 Fixups, STI) << 4;

779 Fixups, STI);

780

781 return (OffBits & 0xF) | RegBits;

782}

783

788

789 assert(MI.getOperand(OpNo).isReg());

791 Fixups, STI) << 4;

793 Fixups, STI) >> 1;

794

795 return (OffBits & 0xF) | RegBits;

796}

797

802

803 assert(MI.getOperand(OpNo).isReg());

805 Fixups, STI) << 4;

807 Fixups, STI) >> 2;

808

809 return (OffBits & 0xF) | RegBits;

810}

811

816

817 assert(MI.getOperand(OpNo).isReg() &&

818 (MI.getOperand(OpNo).getReg() == Mips::SP ||

819 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&

820 "Unexpected base register!");

822 Fixups, STI) >> 2;

823

824 return OffBits & 0x1F;

825}

826

831

832 assert(MI.getOperand(OpNo).isReg() &&

833 MI.getOperand(OpNo).getReg() == Mips::GP &&

834 "Unexpected base register!");

835

837 Fixups, STI) >> 2;

838

839 return OffBits & 0x7F;

840}

841

846

847 assert(MI.getOperand(OpNo).isReg());

849 STI) << 16;

850 unsigned OffBits =

852

853 return (OffBits & 0x1FF) | RegBits;

854}

855

860

861 assert(MI.getOperand(OpNo).isReg());

863 STI) << 16;

865

866 return (OffBits & 0x07FF) | RegBits;

867}

868

873

874

875 switch (MI.getOpcode()) {

876 default:

877 break;

878 case Mips::SWM32_MM:

879 case Mips::LWM32_MM:

880 OpNo = MI.getNumOperands() - 2;

881 break;

882 }

883

884

885 assert(MI.getOperand(OpNo).isReg());

887 << 16;

889

890 return (OffBits & 0x0FFF) | RegBits;

891}

892

897

898 assert(MI.getOperand(OpNo).isReg());

900 STI) << 16;

902

903 return (OffBits & 0xFFFF) | RegBits;

904}

905

910

911

912 switch (MI.getOpcode()) {

913 default:

914 break;

915 case Mips::SWM16_MM:

916 case Mips::SWM16_MMR6:

917 case Mips::LWM16_MM:

918 case Mips::LWM16_MMR6:

919 OpNo = MI.getNumOperands() - 2;

920 break;

921 }

922

923

924 assert(MI.getOperand(OpNo).isReg());

925

926 assert(MI.getOperand(OpNo+1).isImm());

928

929 return ((OffBits >> 2) & 0x0F);

930}

931

932

933

934unsigned

938 assert(MI.getOperand(OpNo-1).isImm());

939 assert(MI.getOperand(OpNo).isImm());

942

943 return Position + Size - 1;

944}

945

946template <unsigned Bits, int Offset>

947unsigned

951 assert(MI.getOperand(OpNo).isImm());

955}

956

957unsigned

961 const MCOperand &MO = MI.getOperand(OpNo);

962 if (MO.isImm()) {

963

965 assert((Res & 3) == 0);

966 return Res >> 2;

967 }

968

970 "getSimm19Lsl2Encoding expects only expressions or an immediate");

971

976 return 0;

977}

978

979unsigned

983 const MCOperand &MO = MI.getOperand(OpNo);

984 if (MO.isImm()) {

985

987 assert((Res & 7) == 0);

988 return Res >> 3;

989 }

990

992 "getSimm18Lsl2Encoding expects only expressions or an immediate");

993

998 return 0;

999}

1000

1001unsigned

1009

1010unsigned

1014 assert(MI.getOperand(OpNo).isImm());

1015 const MCOperand &MO = MI.getOperand(OpNo);

1017 switch (Value) {

1018 case 128: return 0x0;

1019 case 1: return 0x1;

1020 case 2: return 0x2;

1021 case 3: return 0x3;

1022 case 4: return 0x4;

1023 case 7: return 0x5;

1024 case 8: return 0x6;

1025 case 15: return 0x7;

1026 case 16: return 0x8;

1027 case 31: return 0x9;

1028 case 32: return 0xa;

1029 case 63: return 0xb;

1030 case 64: return 0xc;

1031 case 255: return 0xd;

1032 case 32768: return 0xe;

1033 case 65535: return 0xf;

1034 }

1036}

1037

1038unsigned

1042 unsigned res = 0;

1043

1044

1045

1046

1047 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {

1049 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);

1050 if (RegNo != 31)

1051 res++;

1052 else

1053 res |= 0x10;

1054 }

1055 return res;

1056}

1057

1058unsigned

1062 return (MI.getNumOperands() - 4);

1063}

1064

1065unsigned

1069 unsigned res = 0;

1070

1071 if (MI.getOperand(0).getReg() == Mips::A1 &&

1072 MI.getOperand(1).getReg() == Mips::A2)

1073 res = 0;

1074 else if (MI.getOperand(0).getReg() == Mips::A1 &&

1075 MI.getOperand(1).getReg() == Mips::A3)

1076 res = 1;

1077 else if (MI.getOperand(0).getReg() == Mips::A2 &&

1078 MI.getOperand(1).getReg() == Mips::A3)

1079 res = 2;

1080 else if (MI.getOperand(0).getReg() == Mips::A0 &&

1081 MI.getOperand(1).getReg() == Mips::S5)

1082 res = 3;

1083 else if (MI.getOperand(0).getReg() == Mips::A0 &&

1084 MI.getOperand(1).getReg() == Mips::S6)

1085 res = 4;

1086 else if (MI.getOperand(0).getReg() == Mips::A0 &&

1087 MI.getOperand(1).getReg() == Mips::A1)

1088 res = 5;

1089 else if (MI.getOperand(0).getReg() == Mips::A0 &&

1090 MI.getOperand(1).getReg() == Mips::A2)

1091 res = 6;

1092 else if (MI.getOperand(0).getReg() == Mips::A0 &&

1093 MI.getOperand(1).getReg() == Mips::A3)

1094 res = 7;

1095

1096 return res;

1097}

1098

1099unsigned

1103 assert(((OpNo == 2) || (OpNo == 3)) &&

1104 "Unexpected OpNo for movep operand encoding!");

1105

1107 assert(Op.isReg() && "Operand of movep is not a register!");

1108 switch (Op.getReg().id()) {

1109 default:

1111 case Mips::ZERO: return 0;

1112 case Mips::S1: return 1;

1113 case Mips::V0: return 2;

1114 case Mips::V1: return 3;

1115 case Mips::S0: return 4;

1116 case Mips::S2: return 5;

1117 case Mips::S3: return 6;

1118 case Mips::S4: return 7;

1119 }

1120}

1121

1122unsigned

1126 const MCOperand &MO = MI.getOperand(OpNo);

1127 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");

1128

1129 unsigned Res = static_cast<unsigned>(MO.getImm());

1130 assert((Res & 3) == 0);

1131 return Res >> 2;

1132}

1133

1134#include "MipsGenMCCodeEmitter.inc"

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file declares a class to represent arbitrary precision floating point values and provide a varie...

This file implements a class to represent arbitrary precision integral constant values and operations...

static void LowerLargeShift(MCInst &Inst)

Definition MipsMCCodeEmitter.cpp:83

This file defines the SmallVector class.

static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())

MCCodeEmitter - Generic instruction encoding interface.

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

@ Specifier

Expression with a relocation specifier.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

Instances of this class represent a single low-level machine instruction.

unsigned getNumOperands() const

unsigned getOpcode() const

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Describe properties that are true of each instruction in the target description file.

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

void setReg(MCRegister Reg)

Set the register number.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

uint64_t getDFPImm() const

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:313

unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1123

unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTarget21OpValue - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:395

uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:958

unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:516

unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getMachineOpValue - Return binary encoding of operand.

Definition MipsMCCodeEmitter.cpp:716

unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Subtract Offset then encode as a N-bit unsigned integer.

Definition MipsMCCodeEmitter.cpp:948

unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:843

unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:935

unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1066

unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTargetOpValueMMR6 - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:291

unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTargetOpValue - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:249

unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1059

unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:828

unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:813

unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:771

unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Return binary encoding of memory related operand.

Definition MipsMCCodeEmitter.cpp:755

unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTarget26OpValue - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:437

unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTarget26OpValueMM - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:457

unsigned getImmOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:734

unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand.

Definition MipsMCCodeEmitter.cpp:270

unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:980

unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:550

unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getJumpOffset16OpValue - Return binary encoding of the jump target operand.

Definition MipsMCCodeEmitter.cpp:479

unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand.

Definition MipsMCCodeEmitter.cpp:355

unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getJumpTargetOpValue - Return binary encoding of the jump target operand.

Definition MipsMCCodeEmitter.cpp:500

unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1011

unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1039

unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:857

unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:532

unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:907

unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:894

unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:589

unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand.

Definition MipsMCCodeEmitter.cpp:375

unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1100

unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:576

void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override

encodeInstruction - Emit the instruction.

Definition MipsMCCodeEmitter.cpp:157

unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:1002

unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS.

Definition MipsMCCodeEmitter.cpp:416

unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:799

unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand.

Definition MipsMCCodeEmitter.cpp:335

unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:870

unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:563

void EmitByte(unsigned char C, raw_ostream &OS) const

Definition MipsMCCodeEmitter.cpp:151

unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition MipsMCCodeEmitter.cpp:785

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

static unsigned getFormat(uint64_t TSFlags)

@ fixup_MICROMIPS_TLS_TPREL_LO16

@ fixup_MICROMIPS_GOT_PAGE

@ fixup_MICROMIPS_PC16_S1

@ fixup_MICROMIPS_TLS_TPREL_HI16

@ fixup_MICROMIPS_PC21_S1

@ fixup_MICROMIPS_GPOFF_LO

@ fixup_MICROMIPS_PC19_S2

@ fixup_MICROMIPS_TLS_LDM

@ fixup_MICROMIPS_GOT_OFST

@ fixup_MICROMIPS_TLS_DTPREL_HI16

@ fixup_MICROMIPS_PC10_S1

@ fixup_MICROMIPS_HIGHEST

@ fixup_MICROMIPS_GOT_DISP

@ fixup_MICROMIPS_PC18_S3

@ fixup_MICROMIPS_PC26_S1

@ fixup_MICROMIPS_GOTTPREL

@ fixup_MICROMIPS_TLS_DTPREL_LO16

@ fixup_Mips_Branch_PCRel

@ fixup_MICROMIPS_GPOFF_HI

bool isGpOff(const MCSpecifierExpr &E)

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCContext &Ctx)

Definition MipsMCCodeEmitter.cpp:50

MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCContext &Ctx)

Definition MipsMCCodeEmitter.cpp:45

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

static Lanai::Fixups FixupKind(const MCExpr *Expr)

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)

To bit_cast(const From &from) noexcept

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.