MipsSubtarget.cpp Source File (original) (raw)

28using namespace llvm;

30#define DEBUG_TYPE "mips-subtarget"

32#define GET_SUBTARGETINFO_TARGET_DESC

33#define GET_SUBTARGETINFO_CTOR

34#include "MipsGenSubtargetInfo.inc"

40 cl::desc("Allow for a mixture of Mips16 "

41 "and Mips32 code in a single output file"),

45 cl::desc("Compile all functions that don't use "

46 "floating point as Mips 16"),

50 cl::desc("Enable mips16 hard float."),

55 cl::desc("Enable mips16 constant islands."),

60 cl::desc("Enable gp-relative addressing of mips small data items"));

62bool MipsSubtarget::DspWarningPrinted = false;

63bool MipsSubtarget::MSAWarningPrinted = false;

64bool MipsSubtarget::VirtWarningPrinted = false;

65bool MipsSubtarget::CRCWarningPrinted = false;

66bool MipsSubtarget::GINVWarningPrinted = false;

67bool MipsSubtarget::MIPS1WarningPrinted = false;

69void MipsSubtarget::anchor() {}

75 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),

77 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),

79 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),

80 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),

86 UseIndirectJumpsHazard(false), StrictAlign(false),

87 StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),

88 InstrInfo(

89 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),

93 if (MipsArchVersion == MipsDefault)

94 MipsArchVersion = Mips32;

97 if (MipsArchVersion == Mips1 && !MIPS1WarningPrinted) {

98 errs() << "warning: MIPS-I support is experimental\n";

99 MIPS1WarningPrinted = true;

100 }

101

102

103

104 if (MipsArchVersion == Mips5)

105 report_fatal_error("Code generation for MIPS-V is not implemented", false);

106

107

109 "Invalid Arch & ABI pair.");

110

112 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "

113 "See -mattr=+fp64.",

114 false);

115

118 "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "

119 "Use -mcpu=mips32r2 or greater.", false);

120

122 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);

123

125 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);

126

129

130 if ( $isABI\_O32$ () && InMicroMipsMode)

132

133 if (UseIndirectJumpsHazard) {

134 if (InMicroMipsMode)

136 "cannot combine indirect jumps with hazard barriers and microMIPS");

139 "indirect jumps with hazard barriers requires MIPS32R2 or later");

140 }

142 report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given "

143 "architecture.",

144 false);

145 }

146

149

154 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);

155 }

156

157 if (NoABICalls && TM.isPositionIndependent())

158 report_fatal_error("position-independent code requires '-mabicalls'");

159

161 NoABICalls = true;

162

163

164 UseSmallSection = GPOpt;

165 if (!NoABICalls && GPOpt) {

166 errs() << "warning: cannot use small-data accesses for '-mabicalls'"

167 << "\n";

168 UseSmallSection = false;

169 }

170

171 if (hasDSPR2() && !DspWarningPrinted) {

173 errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "

174 << "greater\n";

175 DspWarningPrinted = true;

177 errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "

178 << "greater\n";

179 DspWarningPrinted = true;

180 }

181 } else if (hasDSP() && !DspWarningPrinted) {

183 errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "

184 << "greater\n";

185 DspWarningPrinted = true;

187 errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "

188 << "greater\n";

189 DspWarningPrinted = true;

190 }

191 }

192

194

196 errs() << "warning: the 'msa' ASE requires " << ArchName

197 << " revision 5 or greater\n";

198 MSAWarningPrinted = true;

199 }

201 errs() << "warning: the 'virt' ASE requires " << ArchName

202 << " revision 5 or greater\n";

203 VirtWarningPrinted = true;

204 }

206 errs() << "warning: the 'crc' ASE requires " << ArchName

207 << " revision 6 or greater\n";

208 CRCWarningPrinted = true;

209 }

211 errs() << "warning: the 'ginv' ASE requires " << ArchName

212 << " revision 6 or greater\n";

213 GINVWarningPrinted = true;

214 }

215

216 TSInfo = std::make_unique();

217

220

224}

225

227

230}

231

232

234

236 CriticalPathRCs.clear();

237 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass

238 : &Mips::GPR32RegClass);

239}

240

243}

244

249

250

252

253 InstrItins = getInstrItineraryForCPU(CPUName);

254

255 if (InMips16Mode && !IsSoftFloat)

256 InMips16HardFloat = true;

257

258 if (StackAlignOverride)

259 stackAlignment = *StackAlignOverride;

261 stackAlignment = Align(16);

262 else {

263 assert(isABI_O32() && "Unknown ABI for stack alignment!");

264 stackAlignment = Align(8);

265 }

266

268 report_fatal_error("64-bit code requested on a subtarget that doesn't "

269 "support it!");

270

271 return *this;

272}

273

276 << "\n");

278}

279

282}

283

288

290 return TSInfo.get();

291}

292

295}

296

299}

300

303}

304

307}

This file contains the simple types necessary to represent the attributes associated with functions a...

This file describes how to lower LLVM calls to machine code calls.

This file declares the targeting of the Machinelegalizer class for Mips.

This file declares the targeting of the RegisterBankInfo class for Mips.

static cl::opt< bool > Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden, cl::desc("Enable mips16 constant islands."), cl::init(true))

static cl::opt< bool > Mixed16_32("mips-mixed-16-32", cl::init(false), cl::desc("Allow for a mixture of Mips16 " "and Mips32 code in a single output file"), cl::Hidden)

static cl::opt< bool > Mips16HardFloat("mips16-hard-float", cl::NotHidden, cl::desc("Enable mips16 hard float."), cl::init(false))

static cl::opt< bool > Mips_Os16("mips-os16", cl::init(false), cl::desc("Compile all functions that don't use " "floating point as Mips 16"), cl::Hidden)

static cl::opt< bool > GPOpt("mgpopt", cl::Hidden, cl::desc("Enable gp-relative addressing of mips small data items"))

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This class provides legalization strategies.

This class provides the information for the target register banks.

const LegalizerInfo * getLegalizerInfo() const override

static bool useConstantIslands()

bool enablePostRAScheduler() const override

This overrides the PostRAScheduler bit in the SchedModel for each CPU.

std::unique_ptr< InstructionSelector > InstSelector

MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)

const CallLowering * getCallLowering() const override

std::unique_ptr< RegisterBankInfo > RegBankInfo

~MipsSubtarget() override

bool inAbs2008Mode() const

std::unique_ptr< CallLowering > CallLoweringInfo

const MipsRegisterInfo * getRegisterInfo() const override

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

const RegisterBankInfo * getRegBankInfo() const override

bool isPositionIndependent() const

InstructionSelector * getInstructionSelector() const override

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

const MipsTargetLowering * getTargetLowering() const override

void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override

MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride)

This constructor initializes the data members to match that of the specified triple.

Reloc::Model getRelocationModel() const

CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override

const MipsABIInfo & getABI() const

Holds all the information related to register banks.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

Primary interface to the complete machine description for the target machine.

bool isPositionIndependent() const

Reloc::Model getRelocationModel() const

Returns the code generation relocation model.

Triple - Helper class for working with autoconf configuration names.

StringRef selectMipsCPU(const Triple &TT, StringRef CPU)

Select the Mips CPU for the given triple and cpu name.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

InstructionSelector * createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, const MipsRegisterBankInfo &)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

CodeGenOptLevel

Code generation optimization level.

raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

This struct is a compact representation of a valid (non-zero power of two) alignment.

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.