NVPTXISelDAGToDAG.cpp File Reference (original) (raw)

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Macros
#define	DEBUG_TYPE "nvptx-isel"
#define	PASS_NAME "NVPTX DAG->DAG Pattern Instruction Selection"
#define	TCGEN05_LD_OPCODE(SHAPE, NUM)
#define	CP_ASYNC_BULK_TENSOR_OPCODE(dir, dim, mode, is_s32, suffix)
#define	GET_CP_ASYNC_BULK_TENSOR_OPCODE_S2G_RED(dim, mode, is_ch, is_s32)
#define	TCGEN05_ST_OPCODE(SHAPE, NUM)

Functions
static unsigned	getTcgen05LdOpcode (unsigned IID, bool enablePack)
static std::optional< NVPTX::AddressSpace >	convertAS (unsigned AS)
static bool	canLowerToLDG (const MemSDNode &N, const NVPTXSubtarget &Subtarget, NVPTX::AddressSpace CodeAddrSpace)
static unsigned int	getFenceOp (NVPTX::Ordering O, NVPTX::Scope S, NVPTXSubtarget const *T)
static std::optional< unsigned >	pickOpcodeForVT (MVT::SimpleValueType VT, std::optional< unsigned > Opcode_i16, std::optional< unsigned > Opcode_i32, std::optional< unsigned > Opcode_i64)
static bool	isAddLike (const SDValue V)
static SDValue	stripAssertAlign (SDValue N)
static SDValue	selectBaseADDR (SDValue N, SelectionDAG *DAG)
static SDValue	accumulateOffset (SDValue &Addr, SDLoc DL, SelectionDAG *DAG)
static std::pair< SDValue, SDValue >	selectADDR (SDValue Addr, SelectionDAG *DAG)
static unsigned	getStoreVectorNumElts (SDNode *N)
static unsigned	GetCpAsyncBulkTensorS2GReductionOpcode (size_t Dim, bool IsShared32, bool IsCacheHint, bool IsIm2Col)
static unsigned	getTcgen05StOpcode (unsigned IID, bool enableUnpack)

Variables
static cl::opt< bool >	EnableRsqrtOpt ("nvptx-rsqrt-approx-opt", cl::init(true), cl::Hidden, cl::desc("Enable reciprocal sqrt optimization"))
static cl::opt< bool >	EnableMADWide ("nvptx-mad-wide-opt", cl::init(false), cl::Hidden, cl::desc("Enable MAD wide optimization"))

◆ CP_ASYNC_BULK_TENSOR_OPCODE

#define CP_ASYNC_BULK_TENSOR_OPCODE	(	dir,
dim,
mode,
is_s32,
suffix )

Value:

(is_s32 \

? NVPTX::CP_ASYNC_BULK_TENSOR_##dir##_##dim##_SHARED32_##mode##suffix \

: NVPTX::CP_ASYNC_BULK_TENSOR_##dir##_##dim##_##mode##suffix)

amode Optimize addressing mode

Definition at line 1902 of file NVPTXISelDAGToDAG.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE "nvptx-isel"

◆ GET_CP_ASYNC_BULK_TENSOR_OPCODE_S2G_RED

#define GET_CP_ASYNC_BULK_TENSOR_OPCODE_S2G_RED	(	dim,
mode,
is_ch,
is_s32 )

Value:

(is_ch ? (CP_ASYNC_BULK_TENSOR_OPCODE(RED, dim, mode, is_s32, _CH)) \

: (CP_ASYNC_BULK_TENSOR_OPCODE(RED, dim, mode, is_s32, )))

#define CP_ASYNC_BULK_TENSOR_OPCODE(dir, dim, mode, is_s32, suffix)

Definition at line 1907 of file NVPTXISelDAGToDAG.cpp.

Referenced by GetCpAsyncBulkTensorS2GReductionOpcode().

◆ PASS_NAME

◆ TCGEN05_LD_OPCODE

#define TCGEN05_LD_OPCODE	(	SHAPE,
NUM )

◆ TCGEN05_ST_OPCODE

#define TCGEN05_ST_OPCODE	(	SHAPE,
NUM )

◆ accumulateOffset()

◆ canLowerToLDG()

◆ convertAS()

Definition at line 496 of file NVPTXISelDAGToDAG.cpp.

References llvm::NVPTXAS::ADDRESS_SPACE_CONST, llvm::NVPTXAS::ADDRESS_SPACE_GENERIC, llvm::NVPTXAS::ADDRESS_SPACE_GLOBAL, llvm::NVPTXAS::ADDRESS_SPACE_LOCAL, llvm::NVPTXAS::ADDRESS_SPACE_PARAM, llvm::NVPTXAS::ADDRESS_SPACE_SHARED, llvm::NVPTXAS::ADDRESS_SPACE_SHARED_CLUSTER, llvm::NVPTX::Const, llvm::NVPTX::Generic, llvm::NVPTX::Global, llvm::NVPTX::Local, llvm::NVPTX::Param, llvm::NVPTX::Shared, and llvm::NVPTX::SharedCluster.

Referenced by llvm::NVPTXDAGToDAGISel::getAddrSpace().

◆ GetCpAsyncBulkTensorS2GReductionOpcode()

unsigned GetCpAsyncBulkTensorS2GReductionOpcode ( size_t Dim, bool IsShared32, bool IsCacheHint, bool IsIm2Col )	static

◆ getFenceOp()

Definition at line 796 of file NVPTXISelDAGToDAG.cpp.

References llvm::NVPTX::Acquire, llvm::NVPTX::AcquireRelease, llvm::NVPTX::Block, llvm::NVPTX::Cluster, llvm::NVPTX::DefaultDevice, llvm::NVPTX::Device, llvm::formatv(), llvm_unreachable, llvm::NVPTX::NotAtomic, llvm::NVPTX::Relaxed, llvm::NVPTX::RelaxedMMIO, llvm::NVPTX::Release, llvm::report_fatal_error(), llvm::NVPTX::SequentiallyConsistent, llvm::NVPTX::System, T, llvm::NVPTX::Thread, and llvm::NVPTX::Volatile.

◆ getStoreVectorNumElts()

◆ getTcgen05LdOpcode()

◆ getTcgen05StOpcode()

◆ isAddLike()

◆ pickOpcodeForVT()

◆ selectADDR()

◆ selectBaseADDR()

◆ stripAssertAlign()

◆ EnableMADWide

cl::opt< bool > EnableMADWide("nvptx-mad-wide-opt", cl::init(false), cl::Hidden, cl::desc("Enable MAD wide optimization")) ( "nvptx-mad-wide-opt" , cl::init(false) , cl::Hidden , cl::desc("Enable MAD wide optimization") )	static

◆ EnableRsqrtOpt

cl::opt< bool > EnableRsqrtOpt("nvptx-rsqrt-approx-opt", cl::init(true), cl::Hidden, cl::desc("Enable reciprocal sqrt optimization")) ( "nvptx-rsqrt-approx-opt" , cl::init(true) , cl::Hidden , cl::desc("Enable reciprocal sqrt optimization") )	static