PPCInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H

14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H

23#define GET_INSTRINFO_HEADER

24#include "PPCGenInstrInfo.inc"

26namespace llvm {

57};

62 unsigned Imm : 16;

65};

100};

101

102

103#define NoInstr PPC::INSTRUCTION_LIST_END

104#define Pwr8LoadOpcodes \

105 { \

106 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \

107 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \

108 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \

109 PPC::RESTORE_QUADWORD \

110 }

111

112#define Pwr9LoadOpcodes \

113 { \

114 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \

115 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \

116 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \

117 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \

118 }

119

120#define Pwr10LoadOpcodes \

121 { \

122 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \

123 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \

124 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \

125 PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD \

126 }

127

128#define FutureLoadOpcodes \

129 { \

130 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \

131 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \

132 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \

133 PPC::RESTORE_UACC, PPC::RESTORE_WACC, NoInstr, PPC::RESTORE_QUADWORD \

134 }

135

136#define Pwr8StoreOpcodes \

137 { \

138 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \

139 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \

140 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \

141 PPC::SPILL_QUADWORD \

142 }

143

144#define Pwr9StoreOpcodes \

145 { \

146 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \

147 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \

148 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, NoInstr, \

149 PPC::SPILL_QUADWORD \

150 }

151

152#define Pwr10StoreOpcodes \

153 { \

154 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \

155 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \

156 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \

157 NoInstr, NoInstr, PPC::SPILL_QUADWORD \

158 }

159

160#define FutureStoreOpcodes \

161 { \

162 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \

163 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \

164 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \

165 PPC::SPILL_WACC, NoInstr, PPC::SPILL_QUADWORD \

166 }

167

168

169#define StoreOpcodesForSpill \

170 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }

171#define LoadOpcodesForSpill \

172 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }

173

174class PPCSubtarget;

182

183 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,

187 unsigned DestReg, int FrameIdx,

190

191

192

194 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;

195

196

198 unsigned OpNoForForwarding) const;

199

200

202 unsigned ConstantOpNo,

204

205

208 bool KillDefMI) const;

209

210

211

212

213

215 unsigned &OpNoForForwarding,

216 bool &SeenIntermediateUse) const;

217

218

219

221 unsigned OpNoForForwarding) const;

226 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,

229 int64_t &Imm,

230 int64_t BaseImm = 0) const;

231 bool isRegElgibleForForwarding(const MachineOperand &RegMO,

234 bool &IsFwdFeederRegKilled,

235 bool &SeenIntermediateUse) const;

236 unsigned getSpillTarget() const;

240 int16_t getFMAOpIdxInfo(unsigned Opcode) const;

248 virtual void anchor();

249

250protected:

251

252

253

254

255

256

257

258

259

260

262 unsigned OpIdx1,

263 unsigned OpIdx2) const override;

264

265public:

267

270

271

272

273

274

276

279 }

282 }

285 }

288 }

291 }

292

294 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,

295 PPC::VOR, PPC::XXLOR, PPC::XXLORf,

296 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,

297 PPC::EVOR, -1U};

298 for (int i = 0; CopyOpcodes[i] != -1U; i++)

299 if (Opcode == CopyOpcodes[i])

300 return true;

301 return false;

302 }

303

310 }

311

317 }

318

328 }

329

336

339 unsigned *PredCost = nullptr) const override;

340

343 unsigned DefIdx,

345 unsigned UseIdx) const override;

347 SDNode *DefNode, unsigned DefIdx,

349 unsigned UseIdx) const override {

350 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,

351 UseNode, UseIdx);

352 }

353

356 unsigned DefIdx) const override {

357

358

359

360 return false;

361 }

362

364 return true;

365 }

366

367

368

374

375

376

377

379 bool DoRegPressureReduce) const;

380

382

383

384

385

388 bool DoRegPressureReduce) const override;

389

390

391

392

393

397

398

399

400 void

403

405 bool Invert) const override;

406

407

408

409

410

411

412

413

414

416

417

418

421

424 unsigned &SubIdx) const override;

426 int &FrameIndex) const override;

429 int &FrameIndex) const override;

430

432 unsigned &SrcOpIdx2) const override;

433

436

437

438

442 bool AllowModify) const override;

444 int *BytesRemoved = nullptr) const override;

448 int *BytesAdded = nullptr) const override;

449

450

453 int &) const override;

457 Register FalseReg) const override;

458

461 bool KillSrc, bool RenamableDest = false,

462 bool RenamableSrc = false) const override;

463

469

470

471

472

475 unsigned SrcReg, bool isKill, int FrameIndex,

478

484

485

486

487

490 unsigned DestReg, int FrameIndex,

493

495

497

498 bool

500

503

506

507

508

509

511 unsigned NumCycles, unsigned ExtraPredCycles,

513 return true;

514 }

515

517 unsigned NumT, unsigned ExtraT,

519 unsigned NumF, unsigned ExtraF,

521

524 return true;

525 }

526

529 return false;

530 }

531

532

534

538

541

544

546 bool SkipDead) const override;

547

548

549

551 Register &SrcReg2, int64_t &Mask,

552 int64_t &Value) const override;

553

557

558

559

560

561

566

568

569

570

576

577

578

580 int64_t Offset1, bool OffsetIsScalable1,

582 int64_t Offset2, bool OffsetIsScalable2,

583 unsigned ClusterSize,

584 unsigned NumBytes) const override;

585

586

587

588 bool

591

592

593

594

596

598

599 std::pair<unsigned, unsigned>

601

604

605

607

608

610

613

615

616 std::pair<bool, bool>

619

620

624 }

625

626

630 }

633 unsigned BinOpDepth,

635

644 unsigned &XFormOpcode,

645 int64_t &OffsetOfImmInstr,

649 int64_t OffsetImm) const;

650

653 int64_t Imm) const;

654

656 bool PostRA) const;

657

658

659

661 bool &SeenIntermediateUse) const;

662

663

667 int64_t Imm) const;

668

669

670 bool isBDNZ(unsigned Opcode) const;

671

672

673

674

675

679

680

681

682 std::unique_ptrTargetInstrInfo::PipelinerLoopInfo

684};

685

686}

687

688#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

unsigned const TargetRegisterInfo * TRI

uint64_t IntrinsicInst * II

#define LoadOpcodesForSpill

#define StoreOpcodesForSpill

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallSet class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This is an important base class in LLVM.

Itinerary data supplied by a subtarget to be used by a target.

Instances of this class represent a single low-level machine instruction.

Wrapper class representing physical registers. Should be passed by value.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const

Return true when there is potentially a faster code sequence for a fma chain ending in Root.

bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const

bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const

bool isPredicated(const MachineInstr &MI) const override

bool expandVSXMemPseudo(MachineInstr &MI) const

bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const

int getExtendResourceLenLimit() const override

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

bool isPrefixed(unsigned Opcode) const

void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override

Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.

MCInst getNop() const override

Return the noop instruction to use for a noop.

static int getRecordFormOpcode(unsigned Opcode)

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Commutes the operands in the given instruction.

bool isXFormMemOp(unsigned Opcode) const

const PPCRegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

CombinerObjective getCombinerObjective(unsigned Pattern) const override

void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...

void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const

unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const

unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const

void promoteInstr32To64ForElimEXTSW(const Register &Reg, MachineRegisterInfo *MRI, unsigned BinOpDepth, LiveVariables *LV) const

bool isTOCSaveMI(const MachineInstr &MI) const

ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...

bool isSExt32To64(unsigned Opcode) const

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

bool isBDNZ(unsigned Opcode) const

Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).

std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const

bool expandPostRAPseudo(MachineInstr &MI) const override

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override

void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const

bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const

bool isZExt32To64(unsigned Opcode) const

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

Return true if two MIs access different memory addresses and false otherwise.

bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override

ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...

static bool isSameClassPhysRegCopy(unsigned Opcode)

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

Get the base operand and byte offset of an instruction that reads/writes memory.

void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const

bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const

bool useMachineCombiner() const override

void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const

bool foldFrameOffset(MachineInstr &MI) const

bool isLoadFromConstantPool(MachineInstr *I) const

MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const

Find the hardware loop instruction used to set-up the specified loop.

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override

bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override

bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override

bool convertToImmediateForm(MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override

bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const

Return true if get the base operand, byte offset of an instruction and the memory width.

bool isMemriOp(unsigned Opcode) const

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

static bool hasTLSFlag(unsigned TF)

bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override

On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...

bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const

void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Return the number of bytes of code the specified instruction may be.

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...

bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override

Returns true if the two given memory operations should be scheduled adjacent.

static bool hasPCRelFlag(unsigned TF)

void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const

bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...

bool optimizeCmpPostRA(MachineInstr &MI) const

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

const Constant * getConstantFromConstantPool(MachineInstr *I) const

bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override

static bool hasGOTFlag(unsigned TF)

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const

MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const

Wrapper class representing virtual and physical registers.

Represents one node in the SelectionDAG.

HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const

This is an architecture-specific helper function of reassociateOps.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

TargetSubtargetInfo - Generic base class for all target subtargets.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

@ ZExt32To64

This instruction produced a zero extended result.

@ SExt32To64

This instruction produced a sign extended result.

@ Prefixed

This instruction is prefixed.

@ MemriOp

This instruction takes a register+immediate memory operand.

@ XFormMemOp

This instruction is an X-Form memory operation.

@ MO_TPREL_PCREL_FLAG

MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TPREL_FLAG.

@ MO_GOT_TPREL_PCREL_FLAG

MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...

@ MO_GOT_PCREL_FLAG

MO_GOT_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG.

@ MO_TLSGDM_FLAG

MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative to the region handle of TLS Gene...

@ MO_PCREL_FLAG

MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to the current instruction addre...

@ MO_TLSLD_FLAG

MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to TLS Local Dynamic model.

@ MO_TLS_PCREL_FLAG

MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TLS.

@ MO_GOT_FLAG

MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.

@ MO_DTPREL_LO

These values identify relocations on immediates folded into memory operations.

@ MO_TLS

Symbol for VK_PPC_TLS fixup attached to an ADD instruction.

@ MO_TPREL_FLAG

MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to the thread pointer and the sy...

@ MO_GOT_TLSLD_PCREL_FLAG

MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...

@ MO_TLSGD_FLAG

MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to TLS General Dynamic model for ...

@ MO_GOT_TLSGD_PCREL_FLAG

MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

CombinerObjective

The combiner's goal may differ based on which pattern it is attempting to optimize.

PPCMachineCombinerPattern

uint64_t IsSummingOperands

uint64_t OpNoForForwarding

uint64_t ImmMustBeMultipleOf

uint64_t ZeroIsSpecialNew

uint64_t ZeroIsSpecialOrig