PPCInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H

14#define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H

23#define GET_INSTRINFO_HEADER

24#include "PPCGenInstrInfo.inc"

26namespace llvm {

57};

62 unsigned Imm : 16;

65};

103

104

105#define NoInstr PPC::INSTRUCTION_LIST_END

106#define Pwr8LoadOpcodes \

107 {PPC::LWZ, \

108 PPC::LD, \

109 PPC::LFD, \

110 PPC::LFS, \

111 PPC::RESTORE_CR, \

112 PPC::RESTORE_CRBIT, \

113 PPC::LVX, \

114 PPC::LXVD2X, \

115 PPC::LXSDX, \

116 PPC::LXSSPX, \

117 PPC::SPILLTOVSR_LD, \

118 NoInstr, \

119 NoInstr, \

120 NoInstr, \

121 NoInstr, \

122 NoInstr, \

123 NoInstr, \

124 PPC::EVLDD, \

125 PPC::RESTORE_QUADWORD}

126

127#define Pwr9LoadOpcodes \

128 {PPC::LWZ, \

129 PPC::LD, \

130 PPC::LFD, \

131 PPC::LFS, \

132 PPC::RESTORE_CR, \

133 PPC::RESTORE_CRBIT, \

134 PPC::LVX, \

135 PPC::LXV, \

136 PPC::DFLOADf64, \

137 PPC::DFLOADf32, \

138 PPC::SPILLTOVSR_LD, \

139 NoInstr, \

140 NoInstr, \

141 NoInstr, \

142 NoInstr, \

143 NoInstr, \

144 NoInstr, \

145 NoInstr, \

146 PPC::RESTORE_QUADWORD}

147

148#define Pwr10LoadOpcodes \

149 {PPC::LWZ, \

150 PPC::LD, \

151 PPC::LFD, \

152 PPC::LFS, \

153 PPC::RESTORE_CR, \

154 PPC::RESTORE_CRBIT, \

155 PPC::LVX, \

156 PPC::LXV, \

157 PPC::DFLOADf64, \

158 PPC::DFLOADf32, \

159 PPC::SPILLTOVSR_LD, \

160 PPC::LXVP, \

161 PPC::RESTORE_ACC, \

162 PPC::RESTORE_UACC, \

163 NoInstr, \

164 NoInstr, \

165 NoInstr, \

166 NoInstr, \

167 PPC::RESTORE_QUADWORD}

168

169#define FutureLoadOpcodes \

170 {PPC::LWZ, \

171 PPC::LD, \

172 PPC::LFD, \

173 PPC::LFS, \

174 PPC::RESTORE_CR, \

175 PPC::RESTORE_CRBIT, \

176 PPC::LVX, \

177 PPC::LXV, \

178 PPC::DFLOADf64, \

179 PPC::DFLOADf32, \

180 PPC::SPILLTOVSR_LD, \

181 PPC::LXVP, \

182 PPC::RESTORE_ACC, \

183 PPC::RESTORE_UACC, \

184 PPC::RESTORE_WACC, \

185 PPC::RESTORE_DMRP, \

186 PPC::RESTORE_DMR, \

187 NoInstr, \

188 PPC::RESTORE_QUADWORD}

189

190#define Pwr8StoreOpcodes \

191 {PPC::STW, \

192 PPC::STD, \

193 PPC::STFD, \

194 PPC::STFS, \

195 PPC::SPILL_CR, \

196 PPC::SPILL_CRBIT, \

197 PPC::STVX, \

198 PPC::STXVD2X, \

199 PPC::STXSDX, \

200 PPC::STXSSPX, \

201 PPC::SPILLTOVSR_ST, \

202 NoInstr, \

203 NoInstr, \

204 NoInstr, \

205 NoInstr, \

206 NoInstr, \

207 NoInstr, \

208 PPC::EVSTDD, \

209 PPC::SPILL_QUADWORD}

210

211#define Pwr9StoreOpcodes \

212 {PPC::STW, \

213 PPC::STD, \

214 PPC::STFD, \

215 PPC::STFS, \

216 PPC::SPILL_CR, \

217 PPC::SPILL_CRBIT, \

218 PPC::STVX, \

219 PPC::STXV, \

220 PPC::DFSTOREf64, \

221 PPC::DFSTOREf32, \

222 PPC::SPILLTOVSR_ST, \

223 NoInstr, \

224 NoInstr, \

225 NoInstr, \

226 NoInstr, \

227 NoInstr, \

228 NoInstr, \

229 NoInstr, \

230 PPC::SPILL_QUADWORD}

231

232#define Pwr10StoreOpcodes \

233 {PPC::STW, \

234 PPC::STD, \

235 PPC::STFD, \

236 PPC::STFS, \

237 PPC::SPILL_CR, \

238 PPC::SPILL_CRBIT, \

239 PPC::STVX, \

240 PPC::STXV, \

241 PPC::DFSTOREf64, \

242 PPC::DFSTOREf32, \

243 PPC::SPILLTOVSR_ST, \

244 PPC::STXVP, \

245 PPC::SPILL_ACC, \

246 PPC::SPILL_UACC, \

247 NoInstr, \

248 NoInstr, \

249 NoInstr, \

250 NoInstr, \

251 PPC::SPILL_QUADWORD}

252

253#define FutureStoreOpcodes \

254 {PPC::STW, \

255 PPC::STD, \

256 PPC::STFD, \

257 PPC::STFS, \

258 PPC::SPILL_CR, \

259 PPC::SPILL_CRBIT, \

260 PPC::STVX, \

261 PPC::STXV, \

262 PPC::DFSTOREf64, \

263 PPC::DFSTOREf32, \

264 PPC::SPILLTOVSR_ST, \

265 PPC::STXVP, \

266 PPC::SPILL_ACC, \

267 PPC::SPILL_UACC, \

268 PPC::SPILL_WACC, \

269 PPC::SPILL_DMRP, \

270 PPC::SPILL_DMR, \

271 NoInstr, \

272 PPC::SPILL_QUADWORD}

273

274

275#define StoreOpcodesForSpill \

276 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, FutureStoreOpcodes }

277#define LoadOpcodesForSpill \

278 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, FutureLoadOpcodes }

279

280class PPCSubtarget;

288

289 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,

293 unsigned DestReg, int FrameIdx,

296

297

298

300 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;

301

302

304 unsigned OpNoForForwarding) const;

305

306

308 unsigned ConstantOpNo,

310

311

314 bool KillDefMI) const;

315

316

317

318

319

321 unsigned &OpNoForForwarding,

322 bool &SeenIntermediateUse) const;

323

324

325

327 unsigned OpNoForForwarding) const;

332 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,

335 int64_t &Imm,

336 int64_t BaseImm = 0) const;

337 bool isRegElgibleForForwarding(const MachineOperand &RegMO,

340 bool &IsFwdFeederRegKilled,

341 bool &SeenIntermediateUse) const;

342 unsigned getSpillTarget() const;

346 int16_t getFMAOpIdxInfo(unsigned Opcode) const;

354 virtual void anchor();

355

356protected:

357

358

359

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361

362

363

364

365

366

368 unsigned OpIdx1,

369 unsigned OpIdx2) const override;

370

371public:

373

376

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382

398

400 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,

401 PPC::VOR, PPC::XXLOR, PPC::XXLORf,

402 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,

403 PPC::EVOR, -1U};

404 for (int i = 0; CopyOpcodes[i] != -1U; i++)

405 if (Opcode == CopyOpcodes[i])

406 return true;

407 return false;

408 }

409

417

424

435

442

445 unsigned *PredCost = nullptr) const override;

446

449 unsigned DefIdx,

451 unsigned UseIdx) const override;

453 SDNode *DefNode, unsigned DefIdx,

455 unsigned UseIdx) const override {

456 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,

457 UseNode, UseIdx);

458 }

459

462 unsigned DefIdx) const override {

463

464

465

466 return false;

467 }

468

472

473

474

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481

482

483

485 bool DoRegPressureReduce) const;

486

488

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490

491

494 bool DoRegPressureReduce) const override;

495

496

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498

499

503

504

505

506 void

509

511 bool Invert) const override;

512

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523

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527

530 unsigned &SubIdx) const override;

532 int &FrameIndex) const override;

535 int &FrameIndex) const override;

536

538 unsigned &SrcOpIdx2) const override;

539

542

543

544

548 bool AllowModify) const override;

550 int *BytesRemoved = nullptr) const override;

554 int *BytesAdded = nullptr) const override;

555

556

559 int &) const override;

563 Register FalseReg) const override;

564

567 bool KillSrc, bool RenamableDest = false,

568 bool RenamableSrc = false) const override;

569

573

576

577

578

579

582 unsigned SrcReg, bool isKill, int FrameIndex,

584

588

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592

593

594

597 unsigned DestReg, int FrameIndex,

599

601

603

604 bool

606

609

612

613

614

615

617 unsigned NumCycles, unsigned ExtraPredCycles,

619 return true;

620 }

621

623 unsigned NumT, unsigned ExtraT,

625 unsigned NumF, unsigned ExtraF,

627

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638

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644

647

650

652 bool SkipDead) const override;

653

654

655

657 Register &SrcReg2, int64_t &Mask,

658 int64_t &Value) const override;

659

663

664

665

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675

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682

683

684

686 int64_t Offset1, bool OffsetIsScalable1,

688 int64_t Offset2, bool OffsetIsScalable2,

689 unsigned ClusterSize,

690 unsigned NumBytes) const override;

691

692

693

694 bool

697

698

699

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702

704

705 std::pair<unsigned, unsigned>

707

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719

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722 std::pair<bool, bool>

725

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732

739 unsigned BinOpDepth,

741

750 unsigned &XFormOpcode,

751 int64_t &OffsetOfImmInstr,

755 int64_t OffsetImm) const;

756

759 int64_t Imm) const;

760

762 bool PostRA) const;

763

764

765

767 bool &SeenIntermediateUse) const;

768

769

773 int64_t Imm) const;

774

775

776 bool isBDNZ(unsigned Opcode) const;

777

778

779

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781

785

786

787

788 std::unique_ptrTargetInstrInfo::PipelinerLoopInfo

790};

791

792}

793

794#endif

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

uint64_t IntrinsicInst * II

#define LoadOpcodesForSpill

Definition PPCInstrInfo.h:277

#define StoreOpcodesForSpill

Definition PPCInstrInfo.h:275

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallSet class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This is an important base class in LLVM.

Itinerary data supplied by a subtarget to be used by a target.

Instances of this class represent a single low-level machine instruction.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const

Return true when there is potentially a faster code sequence for a fma chain ending in Root.

bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const

bool isReMaterializableImpl(const MachineInstr &MI) const override

PPCInstrInfo(const PPCSubtarget &STI)

const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const

bool isPredicated(const MachineInstr &MI) const override

bool expandVSXMemPseudo(MachineInstr &MI) const

bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const

int getExtendResourceLenLimit() const override

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

Definition PPCInstrInfo.h:521

bool isPrefixed(unsigned Opcode) const

Definition PPCInstrInfo.h:386

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override

Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.

MCInst getNop() const override

Return the noop instruction to use for a noop.

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

static int getRecordFormOpcode(unsigned Opcode)

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

Commutes the operands in the given instruction.

bool isXFormMemOp(unsigned Opcode) const

Definition PPCInstrInfo.h:383

const PPCRegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

Definition PPCInstrInfo.h:381

CombinerObjective getCombinerObjective(unsigned Pattern) const override

unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const

unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const

void promoteInstr32To64ForElimEXTSW(const Register &Reg, MachineRegisterInfo *MRI, unsigned BinOpDepth, LiveVariables *LV) const

bool isTOCSaveMI(const MachineInstr &MI) const

ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...

bool isSExt32To64(unsigned Opcode) const

Definition PPCInstrInfo.h:389

bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override

bool isBDNZ(unsigned Opcode) const

Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).

std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override

Definition PPCInstrInfo.h:452

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const

Definition PPCInstrInfo.h:733

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const

bool expandPostRAPseudo(MachineInstr &MI) const override

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

Definition PPCInstrInfo.h:616

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const

bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override

void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const

bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const

bool isZExt32To64(unsigned Opcode) const

Definition PPCInstrInfo.h:392

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

Return true if two MIs access different memory addresses and false otherwise.

bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override

ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...

static bool isSameClassPhysRegCopy(unsigned Opcode)

Definition PPCInstrInfo.h:399

bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override

bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

Get the base operand and byte offset of an instruction that reads/writes memory.

void setSpecialOperandAttr(MachineInstr &MI, uint32_t Flags) const

bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const

bool useMachineCombiner() const override

Definition PPCInstrInfo.h:469

void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool foldFrameOffset(MachineInstr &MI) const

bool isLoadFromConstantPool(MachineInstr *I) const

MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const

Find the hardware loop instruction used to set-up the specified loop.

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override

void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const

bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override

Definition PPCInstrInfo.h:633

bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override

bool convertToImmediateForm(MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override

bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override

Definition PPCInstrInfo.h:460

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

Definition PPCInstrInfo.h:628

bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const

Return true if get the base operand, byte offset of an instruction and the memory width.

bool isMemriOp(unsigned Opcode) const

Definition PPCInstrInfo.h:395

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

static bool hasTLSFlag(unsigned TF)

Definition PPCInstrInfo.h:425

bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override

On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...

void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...

bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const

Definition PPCInstrInfo.h:727

void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Return the number of bytes of code the specified instruction may be.

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...

bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override

Returns true if the two given memory operations should be scheduled adjacent.

static bool hasPCRelFlag(unsigned TF)

Definition PPCInstrInfo.h:410

void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const

bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...

bool optimizeCmpPostRA(MachineInstr &MI) const

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

const Constant * getConstantFromConstantPool(MachineInstr *I) const

bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override

static bool hasGOTFlag(unsigned TF)

Definition PPCInstrInfo.h:418

void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const

MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const

Wrapper class representing virtual and physical registers.

Represents one node in the SelectionDAG.

HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const

This is an architecture-specific helper function of reassociateOps.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

TargetSubtargetInfo - Generic base class for all target subtargets.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

@ ZExt32To64

This instruction produced a zero extended result.

@ SExt32To64

This instruction produced a sign extended result.

@ Prefixed

This instruction is prefixed.

@ MemriOp

This instruction takes a register+immediate memory operand.

@ XFormMemOp

This instruction is an X-Form memory operation.

@ MO_TPREL_PCREL_FLAG

MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TPREL_FLAG.

@ MO_GOT_TPREL_PCREL_FLAG

MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...

@ MO_GOT_PCREL_FLAG

MO_GOT_PCREL_FLAG = MO_PCREL_FLAG | MO_GOT_FLAG.

@ MO_TLSGDM_FLAG

MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative to the region handle of TLS Gene...

@ MO_PCREL_FLAG

MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to the current instruction addre...

@ MO_TLSLD_FLAG

MO_TLSLD_FLAG - If this bit is set the symbol reference is relative to TLS Local Dynamic model.

@ MO_TLS_PCREL_FLAG

MO_TPREL_PCREL_FLAG = MO_PCREL_FLAG | MO_TLS.

@ MO_GOT_FLAG

MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.

@ MO_DTPREL_LO

These values identify relocations on immediates folded into memory operations.

@ MO_TLS

Symbol for VK_TLS fixup attached to an ADD instruction.

@ MO_TPREL_FLAG

MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to the thread pointer and the sy...

@ MO_GOT_TLSLD_PCREL_FLAG

MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...

@ MO_TLSGD_FLAG

MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to TLS General Dynamic model for ...

@ MO_GOT_TLSGD_PCREL_FLAG

MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

CombinerObjective

The combiner's goal may differ based on which pattern it is attempting to optimize.

PPCMachineCombinerPattern

Definition PPCInstrInfo.h:92

@ REASSOC_XY_BCA

Definition PPCInstrInfo.h:99

@ REASSOC_XY_BAC

Definition PPCInstrInfo.h:100

@ REASSOC_XY_AMM_BMM

Definition PPCInstrInfo.h:94

@ REASSOC_XMM_AMM_BMM

Definition PPCInstrInfo.h:95

SpillOpcodeKey

Definition PPCInstrInfo.h:68

@ SOK_CRBitSpill

Definition PPCInstrInfo.h:74

@ SOK_VSXVectorSpill

Definition PPCInstrInfo.h:76

@ SOK_SpillToVSR

Definition PPCInstrInfo.h:79

@ SOK_Int4Spill

Definition PPCInstrInfo.h:69

@ SOK_PairedVecSpill

Definition PPCInstrInfo.h:80

@ SOK_VectorFloat8Spill

Definition PPCInstrInfo.h:77

@ SOK_UAccumulatorSpill

Definition PPCInstrInfo.h:82

@ SOK_PairedG8Spill

Definition PPCInstrInfo.h:87

@ SOK_DMRSpill

Definition PPCInstrInfo.h:85

@ SOK_VectorFloat4Spill

Definition PPCInstrInfo.h:78

@ SOK_Float8Spill

Definition PPCInstrInfo.h:71

@ SOK_Float4Spill

Definition PPCInstrInfo.h:72

@ SOK_VRVectorSpill

Definition PPCInstrInfo.h:75

@ SOK_WAccumulatorSpill

Definition PPCInstrInfo.h:83

@ SOK_SPESpill

Definition PPCInstrInfo.h:86

@ SOK_CRSpill

Definition PPCInstrInfo.h:73

@ SOK_AccumulatorSpill

Definition PPCInstrInfo.h:81

@ SOK_Int8Spill

Definition PPCInstrInfo.h:70

@ SOK_LastOpcodeSpill

Definition PPCInstrInfo.h:88

@ SOK_DMRpSpill

Definition PPCInstrInfo.h:84

Definition PPCInstrInfo.h:32

uint64_t SignedImm

Definition PPCInstrInfo.h:34

uint64_t IsSummingOperands

Definition PPCInstrInfo.h:56

uint64_t ImmOpcode

Definition PPCInstrInfo.h:50

uint64_t ImmOpNo

Definition PPCInstrInfo.h:48

uint64_t OpNoForForwarding

Definition PPCInstrInfo.h:46

uint64_t ImmMustBeMultipleOf

Definition PPCInstrInfo.h:36

uint64_t IsCommutative

Definition PPCInstrInfo.h:44

uint64_t ImmWidth

Definition PPCInstrInfo.h:52

uint64_t ZeroIsSpecialNew

Definition PPCInstrInfo.h:42

uint64_t TruncateImmTo

Definition PPCInstrInfo.h:54

uint64_t ZeroIsSpecialOrig

Definition PPCInstrInfo.h:39