LLVM: llvm::PPCInstrInfo Class Reference (original) (raw)

#include "[Target/PowerPC/PPCInstrInfo.h](PPCInstrInfo%5F8h%5Fsource.html)"

Public Member Functions
PPCInstrInfo (const PPCSubtarget &STI)
bool isLoadFromConstantPool (MachineInstr *I) const
const Constant * getConstantFromConstantPool (MachineInstr *I) const
const PPCRegisterInfo & getRegisterInfo () const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isXFormMemOp (unsigned Opcode) const
bool isPrefixed (unsigned Opcode) const
bool isSExt32To64 (unsigned Opcode) const
bool isZExt32To64 (unsigned Opcode) const
bool isMemriOp (unsigned Opcode) const
ScheduleHazardRecognizer * CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
std::optional< unsigned > getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
std::optional< unsigned > getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
bool hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
bool useMachineCombiner () const override
void genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
bool getFMAPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
CombinerObjective getCombinerObjective (unsigned Pattern) const override
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in .
bool shouldReduceRegisterPressure (const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.
void finalizeInsInstrs (MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
bool isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
int getExtendResourceLenLimit () const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
void setSpecialOperandAttr (MachineInstr &MI, uint32_t Flags) const
bool isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool isReMaterializableImpl (const MachineInstr &MI) const override
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void storeRegToStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void loadRegFromStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC) const
unsigned getStoreOpcodeForSpill (const TargetRegisterClass *RC) const
unsigned getLoadOpcodeForSpill (const TargetRegisterClass *RC) const
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool onlyFoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool isPredicated (const MachineInstr &MI) const override
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
bool getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
bool optimizeCmpPostRA (MachineInstr &MI) const
bool getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
MCInst getNop () const override
Return the noop instruction to use for a noop.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
bool expandVSXMemPseudo (MachineInstr &MI) const
bool expandPostRAPseudo (MachineInstr &MI) const override
const TargetRegisterClass * updatedRC (const TargetRegisterClass *RC) const
bool isTOCSaveMI (const MachineInstr &MI) const
std::pair< bool, bool > isSignOrZeroExtended (const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
bool isSignExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
bool isZeroExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
void promoteInstr32To64ForElimEXTSW (const Register &Reg, MachineRegisterInfo *MRI, unsigned BinOpDepth, LiveVariables *LV) const
bool convertToImmediateForm (MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const
bool foldFrameOffset (MachineInstr &MI) const
bool combineRLWINM (MachineInstr &MI, MachineInstr **ToErase=nullptr) const
bool isADDIInstrEligibleForFolding (MachineInstr &ADDIMI, int64_t &Imm) const
bool isADDInstrEligibleForFolding (MachineInstr &ADDMI) const
bool isImmInstrEligibleForFolding (MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
bool isValidToBeChangedReg (MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
void replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
void replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
bool instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
MachineInstr * getDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
void materializeImmPostRA (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
bool isBDNZ (unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
MachineInstr * findLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
virtual void setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Static Public Member Functions
static bool isSameClassPhysRegCopy (unsigned Opcode)
static bool hasPCRelFlag (unsigned TF)
static bool hasGOTFlag (unsigned TF)
static bool hasTLSFlag (unsigned TF)
static int getRecordFormOpcode (unsigned Opcode)

Definition at line 281 of file PPCInstrInfo.h.

◆ analyzeBranch()

Definition at line 1259 of file PPCInstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DisableCTRLoopAnal, llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineOperand::isMBB(), MBB, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and TBB.

◆ analyzeCompare()

◆ analyzeLoopForPipelining()

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 5768 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, isBDNZ(), MRI, and llvm::MachineBasicBlock::pred_begin().

◆ areMemAccessesTriviallyDisjoint()

Return true if two MIs access different memory addresses and false otherwise.

Definition at line 5826 of file PPCInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::LocationSize::getValue(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::LocationSize::hasValue(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), llvm::LocationSize::precise(), and TRI.

◆ canInsertSelect()

◆ ClobbersPredicate()

◆ combineRLWINM()

Definition at line 3861 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::get(), llvm::APInt::getBitsSetWithWrap(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::APInt::getZExtValue(), llvm::MachineInstr::hasImplicitDef(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::isRunOfOnes(), llvm::Register::isVirtual(), llvm::APInt::isZero(), LLVM_DEBUG, MI, MRI, llvm::APInt::rotl(), and llvm::MachineOperand::setIsKill().

◆ commuteInstructionImpl()

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 1130 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::getKillRegState(), MI, and llvm::MCOI::TIED_TO.

◆ convertToImmediateForm()

Definition at line 3799 of file PPCInstrInfo.cpp.

References assert(), DefMI, llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SmallSet< T, N, C >::insert(), instrHasImmForm(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::PPC::isVFRegister(), MI, and MRI.

◆ copyPhysReg()

Definition at line 1677 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::RegState::Define, DL, llvm::PPCRegisterInfo::emitAccCopyInfo(), llvm::get(), getCRBitValue(), llvm::getCRFromCRBit(), llvm::getKillRegState(), getRegisterInfo(), I, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::RegState::Kill, llvm_unreachable, MBB, Opc, TRI, and VSXSelfCopyCrash.

◆ CreateTargetHazardRecognizer()

◆ CreateTargetPostRAHazardRecognizer()

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 117 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), II, llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

◆ decomposeMachineOperandsTargetFlags()

◆ expandPostRAPseudo()

Definition at line 3134 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, expandPostRAPseudo(), expandVSXMemPseudo(), llvm::get(), isAnImmediateOperand(), MBB, MI, llvm::Offset, and llvm::PPC::PRED_NE_MINUS.

Referenced by expandPostRAPseudo().

◆ expandVSXMemPseudo()

◆ finalizeInsInstrs()

Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.

Definition at line 525 of file PPCInstrInfo.cpp.

References assert(), llvm::CallingConv::C, llvm::APFloat::changeSign(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), FMAOpIdxInfo, getConstantFromConstantPool(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::DataLayout::getPrefTypeAlign(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), InfoArrayIdxMULOpIdx, llvm::isa(), MRI, llvm::REASSOC_XY_BAC, llvm::REASSOC_XY_BCA, and TRI.

◆ findCommutedOpIndices()

◆ findLoopInstr()

◆ foldFrameOffset()

Definition at line 3590 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::MachineInstr::eraseFromParent(), llvm::get(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::ImmInstrInfo::ImmOpNo, isADDInstrEligibleForFolding(), isImmInstrEligibleForFolding(), llvm::MachineOperand::isKill(), isValidToBeChangedReg(), LLVM_DEBUG, MI, MRI, llvm::ImmInstrInfo::OpNoForForwarding, llvm::MachineOperand::setImm(), and llvm::ImmInstrInfo::ZeroIsSpecialOrig.

◆ foldImmediate()

◆ genAlternativeCodeSequence()

◆ getCombinerObjective()

◆ getConstantFromConstantPool()

◆ getDefMIPostRA()

◆ getExtendResourceLenLimit()

int llvm::PPCInstrInfo::getExtendResourceLenLimit ( ) const inlineoverride

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

Set extension resource length limit to 1 for edge case. Resource Length is calculated by scaled resource usage in getCycles(). Because of the division in getCycles(), it returns different cycles due to legacy scaled resource usage. So new resource length may be same with legacy or 1 bigger than legacy. We need to execlude the 1 bigger case even the resource length is not perserved for more FMA chain reassociations on PowerPC.

Definition at line 521 of file PPCInstrInfo.h.

◆ getFMAPatterns()

Return true when there is potentially a faster code sequence for a fma chain ending in Root.

All potential patterns are output in the P array.

Definition at line 350 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), FMAOpIdxInfo, llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), InfoArrayIdxAddOpIdx, InfoArrayIdxFAddInst, InfoArrayIdxFSubInst, InfoArrayIdxMULOpIdx, isLoadFromConstantPool(), llvm::Register::isVirtual(), LLVM_DEBUG, MBB, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, llvm::REASSOC_XY_BCA, and TRI.

Referenced by getMachineCombinerPatterns().

◆ getInstrLatency()

◆ getInstSizeInBytes()

◆ getLoadOpcodeForSpill()

◆ getMachineCombinerPatterns()

◆ getMemOperandsWithOffsetWidth()

◆ getMemOperandWithOffsetWidth()

Return true if get the base operand, byte offset of an instruction and the memory width.

Width is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8).

Definition at line 5803 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::memoperands_begin(), llvm::Offset, and TRI.

Referenced by areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), and shouldClusterMemOps().

◆ getNop()

MCInst PPCInstrInfo::getNop ( ) const override

◆ getOperandLatency() [1/2]

Definition at line 167 of file PPCInstrInfo.cpp.

References DefMI, llvm::PPC::DIR_7400, llvm::PPC::DIR_750, llvm::PPC::DIR_970, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR4, llvm::PPC::DIR_PWR5, llvm::PPC::DIR_PWR5X, llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR6X, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, getInstrLatency(), llvm::MachineOperand::getReg(), llvm::Latency, MRI, and UseMI.

◆ getOperandLatency() [2/2]

◆ getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned Opcode) static

◆ getRegisterInfo()

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 381 of file PPCInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), finalizeInsInstrs(), foldFrameOffset(), getDefMIPostRA(), getFMAPatterns(), llvm::PPCSubtarget::getRegisterInfo(), optimizeCompareInstr(), replaceInstrOperandWithImm(), shouldClusterMemOps(), and shouldReduceRegisterPressure().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const override

◆ getStoreOpcodeForSpill()

◆ hasGOTFlag()

bool llvm::PPCInstrInfo::hasGOTFlag ( unsigned TF) inlinestatic

◆ hasLowDefLatency()

◆ hasPCRelFlag()

bool llvm::PPCInstrInfo::hasPCRelFlag ( unsigned TF) inlinestatic

◆ hasTLSFlag()

bool llvm::PPCInstrInfo::hasTLSFlag ( unsigned TF) inlinestatic

Definition at line 425 of file PPCInstrInfo.h.

References llvm::PPCII::MO_DTPREL_LO, llvm::PPCII::MO_GOT_TLSGD_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSLD_PCREL_FLAG, llvm::PPCII::MO_GOT_TPREL_PCREL_FLAG, llvm::PPCII::MO_TLS, llvm::PPCII::MO_TLS_PCREL_FLAG, llvm::PPCII::MO_TLSGD_FLAG, llvm::PPCII::MO_TLSGDM_FLAG, llvm::PPCII::MO_TLSLD_FLAG, llvm::PPCII::MO_TLSLD_LO, llvm::PPCII::MO_TPREL_FLAG, llvm::PPCII::MO_TPREL_HA, llvm::PPCII::MO_TPREL_LO, and llvm::PPCII::MO_TPREL_PCREL_FLAG.

Referenced by getTOCEntryTypeForMO().

◆ insertBranch()

Definition at line 1466 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::getImm(), getReg(), MBB, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and TBB.

◆ insertNoop()

◆ insertSelect()

Definition at line 1565 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, llvm::get(), getReg(), MBB, MI, MRI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, llvm::PPC::PRED_EQ, llvm::PPC::PRED_EQ_MINUS, llvm::PPC::PRED_EQ_PLUS, llvm::PPC::PRED_GE, llvm::PPC::PRED_GE_MINUS, llvm::PPC::PRED_GE_PLUS, llvm::PPC::PRED_GT, llvm::PPC::PRED_GT_MINUS, llvm::PPC::PRED_GT_PLUS, llvm::PPC::PRED_LE, llvm::PPC::PRED_LE_MINUS, llvm::PPC::PRED_LE_PLUS, llvm::PPC::PRED_LT, llvm::PPC::PRED_LT_MINUS, llvm::PPC::PRED_LT_PLUS, llvm::PPC::PRED_NE, llvm::PPC::PRED_NE_MINUS, llvm::PPC::PRED_NE_PLUS, llvm::PPC::PRED_NU, llvm::PPC::PRED_NU_MINUS, llvm::PPC::PRED_NU_PLUS, llvm::PPC::PRED_UN, llvm::PPC::PRED_UN_MINUS, and llvm::PPC::PRED_UN_PLUS.

◆ instrHasImmForm()

Definition at line 3998 of file PPCInstrInfo.cpp.

References llvm::ImmInstrInfo::ImmMustBeMultipleOf, llvm::ImmInstrInfo::ImmOpcode, llvm::ImmInstrInfo::ImmOpNo, llvm::ImmInstrInfo::ImmWidth, llvm::ImmInstrInfo::IsCommutative, llvm::ImmInstrInfo::IsSummingOperands, llvm_unreachable, Opc, llvm::ImmInstrInfo::OpNoForForwarding, llvm::ImmInstrInfo::SignedImm, llvm::ImmInstrInfo::TruncateImmTo, llvm::ImmInstrInfo::ZeroIsSpecialNew, and llvm::ImmInstrInfo::ZeroIsSpecialOrig.

Referenced by convertToImmediateForm(), and isImmInstrEligibleForFolding().

◆ isADDIInstrEligibleForFolding()

bool PPCInstrInfo::isADDIInstrEligibleForFolding ( MachineInstr & ADDIMI,
int64_t & Imm ) const

◆ isADDInstrEligibleForFolding()

◆ isAssociativeAndCommutative()

◆ isBDNZ()

◆ isCoalescableExtInstr()

◆ isImmInstrEligibleForFolding()

Definition at line 3711 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::ImmInstrInfo::ImmOpNo, instrHasImmForm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::ImmInstrInfo::IsSummingOperands, llvm::PPC::isVFRegister(), MI, Opc, and llvm::ImmInstrInfo::OpNoForForwarding.

Referenced by foldFrameOffset().

◆ isLoadFromConstantPool()

◆ isLoadFromStackSlot()

◆ isMemriOp()

bool llvm::PPCInstrInfo::isMemriOp ( unsigned Opcode) const inline

◆ isPredicated()

◆ isPrefixed()

bool llvm::PPCInstrInfo::isPrefixed ( unsigned Opcode) const inline

◆ isProfitableToDupForIfCvt()

◆ isProfitableToIfCvt() [1/2]

◆ isProfitableToIfCvt() [2/2]

◆ isProfitableToUnpredicate()

◆ isReMaterializableImpl()

◆ isSameClassPhysRegCopy()

bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned Opcode) inlinestatic

◆ isSchedulingBoundary()

◆ isSExt32To64()

bool llvm::PPCInstrInfo::isSExt32To64 ( unsigned Opcode) const inline

◆ isSignExtended()

◆ isSignOrZeroExtended()

Definition at line 5522 of file PPCInstrInfo.cpp.

References definedBySignExtendingOp(), definedByZeroExtendingOp(), llvm::dyn_cast(), llvm::dyn_cast_if_present(), llvm::Function::getAttributes(), llvm::Function::getEntryBlock(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getRegInfo(), llvm::Function::getReturnType(), llvm::MachineFunction::getSubtarget(), I, II, llvm::MachineInstr::isCall(), llvm::MachineOperand::isGlobal(), llvm::MachineRegisterInfo::isLiveIn(), llvm::PPCFunctionInfo::isLiveInSExt(), llvm::PPCFunctionInfo::isLiveInZExt(), isSignOrZeroExtended(), llvm::PPCSubtarget::isSVR4ABI(), llvm::Register::isVirtualRegister(), MAX_BINOP_DEPTH, MBB, MI, and MRI.

Referenced by isSignExtended(), isSignOrZeroExtended(), and isZeroExtended().

◆ isStoreToStackSlot()

◆ isTOCSaveMI()

◆ isValidToBeChangedReg()

◆ isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned Opcode) const inline

◆ isZeroExtended()

◆ isZExt32To64()

bool llvm::PPCInstrInfo::isZExt32To64 ( unsigned Opcode) const inline

◆ loadRegFromStackSlot()

◆ loadRegFromStackSlotNoUpd()

Definition at line 2059 of file PPCInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::back(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), MBB, MI, and llvm::MachineMemOperand::MOLoad.

Referenced by loadRegFromStackSlot().

◆ materializeImmPostRA()

◆ onlyFoldImmediate()

◆ optimizeCmpPostRA()

Definition at line 2817 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), analyzeCompare(), assert(), llvm::MachineInstr::clearRegisterDeads(), llvm::dbgs(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::dump(), llvm::get(), getDefMIPostRA(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasImplicitDef(), llvm::RegState::ImplicitDefine, LLVM_DEBUG, MRI, Opc, and llvm::MachineInstr::setDesc().

◆ optimizeCompareInstr()

Definition at line 2432 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), B(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DisableCmpOpt, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::PPC::getSwappedPredicate(), I, llvm::MCInstrDesc::implicit_defs(), llvm::MCInstrDesc::implicit_uses(), isSignExtended(), llvm::Register::isVirtual(), isZeroExtended(), llvm::RegState::Kill, MI, MRI, llvm::MachineInstr::NoSWrap, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineOperand::setImm(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Sub, TRI, and UseMI.

◆ PredicateInstruction()

Definition at line 2232 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::get(), llvm::getImm(), getReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm_unreachable, MBB, MI, llvm::PPC::PRED_BIT_SET, and llvm::PPC::PRED_BIT_UNSET.

◆ promoteInstr32To64ForElimEXTSW()

Definition at line 5318 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineOperand::isReg(), llvm::PPCSubtarget::isSVR4ABI(), llvm::Register::isVirtual(), llvm::RegState::Kill, MAX_BINOP_DEPTH, MBB, MI, MRI, PPCInstrInfo(), promoteInstr32To64ForElimEXTSW(), llvm::LiveVariables::recomputeForSingleDefVirtReg(), TII, and TRI.

Referenced by promoteInstr32To64ForElimEXTSW().

◆ removeBranch()

◆ replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm ( MachineInstr & MI,
unsigned OpNo,
int64_t Imm ) const

◆ replaceInstrWithLI()

◆ reverseBranchCondition()

◆ setSpecialOperandAttr() [1/2]

◆ setSpecialOperandAttr() [2/2]

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 1429 of file TargetInstrInfo.h.

◆ shouldClusterMemOps()

Returns true if the two given memory operations should be scheduled adjacent.

Definition at line 2943 of file PPCInstrInfo.cpp.

References assert(), llvm::ArrayRef< T >::front(), llvm::MachineOperand::getIndex(), getMemOperandWithOffsetWidth(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::LocationSize::getValue(), isClusterableLdStOpcPair(), llvm::MachineOperand::isFI(), isLdStSafeToCluster(), llvm::MachineOperand::isReg(), llvm::LocationSize::precise(), llvm::ArrayRef< T >::size(), and TRI.

◆ shouldReduceRegisterPressure()

On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.

Return true if register pressure for MBB is high and ABI is supported to reduce register pressure. Otherwise return false.

Definition at line 595 of file PPCInstrInfo.cpp.

References assert(), llvm::RegPressureTracker::closeRegion(), llvm::RegisterOperands::collect(), EnableFMARegPressureReduction, FMARPFactor, llvm::RegPressureTracker::getPos(), llvm::RegPressureTracker::getPressure(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::RegisterClassInfo::getRegPressureSetLimit(), llvm::RegPressureTracker::init(), llvm::RegisterPressure::MaxSetPressure, MBB, llvm::CodeModel::Medium, MI, MRI, llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), llvm::reverse(), and TRI.

◆ storeRegToStackSlot()

◆ storeRegToStackSlotNoUpd()

◆ SubsumesPredicate()

◆ updatedRC()

◆ useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const inlineoverride

The documentation for this class was generated from the following files: