PPCMCTargetDesc.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H

14#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H

17#undef PPC

21#include

22#include

24namespace llvm {

37namespace PPC {

51 unsigned OpNo);

53}

64 uint8_t OSABI);

66std::unique_ptr

76static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {

77 if (!Val)

78 return false;

85 return true;

86 } else {

87 Val = ~Val;

93 return true;

94 }

95 }

97 return false;

98}

101 if (!Val)

102 return false;

103

105

107

109 return true;

110 } else {

111 Val = ~Val;

113

115

117 return true;

118 }

119 }

120

121 return false;

122}

123

124

125

126

128enum {

129

130

131

132

133

134

136

137

138

140

141

142

144

145

146

149};

162

163enum {

164

166

167

169

171

173

175

177};

178}

179

180}

181

182

183

184

185#define GET_REGINFO_ENUM

186#include "PPCGenRegisterInfo.inc"

187

188

189

190#define GET_INSTRINFO_ENUM

191#define GET_INSTRINFO_SCHED_ENUM

192#define GET_INSTRINFO_MC_HELPER_DECLS

193#include "PPCGenInstrInfo.inc"

194

195#define GET_SUBTARGETINFO_ENUM

196#include "PPCGenSubtargetInfo.inc"

197

198#define PPC_REGS0_7(X) \

199 { \

200 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \

201 }

202

203#define PPC_REGS0_31(X) \

204 { \

205 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \

206 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \

207 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \

208 }

209

210#define PPC_REGS_EVEN0_30(X) \

211 { \

212 X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, X##18, X##20, \

213 X##22, X##24, X##26, X##28, X##30 \

214 }

215

216#define PPC_REGS0_63(X) \

217 { \

218 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \

219 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \

220 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \

221 X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \

222 X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \

223 X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \

224 X##62, X##63 \

225 }

226

227#define PPC_REGS_NO0_31(Z, X) \

228 { \

229 Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \

230 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \

231 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \

232 }

233

234#define PPC_REGS_LO_HI(LO, HI) \

235 { \

236 LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \

237 LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \

238 LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \

239 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \

240 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \

241 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \

242 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \

243 HI##28, HI##29, HI##30, HI##31 \

244 }

245

246#define PPC_REGS0_7(X) \

247 { \

248 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \

249 }

250

251#define PPC_REGS0_3(X) \

252 { \

253 X##0, X##1, X##2, X##3 \

254 }

255

257

258#define DEFINE_PPC_REGCLASSES \

259 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \

260 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \

261 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \

262 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \

263 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \

264 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \

265 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \

266 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \

267 static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \

268 static const MCPhysReg XRegsNoX0[32] = PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \

269 static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC::VSL, PPC::V); \

270 static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \

271 static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \

272 static const MCPhysReg CRBITRegs[32] = { \

273 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, \

274 PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \

275 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, \

276 PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \

277 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, \

278 PPC::CR7EQ, PPC::CR7UN}; \

279 static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \

280 static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \

281 static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \

282 static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \

283 static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \

284 static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \

285 static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \

286 static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);

287

288namespace llvm {

289namespace PPC {

291 return Reg >= PPC::VF0 && Reg <= PPC::VF31;

292}

293

295 return Reg >= PPC::V0 && Reg <= PPC::V31;

296}

297

299 return Reg >= PPC::DMRROWp0 && Reg <= PPC::DMRROWp31;

300}

301}

302}

303

304#endif

unsigned const MachineRegisterInfo * MRI

Generic interface to target specific assembler backends.

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

Describe properties that are true of each instruction in the target description file.

Interface to description of machine instruction set.

Base class for classes that define behaviour that is specific to both the target and the object forma...

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

Target - Wrapper for Target specific information.

PPCII - This namespace holds all of the PowerPC target-specific per-instruction flags.

Definition PPCMCTargetDesc.h:127

@ ZExt32To64

This instruction produced a zero extended result.

Definition PPCMCTargetDesc.h:174

@ NewDef_Shift

Shift count to bypass PPC970 flags.

Definition PPCMCTargetDesc.h:165

@ SExt32To64

This instruction produced a sign extended result.

Definition PPCMCTargetDesc.h:172

@ Prefixed

This instruction is prefixed.

Definition PPCMCTargetDesc.h:170

@ MemriOp

This instruction takes a register+immediate memory operand.

Definition PPCMCTargetDesc.h:176

@ XFormMemOp

This instruction is an X-Form memory operation.

Definition PPCMCTargetDesc.h:168

PPC970_Unit

Definition PPCMCTargetDesc.h:150

@ PPC970_LSU

Definition PPCMCTargetDesc.h:155

@ PPC970_VALU

Definition PPCMCTargetDesc.h:158

@ PPC970_VPERM

Definition PPCMCTargetDesc.h:159

@ PPC970_FPU

Definition PPCMCTargetDesc.h:156

@ PPC970_FXU

Definition PPCMCTargetDesc.h:154

@ PPC970_Pseudo

These are the various PPC970 execution unit pipelines.

Definition PPCMCTargetDesc.h:153

@ PPC970_BRU

Definition PPCMCTargetDesc.h:160

@ PPC970_CRU

Definition PPCMCTargetDesc.h:157

@ PPC970_Mask

Definition PPCMCTargetDesc.h:148

@ PPC970_First

PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...

Definition PPCMCTargetDesc.h:135

@ PPC970_Cracked

PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...

Definition PPCMCTargetDesc.h:143

@ PPC970_Shift

PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...

Definition PPCMCTargetDesc.h:147

@ PPC970_Single

PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...

Definition PPCMCTargetDesc.h:139

Define some predicates that are used for node matching.

static bool isDMRROWpRegister(unsigned Reg)

Definition PPCMCTargetDesc.h:298

const char * stripRegisterPrefix(const char *RegName)

stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...

MCRegister getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg, unsigned OpNo)

getRegNumForOperand - some operands use different numbering schemes for the same registers.

static bool isVRRegister(MCRegister Reg)

Definition PPCMCTargetDesc.h:294

static bool isVFRegister(MCRegister Reg)

Definition PPCMCTargetDesc.h:290

This is an optimization pass for GlobalISel generic memory operations.

std::unique_ptr< MCObjectTargetWriter > createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)

Construct a PPC Mach-O object writer.

MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

static bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME)

Definition PPCMCTargetDesc.h:100

constexpr bool isShiftedMask_32(uint32_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...

constexpr bool isShiftedMask_64(uint64_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...

int countl_zero(T Val)

Count number of 0's from the most significant bit to the least stopping at the first 1.

std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)

Construct a PPC XCOFF object writer.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)

Construct an PPC ELF object writer.

static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)

Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side.

Definition PPCMCTargetDesc.h:76