PPCTargetTransformInfo.cpp Source File (original) (raw)

16#include "llvm/IR/IntrinsicsPowerPC.h"

21#include

23using namespace llvm;

25#define DEBUG_TYPE "ppctti"

28 cl::desc("Allow vp.load and vp.store for pwr9"),

39 cl::desc("Enable using coldcc calling conv for cold "

40 "internal functions"));

44 cl::desc("Do not add instruction count to lsr cost model"));

50 cl::desc("Loops with a constant trip count smaller than "

51 "this value will not use the count register."));

68std::optional<Instruction *>

71 switch (IID) {

72 default:

73 break;

74 case Intrinsic::ppc_altivec_lvx:

75 case Intrinsic::ppc_altivec_lvxl:

80 Value *Ptr = II.getArgOperand(0);

81 return new LoadInst(II.getType(), Ptr, "", false, Align(16));

82 }

83 break;

84 case Intrinsic::ppc_vsx_lxvw4x:

85 case Intrinsic::ppc_vsx_lxvd2x: {

87 Value *Ptr = II.getArgOperand(0);

89 }

90 case Intrinsic::ppc_altivec_stvx:

91 case Intrinsic::ppc_altivec_stvxl:

96 Value *Ptr = II.getArgOperand(1);

97 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(16));

98 }

99 break;

100 case Intrinsic::ppc_vsx_stxvw4x:

101 case Intrinsic::ppc_vsx_stxvd2x: {

102

103 Value *Ptr = II.getArgOperand(1);

104 return new StoreInst(II.getArgOperand(0), Ptr, false, Align(1));

105 }

106 case Intrinsic::ppc_altivec_vperm:

107

108

109

110

111

112

115 "Bad type for intrinsic!");

116

117

118 bool AllEltsOk = true;

119 for (unsigned I = 0; I != 16; ++I) {

120 Constant *Elt = Mask->getAggregateElement(I);

122 AllEltsOk = false;

123 break;

124 }

125 }

126

127 if (AllEltsOk) {

128

134

135

136 Value *ExtractedElts[32];

137 memset(ExtractedElts, 0, sizeof(ExtractedElts));

138

139 for (unsigned I = 0; I != 16; ++I) {

141 continue;

142 unsigned Idx =

144 Idx &= 31;

145 if (DL.isLittleEndian())

146 Idx = 31 - Idx;

147

148 if (!ExtractedElts[Idx]) {

149 Value *Op0ToUse = (DL.isLittleEndian()) ? Op1 : Op0;

150 Value *Op1ToUse = (DL.isLittleEndian()) ? Op0 : Op1;

152 Idx < 16 ? Op0ToUse : Op1ToUse, IC.Builder.getInt32(Idx & 15));

153 }

154

155

158 }

160 }

161 }

162 break;

163 }

164 return std::nullopt;

165}

166

171

172 assert(Ty->isIntegerTy());

173

174 unsigned BitSize = Ty->getPrimitiveSizeInBits();

175 if (BitSize == 0)

176 return ~0U;

177

178 if (Imm == 0)

180

181 if (Imm.getBitWidth() <= 64) {

182 if (isInt<16>(Imm.getSExtValue()))

184

185 if (isInt<32>(Imm.getSExtValue())) {

186

187 if ((Imm.getZExtValue() & 0xFFFF) == 0)

189

191 }

192 }

193

195}

196

203

204 assert(Ty->isIntegerTy());

205

206 unsigned BitSize = Ty->getPrimitiveSizeInBits();

207 if (BitSize == 0)

208 return ~0U;

209

210 switch (IID) {

211 default:

213 case Intrinsic::sadd_with_overflow:

214 case Intrinsic::uadd_with_overflow:

215 case Intrinsic::ssub_with_overflow:

216 case Intrinsic::usub_with_overflow:

217 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))

219 break;

220 case Intrinsic::experimental_stackmap:

221 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))

223 break;

224 case Intrinsic::experimental_patchpoint_void:

225 case Intrinsic::experimental_patchpoint:

226 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))

228 break;

229 }

231}

232

239

240 assert(Ty->isIntegerTy());

241

242 unsigned BitSize = Ty->getPrimitiveSizeInBits();

243 if (BitSize == 0)

244 return ~0U;

245

246 unsigned ImmIdx = ~0U;

247 bool ShiftedFree = false, RunFree = false, UnsignedFree = false,

248 ZeroFree = false;

249 switch (Opcode) {

250 default:

252 case Instruction::GetElementPtr:

253

254

255

256 if (Idx == 0)

259 case Instruction::And:

260 RunFree = true;

261 [[fallthrough]];

262 case Instruction::Add:

263 case Instruction::Or:

264 case Instruction::Xor:

265 ShiftedFree = true;

266 [[fallthrough]];

267 case Instruction::Sub:

268 case Instruction::Mul:

269 case Instruction::Shl:

270 case Instruction::LShr:

271 case Instruction::AShr:

272 ImmIdx = 1;

273 break;

274 case Instruction::ICmp:

275 UnsignedFree = true;

276 ImmIdx = 1;

277

278 [[fallthrough]];

279 case Instruction::Select:

280 ZeroFree = true;

281 break;

282 case Instruction::PHI:

283 case Instruction::Call:

284 case Instruction::Ret:

285 case Instruction::Load:

286 case Instruction::Store:

287 break;

288 }

289

290 if (ZeroFree && Imm == 0)

292

293 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {

294 if (isInt<16>(Imm.getSExtValue()))

296

297 if (RunFree) {

298 if (Imm.getBitWidth() <= 32 &&

302

303 if (ST->isPPC64() &&

307 }

308

309 if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))

311

312 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)

314 }

315

317}

318

319

320

322 return Ty->isVectorTy() && (Ty->getScalarSizeInBits() == 1) &&

323 (Ty->getPrimitiveSizeInBits() > 128);

324}

325

329

330

333

334 if (U->getType()->isVectorTy()) {

335

338 }

339

341}

342

349 SchedModel.init(ST);

350

351

354

355

362 Metrics.analyzeBasicBlock(BB, TTI, EphValues);

363

365 return false;

366 }

367

368

369 for (auto *BB : L->getBlocks())

370 for (auto &I : *BB)

372 if (Call->getIntrinsicID() == Intrinsic::set_loop_iterations ||

373 Call->getIntrinsicID() == Intrinsic::loop_decrement)

374 return false;

375

377 L->getExitingBlocks(ExitingBlocks);

378

379

380

381 for (auto &BB : ExitingBlocks) {

383 if (!TI) continue;

384

386 uint64_t TrueWeight = 0, FalseWeight = 0;

387 if (!BI->isConditional() ||

389 continue;

390

391

392

393 bool TrueIsExit = !L->contains(BI->getSuccessor(0));

394 if (( TrueIsExit && FalseWeight < TrueWeight) ||

395 (!TrueIsExit && FalseWeight > TrueWeight))

396 return false;

397 }

398 }

399

400 LLVMContext &C = L->getHeader()->getContext();

404 return true;

405}

406

410 if (ST->getCPUDirective() == PPC::DIR_A2) {

411

412

414

415

416

418 }

419

421}

422

427

428

429

430

434

436

437 if (ST->getCPUDirective() == PPC::DIR_A2)

438 return true;

439

440 return LoopHasReductions;

441}

442

446 if (getST()->hasAltivec())

447 Options.LoadSizes = {16, 8, 4, 2, 1};

448 else

449 Options.LoadSizes = {8, 4, 2, 1};

450

451 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);

453}

454

456

459 ClassID == VRRC || ClassID == VSXRC);

460 if (ST->hasVSX()) {

462 return ClassID == VSXRC ? 64 : 32;

463 }

465 return 32;

466}

467

470 return ST->hasVSX() ? VSXRC : VRRC;

471 if (Ty &&

472 (Ty->getScalarType()->isFloatTy() || Ty->getScalarType()->isDoubleTy()))

474 if (Ty && (Ty->getScalarType()->isFP128Ty() ||

475 Ty->getScalarType()->isPPC_FP128Ty()))

477 if (Ty && Ty->getScalarType()->isHalfTy())

480}

481

483

484 switch (ClassID) {

485 default:

487 return "PPC::unknown register class";

488 case GPRRC: return "PPC::GPRRC";

489 case FPRRC: return "PPC::FPRRC";

490 case VRRC: return "PPC::VRRC";

491 case VSXRC: return "PPC::VSXRC";

492 }

493}

494

497 switch (K) {

504 }

505

507}

508

510

511 unsigned Directive = ST->getCPUDirective();

512

516 return 128;

517

518

519 return 64;

520}

521

525

527 unsigned Directive = ST->getCPUDirective();

528

529

531 return 5;

532

533

534

536 return 6;

537

538

540 return 1;

541

542

543

544

545

546

550 return 12;

551

552

553

554 return 2;

555}

556

557

558

559

560

563 Type *Ty2) const {

564

565

566

567

570

571 if (!ST->vectorsUseTwoUnits() || !Ty1->isVectorTy())

573

575

576

577 if (LT1.first != 1 || !LT1.second.isVector())

579

580 int ISD = TLI->InstructionOpcodeToISD(Opcode);

581 if (TLI->isOperationExpand(ISD, LT1.second))

583

584 if (Ty2) {

586 if (LT2.first != 1 || !LT2.second.isVector())

588 }

589

591}

592

597 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");

598

600 if (!CostFactor.isValid())

602

603

606 Op2Info, Args, CxtI);

607

608

610 Opcode, Ty, CostKind, Op1Info, Op2Info);

611 return Cost * CostFactor;

612}

613

621

624 if (!CostFactor.isValid())

626

627

629

630

631

632

633

634

635 return LT.first * CostFactor;

636}

637

642 return Opcode == Instruction::PHI ? 0 : 1;

643

644 return 0;

645}

646

652 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");

653

655 if (!CostFactor.isValid())

657

660 Cost *= CostFactor;

661

663 return Cost == 0 ? 0 : 1;

665}

666

673 if (!CostFactor.isValid())

675

677 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);

678

681 return Cost * CostFactor;

682}

683

686 unsigned Index, const Value *Op0,

687 const Value *Op1) const {

689

690 int ISD = TLI->InstructionOpcodeToISD(Opcode);

692

694 if (!CostFactor.isValid())

696

699 Cost *= CostFactor;

700

702

704 Index == (ST->isLittleEndian() ? 1 : 0))

705 return 0;

706

708 }

711

712 unsigned MaskCostForOneBitSize = (VecMaskCost && EltSize == 1) ? 1 : 0;

713

714 unsigned MaskCostForIdx = (Index != -1U) ? 0 : 1;

715 if (ST->hasP9Altivec()) {

716

717

718

719

721 if (ST->hasP10Vector())

722 return CostFactor + MaskCostForIdx;

723 if (Index != -1U)

724 return 2 * CostFactor;

726

728

729 if (EltSize == 64 && Index != -1U)

730 return 1;

731 if (EltSize == 32) {

732 unsigned MfvsrwzIndex = ST->isLittleEndian() ? 2 : 1;

733 if (Index == MfvsrwzIndex)

734 return 1;

735

736

737

738 return CostFactor + MaskCostForIdx;

739 }

740

741

742

743

744 return CostFactor + MaskCostForOneBitSize + MaskCostForIdx;

745 }

746 } else if (ST->hasDirectMove() && Index != -1U) {

747

748

750 return 3;

751 return 3 + MaskCostForOneBitSize;

752 }

753 }

754

755

756

757

758

759 unsigned LHSPenalty = 2;

761 LHSPenalty += 7;

762

763

764

765

766

769 return LHSPenalty + Cost;

770

772}

773

780

782 if (!CostFactor.isValid())

784

785 if (TLI->getValueType(DL, Src, true) == MVT::Other)

788

790 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&

791 "Invalid Opcode");

792

795

798

799 Cost *= CostFactor;

800

801 bool IsAltivecType = ST->hasAltivec() &&

802 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||

803 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);

804 bool IsVSXType = ST->hasVSX() &&

805 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);

806

807

808

809

810

811

812 unsigned MemBits = Src->getPrimitiveSizeInBits();

813 unsigned SrcBytes = LT.second.getStoreSize();

814 if (ST->hasVSX() && IsAltivecType) {

815 if (MemBits == 64 || (ST->hasP8Vector() && MemBits == 32))

816 return 1;

817

818

819 if (Opcode == Instruction::Load && MemBits == 32 && Alignment < SrcBytes)

820 return 2;

821 }

822

823

824 if (!SrcBytes || Alignment >= SrcBytes)

826

827

828

829

830

831

832

833

834 if (Opcode == Instruction::Load && (!ST->hasP8Vector() && IsAltivecType) &&

835 Alignment >= LT.second.getScalarType().getStoreSize())

836 return Cost + LT.first;

837

838

839

840

841

842 if (IsVSXType || (ST->hasVSX() && IsAltivecType))

844

845

846 if (TLI->allowsMisalignedMemoryAccesses(LT.second, 0))

848

849

850

851

852

853 Cost += LT.first * ((SrcBytes / Alignment.value()) - 1);

854

855

856

857

858 if (Src->isVectorTy() && Opcode == Instruction::Store)

860 ++I)

862 nullptr, nullptr);

863

865}

866

870 bool UseMaskForCond, bool UseMaskForGaps) const {

873 if (!CostFactor.isValid())

875

876 if (UseMaskForCond || UseMaskForGaps)

879 UseMaskForCond, UseMaskForGaps);

880

882 "Expect a vector type for interleaved memory op");

883

884

886

887

890

891

892

893

894

895

896 Cost += Factor*(LT.first-1);

897

899}

900

906

908 const Function *Callee) const {

909 const TargetMachine &TM = getTLI()->getTargetMachine();

910

915

916

917

918 return CallerBits == CalleeBits;

919}

920

924

925

926

927

928

929

931 return false;

932

934 if (Ty->isSized())

935 return Ty->isIntOrIntVectorTy(1) && Ty->getPrimitiveSizeInBits() > 128;

936 return false;

937 });

938}

939

944

945 for (Loop *I : *L)

946 if (canSaveCmp(I, BI, SE, LI, DT, AC, LibInfo))

947 return false;

948

950

952 return false;

953

955 return false;

956

958 return false;

959

961 return true;

962}

963

975

977

980

982 return false;

984}

985

989 case Intrinsic::ppc_altivec_lvx:

990 case Intrinsic::ppc_altivec_lvxl:

991 case Intrinsic::ppc_altivec_lvebx:

992 case Intrinsic::ppc_altivec_lvehx:

993 case Intrinsic::ppc_altivec_lvewx:

994 case Intrinsic::ppc_vsx_lxvd2x:

995 case Intrinsic::ppc_vsx_lxvw4x:

996 case Intrinsic::ppc_vsx_lxvd2x_be:

997 case Intrinsic::ppc_vsx_lxvw4x_be:

998 case Intrinsic::ppc_vsx_lxvl:

999 case Intrinsic::ppc_vsx_lxvll:

1000 case Intrinsic::ppc_vsx_lxvp: {

1002 Info.ReadMem = true;

1003 Info.WriteMem = false;

1004 return true;

1005 }

1006 case Intrinsic::ppc_altivec_stvx:

1007 case Intrinsic::ppc_altivec_stvxl:

1008 case Intrinsic::ppc_altivec_stvebx:

1009 case Intrinsic::ppc_altivec_stvehx:

1010 case Intrinsic::ppc_altivec_stvewx:

1011 case Intrinsic::ppc_vsx_stxvd2x:

1012 case Intrinsic::ppc_vsx_stxvw4x:

1013 case Intrinsic::ppc_vsx_stxvd2x_be:

1014 case Intrinsic::ppc_vsx_stxvw4x_be:

1015 case Intrinsic::ppc_vsx_stxvl:

1016 case Intrinsic::ppc_vsx_stxvll:

1017 case Intrinsic::ppc_vsx_stxvp: {

1019 Info.ReadMem = false;

1020 Info.WriteMem = true;

1021 return true;

1022 }

1023 case Intrinsic::ppc_stbcx:

1024 case Intrinsic::ppc_sthcx:

1025 case Intrinsic::ppc_stdcx:

1026 case Intrinsic::ppc_stwcx: {

1028 Info.ReadMem = false;

1029 Info.WriteMem = true;

1030 return true;

1031 }

1032 default:

1033 break;

1034 }

1035

1036 return false;

1037}

1038

1040 return TLI->supportsTailCallFor(CB);

1041}

1042

1043

1044

1045

1049 unsigned Directive = ST->getCPUDirective();

1053 return DefaultLegalization;

1054

1055 if (!ST->isPPC64())

1056 return DefaultLegalization;

1057

1059 if (IID != Intrinsic::vp_load && IID != Intrinsic::vp_store)

1060 return DefaultLegalization;

1061

1062 bool IsLoad = IID == Intrinsic::vp_load;

1064 EVT VT = TLI->getValueType(DL, VecTy, true);

1065 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&

1066 VT != MVT::v16i8)

1067 return DefaultLegalization;

1068

1069 auto IsAllTrueMask = [](Value *MaskVal) {

1072 return ConstValue->isAllOnesValue();

1073 return false;

1074 };

1075 unsigned MaskIx = IsLoad ? 1 : 2;

1076 if (!IsAllTrueMask(PI.getOperand(MaskIx)))

1077 return DefaultLegalization;

1078

1080}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file provides a helper that implements much of the TTI interface in terms of the target-independ...

static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))

TargetTransformInfo::VPLegalization VPLegalization

This file provides the interface for the instcombine pass implementation.

uint64_t IntrinsicInst * II

static cl::opt< bool > VecMaskCost("ppc-vec-mask-cost", cl::desc("add masking cost for i1 vectors"), cl::init(true), cl::Hidden)

static cl::opt< bool > Pwr9EVL("ppc-pwr9-evl", cl::desc("Allow vp.load and vp.store for pwr9"), cl::init(false), cl::Hidden)

static cl::opt< bool > DisablePPCConstHoist("disable-ppc-constant-hoisting", cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden)

static cl::opt< unsigned > SmallCTRLoopThreshold("min-ctr-loop-threshold", cl::init(4), cl::Hidden, cl::desc("Loops with a constant trip count smaller than " "this value will not use the count register."))

static bool isMMAType(Type *Ty)

Definition PPCTargetTransformInfo.cpp:321

static cl::opt< bool > EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false), cl::desc("Enable using coldcc calling conv for cold " "internal functions"))

static cl::opt< bool > LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false), cl::desc("Do not add instruction count to lsr cost model"))

This file a TargetTransformInfoImplBase conforming object specific to the PPC target machine.

This file contains the declarations for profiling metadata utility functions.

static unsigned getNumElements(Type *Ty)

This file describes how to lower LLVM code to machine code.

This pass exposes codegen information to IR-level passes.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

A cache of @llvm.assume calls within a function.

LLVM Basic Block Representation.

InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const override

InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override

InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const override

bool shouldBuildRelLookupTables() const override

InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr) const override

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const override

void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP) const override

InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override

std::pair< InstructionCost, MVT > getTypeLegalizationCost(Type *Ty) const

InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const override

InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr) const override

Conditional or Unconditional Branch instruction.

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

Value * getArgOperand(unsigned i) const

static LLVM_ABI CastInst * Create(Instruction::CastOps, Value *S, Type *Ty, const Twine &Name="", InsertPosition InsertBefore=nullptr)

Provides a way to construct any of the CastInst subclasses using an opcode instead of the subclass's ...

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

This is an important base class in LLVM.

Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.

Container class for subtarget features.

Value * CreateInsertElement(Type *VecTy, Value *NewElt, Value *Idx, const Twine &Name="")

Value * CreateExtractElement(Value *Vec, Value *Idx, const Twine &Name="")

ConstantInt * getInt32(uint32_t C)

Get a constant 32-bit value.

Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")

The core instruction combiner logic.

const DataLayout & getDataLayout() const

DominatorTree & getDominatorTree() const

AssumptionCache & getAssumptionCache() const

static InstructionCost getInvalid(CostType Val=0)

static InstructionCost getMax()

A wrapper class for inspecting calls to intrinsic functions.

Intrinsic::ID getIntrinsicID() const

Return the intrinsic ID of this intrinsic.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

Represents a single loop in the control flow graph.

const FeatureBitset & getFeatureBits() const

bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const override

Definition PPCTargetTransformInfo.cpp:964

InstructionCost vectorCostAdjustmentFactor(unsigned Opcode, Type *Ty1, Type *Ty2) const

Definition PPCTargetTransformInfo.cpp:561

InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const override

Definition PPCTargetTransformInfo.cpp:593

Definition PPCTargetTransformInfo.cpp:774

Definition PPCTargetTransformInfo.cpp:867

bool enableInterleavedAccessVectorization() const override

Definition PPCTargetTransformInfo.cpp:455

unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const override

Definition PPCTargetTransformInfo.cpp:468

bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const override

Definition PPCTargetTransformInfo.cpp:940

TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override

Definition PPCTargetTransformInfo.cpp:444

unsigned getCacheLineSize() const override

Definition PPCTargetTransformInfo.cpp:509

bool useColdCCForColdCall(Function &F) const override

Definition PPCTargetTransformInfo.cpp:431

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const override

Definition PPCTargetTransformInfo.cpp:407

bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const override

Definition PPCTargetTransformInfo.cpp:986

TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override

Definition PPCTargetTransformInfo.cpp:496

bool isNumRegsMajorCostOfLSR() const override

Definition PPCTargetTransformInfo.cpp:976

unsigned getPrefetchDistance() const override

Definition PPCTargetTransformInfo.cpp:522

TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const override

Definition PPCTargetTransformInfo.cpp:1047

bool areInlineCompatible(const Function *Caller, const Function *Callee) const override

Definition PPCTargetTransformInfo.cpp:907

unsigned getNumberOfRegisters(unsigned ClassID) const override

Definition PPCTargetTransformInfo.cpp:457

bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const override

Definition PPCTargetTransformInfo.cpp:343

void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP) const override

Definition PPCTargetTransformInfo.cpp:423

InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const override

Definition PPCTargetTransformInfo.cpp:233

InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override

Definition PPCTargetTransformInfo.cpp:638

InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const override

Get intrinsic cost based on arguments.

Definition PPCTargetTransformInfo.cpp:902

const char * getRegisterClassName(unsigned ClassID) const override

Definition PPCTargetTransformInfo.cpp:482

InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const override

Definition PPCTargetTransformInfo.cpp:327

unsigned getMaxInterleaveFactor(ElementCount VF) const override

Definition PPCTargetTransformInfo.cpp:526

bool shouldBuildRelLookupTables() const override

Definition PPCTargetTransformInfo.cpp:978

bool supportsTailCallFor(const CallBase *CB) const override

Definition PPCTargetTransformInfo.cpp:1039

InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args={}, const Instruction *CxtI=nullptr) const override

Definition PPCTargetTransformInfo.cpp:614

InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const override

Definition PPCTargetTransformInfo.cpp:198

bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const override

Definition PPCTargetTransformInfo.cpp:921

TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override

Definition PPCTargetTransformInfo.cpp:60

Definition PPCTargetTransformInfo.cpp:667

bool enableAggressiveInterleaving(bool LoopHasReductions) const override

Definition PPCTargetTransformInfo.cpp:435

InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const override

Definition PPCTargetTransformInfo.cpp:167

InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override

Definition PPCTargetTransformInfo.cpp:684

InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override

Definition PPCTargetTransformInfo.cpp:647

std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override

Definition PPCTargetTransformInfo.cpp:69

Common code between 32-bit and 64-bit PowerPC targets.

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

static LLVM_ABI PoisonValue * get(Type *T)

Static factory methods - Return an 'poison' object of the specified type.

The main scalar evolution driver.

LLVM_ABI unsigned getSmallConstantTripCount(const Loop *L)

Returns the exact trip count of the loop if we can compute it, and the result is a small constant.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction for storing to memory.

Provides information about what library functions are available for the current target.

Primary interface to the complete machine description for the target machine.

virtual const TargetSubtargetInfo * getSubtargetImpl(const Function &) const

Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...

Provide an instruction scheduling machine model to CodeGen passes.

unsigned getIssueWidth() const

Maximum number of micro-ops that may be scheduled per cycle.

LLVM_ABI void init(const TargetSubtargetInfo *TSInfo, bool EnableSModel=true, bool EnableSItins=true)

Initialize the machine model for instruction scheduling.

virtual TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const

virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const

virtual InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const

virtual InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const

virtual bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const

virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const

virtual bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

TargetCostKind

The kind of cost model.

@ TCK_RecipThroughput

Reciprocal throughput.

PopcntSupportKind

Flags indicating the kind of support for population count.

@ TCC_Free

Expected to fold away in lowering.

@ TCC_Basic

The cost of a typical 'add' instruction.

ShuffleKind

The various kinds of shuffle patterns for vector queries.

CastContextHint

Represents a hint about the context in which a cast is used.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

static constexpr TypeSize getFixed(ScalarTy ExactSize)

static constexpr TypeSize getScalable(ScalarTy MinimumSize)

The instances of the Type class are immutable: once they are created, they are never changed.

static LLVM_ABI IntegerType * getInt64Ty(LLVMContext &C)

bool isVectorTy() const

True if this is an instance of VectorType.

static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)

Type * getScalarType() const

If this is a vector type, return the element type, otherwise return 'this'.

LLVM_ABI unsigned getScalarSizeInBits() const LLVM_READONLY

If this is a vector type, return the getPrimitiveSizeInBits value for the element type.

bool isDoubleTy() const

Return true if this is 'double', a 64-bit IEEE fp type.

bool isIntegerTy() const

True if this is an instance of IntegerType.

Value * getOperand(unsigned i) const

This is the common base class for vector predication intrinsics.

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

Base class of all SIMD vector types.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types a...

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI Value * getSplatValue(const Value *V)

Get splat value if the input is a splat vector or return nullptr.

constexpr bool isShiftedMask_32(uint32_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...

constexpr bool isShiftedMask_64(uint64_t Value)

Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

LLVM_ABI Align getOrEnforceKnownAlignment(Value *V, MaybeAlign PrefAlign, const DataLayout &DL, const Instruction *CxtI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr)

Try to ensure that the alignment of V is at least PrefAlign bytes.

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI bool extractBranchWeights(const MDNode *ProfileData, SmallVectorImpl< uint32_t > &Weights)

Extract branch weights from MD_prof metadata.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

This struct is a compact representation of a valid (non-zero power of two) alignment.

constexpr uint64_t value() const

This is a hole in the type system and should not be abused.

Utility to calculate the size and a few similar metrics for a set of basic blocks.

static LLVM_ABI void collectEphemeralValues(const Loop *L, AssumptionCache *AC, SmallPtrSetImpl< const Value * > &EphValues)

Collect a loop's ephemeral values (those used only by an assume or similar intrinsics in the loop).

Attributes of a target dependent hardware loop.

LLVM_ABI bool canAnalyze(LoopInfo &LI)

LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)

Information about a load/store intrinsic defined by the target.

unsigned Insns

TODO: Some of these could be merged.

Returns options for expansion of memcmp. IsZeroCmp is.

Parameters that control the generic loop unrolling transformation.

bool Runtime

Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...

bool Partial

Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...

bool AllowExpensiveTripCount

Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...