RISCVInstPrinter.cpp Source File (original) (raw)

23using namespace llvm;

25#define DEBUG_TYPE "asm-printer"

28#define PRINT_ALIAS_INSTR

29#include "RISCVGenAsmWriter.inc"

33 cl::desc("Disable the emission of assembler pseudo instructions"),

37 cl::desc("Emit x8 as fp instead of s0"),

52 if (Opt == "no-aliases") {

54 return true;

55 }

56 if (Opt == "numeric") {

58 return true;

59 }

60 if (Opt == "emit-x8-as-fp") {

63 return true;

64 }

66 return false;

67}

72 bool Res = false;

74 MCInst UncompressedMI;

77 if (Res)

78 NewMI = &UncompressedMI;

82}

91 const MCOperand &MO = MI->getOperand(OpNo);

95 return;

96 }

100 return;

101 }

102

103 assert(MO.isExpr() && "Unknown operand kind in printOperand");

105}

106

108 unsigned OpNo,

111 const MCOperand &MO = MI->getOperand(OpNo);

114

117 if (!STI.hasFeature(RISCV::Feature64Bit))

118 Target &= 0xffffffff;

120 } else {

122 }

123}

124

128 unsigned Imm = MI->getOperand(OpNo).getImm();

129 auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);

130 for (auto &Reg : Range) {

131 if (Reg.IsAltName || Reg.IsDeprecatedName)

132 continue;

133 if (Reg.haveRequiredFeatures(STI.getFeatureBits())) {

135 return;

136 }

137 }

139}

140

144 unsigned FenceArg = MI->getOperand(OpNo).getImm();

145 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");

146

148 O << 'i';

150 O << 'o';

152 O << 'r';

154 O << 'w';

155 if (FenceArg == 0)

156 O << "0";

157}

158

161 auto FRMArg =

164 return;

166}

167

171 auto FRMArg =

173

174

175

177 return;

179}

180

184 unsigned Imm = MI->getOperand(OpNo).getImm();

185 if (Imm == 1) {

187 } else if (Imm == 30) {

189 } else if (Imm == 31) {

191 } else {

193

194

195

196

197 if (FPVal == (int)(FPVal))

199 else

201 }

202}

203

207 const MCOperand &MO = MI->getOperand(OpNo);

208

209 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");

210 O << "(";

212 O << ")";

213}

214

217 unsigned Imm = MI->getOperand(OpNo).getImm();

218

219

223 !(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||

224 STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) ||

225 (Imm >> 9) != 0) {

227 return;

228 }

229

231}

232

236 unsigned Imm = MI->getOperand(OpNo).getImm();

239 O << "e" << SEW;

241 if (AltFmt)

242 O << "alt";

244 O << ", w" << Widen;

245}

246

247

248

249

252 unsigned Imm = MI->getOperand(OpNo).getImm();

253

256

257 O << "{";

259

261 O << ", ";

263 }

264

266 O << '-';

269 }

270

273 O << ", ";

276 }

277

280 O << '-';

282

283

287 }

288

289 O << "}";

290}

291

294 const MCOperand &OffsetMO = MI->getOperand(OpNo + 1);

295

296 assert(OffsetMO.isReg() && "printRegReg can only print register operands");

298

299 O << "(";

300 const MCOperand &BaseMO = MI->getOperand(OpNo);

301 assert(BaseMO.isReg() && "printRegReg can only print register operands");

303 O << ")";

304}

305

308 bool Negate) {

309 int64_t Imm = MI->getOperand(OpNo).getImm();

310 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);

311 int64_t StackAdj = 0;

312 auto RlistVal = MI->getOperand(0).getImm();

314 StackAdj = Imm + Base;

315 assert((StackAdj >= Base && StackAdj <= Base + 48) &&

316 "Incorrect stack adjust");

317 if (Negate)

318 StackAdj = -StackAdj;

319

320

322 O << StackAdj;

323}

324

328 const MCOperand &MO = MI->getOperand(OpNo);

329

330 assert(MO.isReg() && "printVMaskReg can only print register operands");

331 if (MO.getReg() == RISCV::NoRegister)

332 return;

333 O << ", ";

335 O << ".t";

336}

337

339

340

341

342

343

345 return "fp";

347 : RISCV::ABIRegAltName);

348}

static SDValue Widen(SelectionDAG *CurDAG, SDValue N)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > NoAliases("csky-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)

static cl::opt< bool > ArchRegNames("csky-arch-reg-names", cl::desc("Print architectural register names rather than the " "ABI names (such as r14 instead of sp)"), cl::init(false), cl::Hidden)

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

static cl::opt< bool > EmitX8AsFP("riscv-emit-x8-as-fp", cl::desc("Emit x8 as fp instead of s0"), cl::init(false), cl::Hidden)

static cl::opt< bool > NoAliases("riscv-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)

WithMarkup markup(raw_ostream &OS, Markup M)

format_object< int64_t > formatHex(int64_t Value) const

void printAnnotation(raw_ostream &OS, StringRef Annot)

Utility function for printing annotations.

format_object< int64_t > formatImm(int64_t Value) const

Utility function to print immediates in decimal or hex.

bool PrintBranchImmAsAddress

If true, a branch immediate (e.g.

bool PrintAliases

True if we prefer aliases (e.g. nop) to raw mnemonics.

Instances of this class represent a single low-level machine instruction.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const FeatureBitset & getFeatureBits() const

void printRegList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:250

static const char * getRegisterName(MCRegister Reg)

Definition RISCVInstPrinter.cpp:338

void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:125

void printXSfmmVType(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:233

void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:141

void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:325

bool applyTargetSpecificCLOption(StringRef Opt) override

Customize the printer according to a command line option.

Definition RISCVInstPrinter.cpp:51

void printFRMArgLegacy(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:168

bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:292

void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:159

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override

Print the specified MCInst to the specified raw_ostream.

Definition RISCVInstPrinter.cpp:69

void printFPImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:181

void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:204

void printRegName(raw_ostream &O, MCRegister Reg) override

Print the assembler register name.

Definition RISCVInstPrinter.cpp:84

void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:215

void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:88

void printStackAdj(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, bool Negate=false)

Definition RISCVInstPrinter.cpp:306

void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition RISCVInstPrinter.cpp:107

StringRef - Represent a constant reference to a string, i.e.

This class implements an extremely fast bulk output stream that can only output to a stream.

static StringRef roundingModeToString(RoundingMode RndMode)

float getFPImm(unsigned Imm)

bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)

static unsigned getXSfmmWiden(unsigned VType)

LLVM_ABI void printVType(unsigned VType, raw_ostream &OS)

static bool isValidXSfmmVType(unsigned VTypeI)

static bool isAltFmt(unsigned VType)

static unsigned getSEW(unsigned VType)

static VLMUL getVLMUL(unsigned VType)

static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64)

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

format_object< Ts... > format(const char *Fmt, const Ts &... Vals)

These are helper functions used to produce formatted output.