RISCVInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H

14#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H

21#define GET_INSTRINFO_HEADER

22#define GET_INSTRINFO_OPERAND_ENUM

23#include "RISCVGenInstrInfo.inc"

24#include "RISCVGenRegisterInfo.inc"

26namespace llvm {

33 return 0;

35 switch (Value >> Shift) {

36 case 3:

37 return 1;

38 case 5:

39 return 2;

40 case 9:

41 return 3;

42 default:

43 return 0;

44 }

45}

47class RISCVSubtarget;

67unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);

69}

84public:

92 int &FrameIndex) const override;

94 TypeSize &MemBytes) const override;

96 int &FrameIndex) const override;

98 TypeSize &MemBytes) const override;

101

103 return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&

104 MI.getOperand(1).getReg() == RISCV::X0;

105 }

106

113 bool KillSrc, bool RenamableDest = false,

114 bool RenamableSrc = false) const override;

115

119

122

127

132 int FrameIndex,

134 VirtRegMap *VRM = nullptr) const override;

135

136

140 bool DstRenamable = false, bool DstIsDead = false) const;

141

143

147 bool AllowModify) const override;

148

152 int *BytesAdded = nullptr) const override;

153

157 int64_t BrOffset, RegScavenger *RS) const override;

158

160 int *BytesRemoved = nullptr) const override;

161

162 bool

164

166

168

170 int64_t BrOffset) const override;

171

174 unsigned &FalseOp, bool &Optimizable) const override;

175

178 bool) const override;

179

181

182 std::optional

184

186 StringRef &ErrInfo) const override;

187

191

194

199

201 int64_t Offset1, bool OffsetIsScalable1,

203 int64_t Offset2, bool OffsetIsScalable2,

204 unsigned ClusterSize,

205 unsigned NumBytes) const override;

206

211

214

215

216 std::pair<unsigned, unsigned>

218

221

222

224 bool OutlineFromLinkOnceODRs) const override;

225

226

227

229 unsigned &Flags) const override;

230

232

233

234 std::optional<std::unique_ptroutliner::OutlinedFunction>

237 std::vectoroutliner::Candidate &RepeatedSequenceLocs,

238 unsigned MinRepeats) const override;

239

240

243 unsigned Flags) const override;

244

245

248

249

254

257

259 unsigned &SrcOpIdx2) const override;

261 unsigned OpIdx1,

262 unsigned OpIdx2) const override;

263

265

268

269

270 std::string

274

275

276

277

281

283

285

287

290 bool DoRegPressureReduce) const override;

291

292 void

295

301

304

306 bool &Commuted) const override;

307

309 bool Invert) const override;

310

311 std::optional getInverseOpcode(unsigned Opcode) const override;

312

315 std::array<unsigned, 5> &OperandIndices) const override;

316

319

321

322 std::unique_ptrTargetInstrInfo::PipelinerLoopInfo

324

326

327

329

332#define GET_INSTRINFO_HELPER_DECLS

333#include "RISCVGenInstrInfo.inc"

334

336

337

338

340

341

342

344 const MachineOperand &Op, int64_t &Imm);

345

346protected:

348

349private:

350 unsigned getInstBundleLength(const MachineInstr &MI) const;

351

352 bool isVectorAssociativeAndCommutative(const MachineInstr &MI,

353 bool Invert = false) const;

354 bool areRVVInstsReassociable(const MachineInstr &MI1,

356 bool hasReassociableVectorSibling(const MachineInstr &Inst,

357 bool &Commuted) const;

358};

359

361

362

363

365

366std::optional<std::pair<unsigned, unsigned>>

368

369

370

372

373

374

375

377 unsigned Log2SEW);

378

379

381

382

383

385

386

388

389

391

392

403}

404

406

411

412#define GET_RISCVVPseudosTable_DECL

413#include "RISCVGenSearchableTables.inc"

414

415}

416

418

424#define GET_RISCVMaskedPseudosTable_DECL

425#include "RISCVGenSearchableTables.inc"

426}

427

428}

429#endif

unsigned const MachineRegisterInfo * MRI

SmallVector< int16_t, MAX_SRC_OPERANDS_NUM > OperandIndices

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

This class contains meta information specific to a module.

MachineOperand class - Representation of each machine instruction operand.

A Module instance is used to store all the information related to an LLVM module.

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override

std::optional< std::unique_ptr< outliner::OutlinedFunction > > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override

void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const

MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override

void mulImm(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const

Generate code to multiply the value in DestReg by Amt - handles all the common optimizations for this...

static bool isPairableLdStInstOpc(unsigned Opc)

Return true if pairing the given load or store may be paired with another.

RISCVInstrInfo(const RISCVSubtarget &STI)

bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override

bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const override

static bool isLdStSafeToPair(const MachineInstr &LdSt, const TargetRegisterInfo *TRI)

void copyPhysRegVector(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RegClass) const

bool isReMaterializableImpl(const MachineInstr &MI) const override

MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override

bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override

void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override

bool isAsCheapAsAMove(const MachineInstr &MI) const override

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const

unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override

void getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const override

const RISCVSubtarget & STI

Definition RISCVInstrInfo.h:347

bool useMachineCombiner() const override

Definition RISCVInstrInfo.h:282

std::optional< unsigned > getInverseOpcode(unsigned Opcode) const override

bool simplifyInstruction(MachineInstr &MI) const override

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MBBI, unsigned Flags) const override

MachineTraceStrategy getMachineCombinerTraceStrategy() const override

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override

MCInst getNop() const override

MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override

bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override

void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override

bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override

Definition RISCVInstrInfo.h:102

bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override

MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override

std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override

bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

const RISCVRegisterInfo & getRegisterInfo() const

Definition RISCVInstrInfo.h:87

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc)

bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override

CombinerObjective getCombinerObjective(unsigned Pattern) const override

bool isHighLatencyDef(int Opc) const override

static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1)

Return the result of the evaluation of C0 CC C1, where CC is a RISCVCC::CondCode.

bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override

bool optimizeCondBranch(MachineInstr &MI) const override

std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override

bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override

static bool isFromLoadImm(const MachineRegisterInfo &MRI, const MachineOperand &Op, int64_t &Imm)

Return true if the operand is a load immediate instruction and sets Imm to the immediate value.

bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

Wrapper class representing virtual and physical registers.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const

Target-dependent implementation for foldMemoryOperand.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

LLVM Value Representation.

@ C

The default llvm calling convention, compatible with C.

Definition RISCVInstrInfo.h:54

CondCode getInverseBranchCondition(CondCode)

CondCode

Definition RISCVInstrInfo.h:56

@ COND_NE

Definition RISCVInstrInfo.h:58

@ COND_GEU

Definition RISCVInstrInfo.h:62

@ COND_LT

Definition RISCVInstrInfo.h:59

@ COND_EQ

Definition RISCVInstrInfo.h:57

@ COND_GE

Definition RISCVInstrInfo.h:60

@ COND_LTU

Definition RISCVInstrInfo.h:61

@ COND_INVALID

Definition RISCVInstrInfo.h:63

unsigned getBrCond(CondCode CC, unsigned SelectOpc=0)

static constexpr unsigned FPMASK_Negative_Zero

Definition RISCVInstrInfo.h:396

static constexpr unsigned FPMASK_Positive_Subnormal

Definition RISCVInstrInfo.h:398

bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2)

static constexpr unsigned FPMASK_Positive_Normal

Definition RISCVInstrInfo.h:399

static constexpr unsigned FPMASK_Negative_Subnormal

Definition RISCVInstrInfo.h:395

static constexpr unsigned FPMASK_Negative_Normal

Definition RISCVInstrInfo.h:394

bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS)

Given two VL operands, do we know that LHS <= RHS?

static constexpr unsigned FPMASK_Positive_Infinity

Definition RISCVInstrInfo.h:400

static constexpr unsigned FPMASK_Negative_Infinity

Definition RISCVInstrInfo.h:393

static constexpr unsigned FPMASK_Quiet_NaN

Definition RISCVInstrInfo.h:402

unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)

unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW)

std::optional< unsigned > getVectorLowDemandedScalarBits(unsigned Opcode, unsigned Log2SEW)

std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)

static constexpr unsigned FPMASK_Signaling_NaN

Definition RISCVInstrInfo.h:401

static constexpr unsigned FPMASK_Positive_Zero

Definition RISCVInstrInfo.h:397

bool isRVVSpill(const MachineInstr &MI)

static constexpr int64_t VLMaxSentinel

Definition RISCVInstrInfo.h:387

InstrType

Represents how an instruction should be mapped by the outliner.

This is an optimization pass for GlobalISel generic memory operations.

RISCVMachineCombinerPattern

Definition RISCVInstrInfo.h:72

@ SHXADD_ADD_SLLI_OP2

Definition RISCVInstrInfo.h:78

@ FMSUB

Definition RISCVInstrInfo.h:75

@ FMADD_AX

Definition RISCVInstrInfo.h:73

@ FMADD_XA

Definition RISCVInstrInfo.h:74

@ FNMSUB

Definition RISCVInstrInfo.h:76

@ SHXADD_ADD_SLLI_OP1

Definition RISCVInstrInfo.h:77

MachineTraceStrategy

Strategies for selecting traces.

static const MachineMemOperand::Flags MONontemporalBit1

Definition RISCVInstrInfo.h:51

static const MachineMemOperand::Flags MONontemporalBit0

Definition RISCVInstrInfo.h:49

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

CombinerObjective

The combiner's goal may differ based on which pattern it is attempting to optimize.

CodeGenOptLevel

Code generation optimization level.

int isShifted359(T Value, int &Shift)

Definition RISCVInstrInfo.h:31

DWARFExpression::Operation Op

Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.

Definition RISCVInstrInfo.h:407

uint16_t Pseudo

Definition RISCVInstrInfo.h:408

uint16_t BaseInstr

Definition RISCVInstrInfo.h:409

Definition RISCVInstrInfo.h:419

uint8_t MaskOpIdx

Definition RISCVInstrInfo.h:422

uint16_t MaskedPseudo

Definition RISCVInstrInfo.h:420

uint16_t UnmaskedPseudo

Definition RISCVInstrInfo.h:421

An individual sequence of instructions to be replaced with a call to an outlined function.

The information necessary to create an outlined function for some class of candidate.