AMDGPUAsmParser.cpp File Reference (original) (raw)

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Macros
#define	GET_REGISTER_MATCHER
#define	PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE)
#define	EXPR_RESOLVE_OR_ERROR(RESOLVED)
#define	GET_MATCHER_IMPLEMENTATION
#define	GET_MNEMONIC_SPELL_CHECKER
#define	GET_MNEMONIC_CHECKER
Auto-generated Match Functions
{
#define	GET_ASSEMBLER_HEADER

Functions
static const fltSemantics *	getFltSemantics (unsigned Size)
static const fltSemantics *	getFltSemantics (MVT VT)
static const fltSemantics *	getOpFltSemantics (uint8_t OperandType)
static bool	canLosslesslyConvertToFPType (APFloat &FPLiteral, MVT VT)
static bool	isSafeTruncation (int64_t Val, unsigned Size)
static bool	isInlineableLiteralOp16 (int64_t Val, MVT VT, bool HasInv2Pi)
static int	getRegClass (RegisterKind Is, unsigned RegWidth)
static MCRegister	getSpecialRegForName (StringRef RegName)
static bool	isRegularReg (RegisterKind Kind)
static const RegInfo *	getRegularRegInfo (StringRef Str)
static bool	getRegNum (StringRef Str, unsigned &Num)
static ArrayRef< unsigned >	getAllVariants ()
static OperandIndices	getSrcOperandIndices (unsigned Opcode, bool AddMandatoryLiterals=false)
static bool	checkWriteLane (const MCInst &Inst)
static bool	IsMovrelsSDWAOpcode (const unsigned Opcode)
static bool	IsRevOpcode (const unsigned Opcode)
static int	IsAGPROperand (const MCInst &Inst, AMDGPU::OpName Name, const MCRegisterInfo *MRI)
static std::string	AMDGPUMnemonicSpellCheck (StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
static bool	AMDGPUCheckMnemonic (StringRef Mnemonic, const FeatureBitset &AvailableFeatures, unsigned VariantID)
static bool	isInvalidVOPDY (const OperandVector &Operands, uint64_t InvalidOprIdx)
static void	applyMnemonicAliases (StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
static void	addOptionalImmOperand (MCInst &Inst, const OperandVector &Operands, AMDGPUAsmParser::OptionalImmIndexMap &OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default=0, std::optional< unsigned > InsertAt=std::nullopt)
static bool	encodeCnt (const AMDGPU::IsaVersion ISA, int64_t &IntVal, int64_t CntVal, bool Saturate, unsigned(encode)(const IsaVersion &Version, unsigned, unsigned), unsigned(decode)(const IsaVersion &Version, unsigned))
static LLVM_READNONE unsigned	encodeBitmaskPerm (const unsigned AndMask, const unsigned OrMask, const unsigned XorMask)
static bool	ConvertOmodMul (int64_t &Mul)
static bool	ConvertOmodDiv (int64_t &Div)
static void	cvtVOP3DstOpSelOnly (MCInst &Inst, const MCRegisterInfo &MRI)
static bool	isRegOrImmWithInputMods (const MCInstrDesc &Desc, unsigned OpNum)
static void	addSrcModifiersAndSrc (MCInst &Inst, const OperandVector &Operands, unsigned i, unsigned Opc, AMDGPU::OpName OpName)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void	LLVMInitializeAMDGPUAsmParser ()
	Force static initialization.

◆ EXPR_RESOLVE_OR_ERROR

#define EXPR_RESOLVE_OR_ERROR	(	RESOLVED	)

Value:

if (!(RESOLVED)) \

return Error(IDRange.Start, "directive should have resolvable expression", \

IDRange);

◆ GET_ASSEMBLER_HEADER

#define GET_ASSEMBLER_HEADER

◆ GET_MATCHER_IMPLEMENTATION

#define GET_MATCHER_IMPLEMENTATION

◆ GET_MNEMONIC_CHECKER

#define GET_MNEMONIC_CHECKER

◆ GET_MNEMONIC_SPELL_CHECKER

#define GET_MNEMONIC_SPELL_CHECKER

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

◆ PARSE_BITS_ENTRY

#define PARSE_BITS_ENTRY	(	FIELD,
ENTRY,
VALUE,
RANGE )

Value:

return OutOfRangeError(RANGE); \

AMDGPU::MCKernelDescriptor::bits_set(FIELD, VALUE, ENTRY##_SHIFT, ENTRY, \

getContext());

#define ENTRY(ASMNAME, ENUM)

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

◆ OperandIndices

◆ addOptionalImmOperand()

void addOptionalImmOperand ( MCInst & Inst, const OperandVector & Operands, AMDGPUAsmParser::OptionalImmIndexMap & OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default = 0, std::optional< unsigned > InsertAt = std::nullopt )	static

◆ addSrcModifiersAndSrc()

◆ AMDGPUCheckMnemonic()

◆ AMDGPUMnemonicSpellCheck()

◆ applyMnemonicAliases()

◆ canLosslesslyConvertToFPType()

◆ checkWriteLane()

◆ ConvertOmodDiv()

bool ConvertOmodDiv ( int64_t & Div)	static

◆ ConvertOmodMul()

bool ConvertOmodMul ( int64_t & Mul)	static

◆ cvtVOP3DstOpSelOnly()

Definition at line 9192 of file AMDGPUAsmParser.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::SISrcMods::DST_OP_SEL, llvm::MCOperand::getImm(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::DstOp::getReg(), llvm::AMDGPU::hasNamedOperand(), llvm::AMDGPU::isHi16Reg(), MRI, Opc, and llvm::MCOperand::setImm().

◆ encodeBitmaskPerm()

◆ encodeCnt()

◆ getAllVariants()

◆ getFltSemantics() [1/2]

◆ getFltSemantics() [2/2]

◆ getOpFltSemantics()

Definition at line 2017 of file AMDGPUAsmParser.cpp.

◆ getRegClass()

int getRegClass ( RegisterKind Is, unsigned RegWidth )	static

◆ getRegNum()

◆ getRegularRegInfo()

◆ getSpecialRegForName()

◆ getSrcOperandIndices()

OperandIndices getSrcOperandIndices ( unsigned Opcode, bool AddMandatoryLiterals = false )	static

◆ IsAGPROperand()

◆ isInlineableLiteralOp16()

bool isInlineableLiteralOp16 ( int64_t Val, MVT VT, bool HasInv2Pi )	static

◆ isInvalidVOPDY()

◆ IsMovrelsSDWAOpcode()

◆ isRegOrImmWithInputMods()

◆ isRegularReg()

bool isRegularReg ( RegisterKind Kind)	static