RISCVInstrInfo.h File Reference (original) (raw)

#include "[RISCV.h](RISCV%5F8h%5Fsource.html)"
#include "[RISCVRegisterInfo.h](RISCVRegisterInfo%5F8h%5Fsource.html)"
#include "[llvm/CodeGen/TargetInstrInfo.h](TargetInstrInfo%5F8h%5Fsource.html)"
#include "[llvm/IR/DiagnosticInfo.h](DiagnosticInfo%5F8h%5Fsource.html)"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenRegisterInfo.inc"
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::RISCVCC
namespace	llvm::RISCV
namespace	llvm::RISCVVPseudosTable

Macros
#define	GET_INSTRINFO_HEADER
#define	GET_INSTRINFO_OPERAND_ENUM
#define	GET_INSTRINFO_HELPER_DECLS
#define	GET_RISCVVPseudosTable_DECL
#define	GET_RISCVMaskedPseudosTable_DECL

Enumerations
enum	llvm::RISCVCC::CondCode { llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_NE, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_INVALID }
enum	llvm::RISCVMachineCombinerPattern : unsigned { llvm::FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START , llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::SHXADD_ADD_SLLI_OP1, llvm::SHXADD_ADD_SLLI_OP2 }

Functions
template<typename T>
int	llvm::isShifted359 (T Value, int &Shift)
CondCode	llvm::RISCVCC::getInverseBranchCondition (CondCode)
unsigned	llvm::RISCVCC::getBrCond (CondCode CC, unsigned SelectOpc=0)
bool	llvm::RISCV::isRVVSpill (const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > >	llvm::RISCV::isRVVSpillForZvlsseg (unsigned Opcode)
bool	llvm::RISCV::hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)
std::optional< unsigned >	llvm::RISCV::getVectorLowDemandedScalarBits (unsigned Opcode, unsigned Log2SEW)
unsigned	llvm::RISCV::getRVVMCOpcode (unsigned RVVPseudoOpcode)
unsigned	llvm::RISCV::getDestLog2EEW (const MCInstrDesc &Desc, unsigned Log2SEW)
bool	llvm::RISCV::isVLKnownLE (const MachineOperand &LHS, const MachineOperand &RHS)
	Given two VL operands, do we know that LHS <= RHS?

Variables
static const MachineMemOperand::Flags	llvm::MONontemporalBit0
static const MachineMemOperand::Flags	llvm::MONontemporalBit1
static constexpr int64_t	llvm::RISCV::VLMaxSentinel = -1LL
static constexpr unsigned	llvm::RISCV::FPMASK_Negative_Infinity = 0x001
static constexpr unsigned	llvm::RISCV::FPMASK_Negative_Normal = 0x002
static constexpr unsigned	llvm::RISCV::FPMASK_Negative_Subnormal = 0x004
static constexpr unsigned	llvm::RISCV::FPMASK_Negative_Zero = 0x008
static constexpr unsigned	llvm::RISCV::FPMASK_Positive_Zero = 0x010
static constexpr unsigned	llvm::RISCV::FPMASK_Positive_Subnormal = 0x020
static constexpr unsigned	llvm::RISCV::FPMASK_Positive_Normal = 0x040
static constexpr unsigned	llvm::RISCV::FPMASK_Positive_Infinity = 0x080
static constexpr unsigned	llvm::RISCV::FPMASK_Signaling_NaN = 0x100
static constexpr unsigned	llvm::RISCV::FPMASK_Quiet_NaN = 0x200

◆ GET_INSTRINFO_HEADER

#define GET_INSTRINFO_HEADER

◆ GET_INSTRINFO_HELPER_DECLS

#define GET_INSTRINFO_HELPER_DECLS

◆ GET_INSTRINFO_OPERAND_ENUM

#define GET_INSTRINFO_OPERAND_ENUM

◆ GET_RISCVMaskedPseudosTable_DECL

#define GET_RISCVMaskedPseudosTable_DECL

◆ GET_RISCVVPseudosTable_DECL

#define GET_RISCVVPseudosTable_DECL