RISCVMCCodeEmitter.cpp Source File (original) (raw)

31using namespace llvm;

33#define DEBUG_TYPE "mccodeemitter"

35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");

36 STATISTIC(MCNumFixups, "Number of MC fixups created");

38namespace {

40 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;

41 void operator=(const RISCVMCCodeEmitter &) = delete;

45public:

47 : Ctx(ctx), MCII(MCII) {}

49 ~RISCVMCCodeEmitter() override = default;

51 void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB,

52 SmallVectorImpl &Fixups,

53 const MCSubtargetInfo &STI) const override;

55 void expandFunctionCall(const MCInst &MI, SmallVectorImpl &CB,

56 SmallVectorImpl &Fixups,

57 const MCSubtargetInfo &STI) const;

59 void expandTLSDESCCall(const MCInst &MI, SmallVectorImpl &CB,

60 SmallVectorImpl &Fixups,

61 const MCSubtargetInfo &STI) const;

63 void expandAddTPRel(const MCInst &MI, SmallVectorImpl &CB,

64 SmallVectorImpl &Fixups,

65 const MCSubtargetInfo &STI) const;

67 void expandLongCondBr(const MCInst &MI, SmallVectorImpl &CB,

68 SmallVectorImpl &Fixups,

69 const MCSubtargetInfo &STI) const;

71 void expandQCLongCondBrImm(const MCInst &MI, SmallVectorImpl &CB,

72 SmallVectorImpl &Fixups,

73 const MCSubtargetInfo &STI, unsigned Size) const;

77 uint64_t getBinaryCodeForInstr(const MCInst &MI,

78 SmallVectorImpl &Fixups,

79 const MCSubtargetInfo &STI) const;

83 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,

84 SmallVectorImpl &Fixups,

85 const MCSubtargetInfo &STI) const;

87 uint64_t getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,

88 SmallVectorImpl &Fixups,

89 const MCSubtargetInfo &STI) const;

91 uint64_t getImmOpValueSlist(const MCInst &MI, unsigned OpNo,

92 SmallVectorImpl &Fixups,

93 const MCSubtargetInfo &STI) const;

95 template

96 unsigned getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,

97 SmallVectorImpl &Fixups,

98 const MCSubtargetInfo &STI) const;

100 uint64_t getImmOpValueZibi(const MCInst &MI, unsigned OpNo,

101 SmallVectorImpl &Fixups,

102 const MCSubtargetInfo &STI) const;

103

104 uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,

105 SmallVectorImpl &Fixups,

106 const MCSubtargetInfo &STI) const;

107

108 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,

109 SmallVectorImpl &Fixups,

110 const MCSubtargetInfo &STI) const;

111

112 unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo,

113 SmallVectorImpl &Fixups,

114 const MCSubtargetInfo &STI) const;

115

116 unsigned getRlistS0OpValue(const MCInst &MI, unsigned OpNo,

117 SmallVectorImpl &Fixups,

118 const MCSubtargetInfo &STI) const;

119};

120}

121

124 return new RISCVMCCodeEmitter(Ctx, MCII);

125}

126

129 bool PCRel = false;

130 switch (Kind) {

131 case ELF::R_RISCV_CALL_PLT:

144 PCRel = true;

145 }

147}

148

149

150

151

152

153

154

155

156

157void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,

161 MCInst TmpInst;

162 MCOperand Func;

163 MCRegister Ra;

164 if (MI.getOpcode() == RISCV::PseudoTAIL) {

165 Func = MI.getOperand(0);

167 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {

168 Func = MI.getOperand(1);

169 Ra = MI.getOperand(0).getReg();

170 } else if (MI.getOpcode() == RISCV::PseudoCALL) {

171 Func = MI.getOperand(0);

172 Ra = RISCV::X1;

173 } else if (MI.getOpcode() == RISCV::PseudoJump) {

174 Func = MI.getOperand(1);

175 Ra = MI.getOperand(0).getReg();

176 }

178

179 assert(Func.isExpr() && "Expected expression");

180

181 const MCExpr *CallExpr = Func.getExpr();

182

183

184 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr);

185 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

187

188 if (MI.getOpcode() == RISCV::PseudoTAIL ||

189 MI.getOpcode() == RISCV::PseudoJump)

190

191 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);

192 else

193

194 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);

195 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

197}

198

199void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,

200 SmallVectorImpl &CB,

201 SmallVectorImpl &Fixups,

202 const MCSubtargetInfo &STI) const {

203 MCOperand SrcSymbol = MI.getOperand(3);

205 "Expected expression as first input to TLSDESCCALL");

207 MCRegister Link = MI.getOperand(0).getReg();

208 MCRegister Dest = MI.getOperand(1).getReg();

209 int64_t Imm = MI.getOperand(2).getImm();

210 addFixup(Fixups, 0, Expr, ELF::R_RISCV_TLSDESC_CALL);

211 MCInst Call =

212 MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);

213

214 uint32_t Binary = getBinaryCodeForInstr(Call, Fixups, STI);

216}

217

218

219void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,

220 SmallVectorImpl &CB,

221 SmallVectorImpl &Fixups,

222 const MCSubtargetInfo &STI) const {

223 MCOperand DestReg = MI.getOperand(0);

224 MCOperand SrcReg = MI.getOperand(1);

225 MCOperand TPReg = MI.getOperand(2);

227 "Expected thread pointer as second input to TP-relative add");

228

229 MCOperand SrcSymbol = MI.getOperand(3);

231 "Expected expression as third input to TP-relative add");

232

234 assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&

235 "Expected tprel_add relocation on TP-relative symbol");

236

237 addFixup(Fixups, 0, Expr, ELF::R_RISCV_TPREL_ADD);

238 if (STI.hasFeature(RISCV::FeatureRelax))

239 Fixups.back().setLinkerRelaxable();

240

241

242 MCInst TmpInst = MCInstBuilder(RISCV::ADD)

244 .addOperand(SrcReg)

245 .addOperand(TPReg);

246 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

248}

249

251 switch (BrOp) {

252 default:

254 case RISCV::PseudoLongBEQ:

255 return RISCV::BNE;

256 case RISCV::PseudoLongBNE:

257 return RISCV::BEQ;

258 case RISCV::PseudoLongBLT:

259 return RISCV::BGE;

260 case RISCV::PseudoLongBGE:

261 return RISCV::BLT;

262 case RISCV::PseudoLongBLTU:

263 return RISCV::BGEU;

264 case RISCV::PseudoLongBGEU:

265 return RISCV::BLTU;

266 case RISCV::PseudoLongQC_BEQI:

267 return RISCV::QC_BNEI;

268 case RISCV::PseudoLongQC_BNEI:

269 return RISCV::QC_BEQI;

270 case RISCV::PseudoLongQC_BLTI:

271 return RISCV::QC_BGEI;

272 case RISCV::PseudoLongQC_BGEI:

273 return RISCV::QC_BLTI;

274 case RISCV::PseudoLongQC_BLTUI:

275 return RISCV::QC_BGEUI;

276 case RISCV::PseudoLongQC_BGEUI:

277 return RISCV::QC_BLTUI;

278 case RISCV::PseudoLongQC_E_BEQI:

279 return RISCV::QC_E_BNEI;

280 case RISCV::PseudoLongQC_E_BNEI:

281 return RISCV::QC_E_BEQI;

282 case RISCV::PseudoLongQC_E_BLTI:

283 return RISCV::QC_E_BGEI;

284 case RISCV::PseudoLongQC_E_BGEI:

285 return RISCV::QC_E_BLTI;

286 case RISCV::PseudoLongQC_E_BLTUI:

287 return RISCV::QC_E_BGEUI;

288 case RISCV::PseudoLongQC_E_BGEUI:

289 return RISCV::QC_E_BLTUI;

290 }

291}

292

293

294

295void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,

296 SmallVectorImpl &CB,

297 SmallVectorImpl &Fixups,

298 const MCSubtargetInfo &STI) const {

299 MCRegister SrcReg1 = MI.getOperand(0).getReg();

300 MCRegister SrcReg2 = MI.getOperand(1).getReg();

301 MCOperand SrcSymbol = MI.getOperand(2);

302 unsigned Opcode = MI.getOpcode();

303 bool IsEqTest =

304 Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;

305

306 bool UseCompressedBr = false;

307 if (IsEqTest && STI.hasFeature(RISCV::FeatureStdExtZca)) {

308 if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&

309 SrcReg2.id() == RISCV::X0) {

310 UseCompressedBr = true;

311 } else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 &&

312 SrcReg1.id() == RISCV::X0) {

314 UseCompressedBr = true;

315 }

316 }

317

319 if (UseCompressedBr) {

320 unsigned InvOpc =

321 Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ;

322 MCInst TmpInst = MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(6);

323 uint16_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

326 } else {

328 MCInst TmpInst =

329 MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8);

330 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

333 }

334

335

336 size_t FixupStartIndex = Fixups.size();

337

338

339 MCInst TmpInst =

340 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol);

341 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

343

344

345 Fixups.resize(FixupStartIndex);

346

347 if (SrcSymbol.isExpr())

349}

350

351

352

353void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,

354 SmallVectorImpl &CB,

355 SmallVectorImpl &Fixups,

356 const MCSubtargetInfo &STI,

357 unsigned Size) const {

358 MCRegister SrcReg1 = MI.getOperand(0).getReg();

359 auto BrImm = MI.getOperand(1).getImm();

360 MCOperand SrcSymbol = MI.getOperand(2);

361 unsigned Opcode = MI.getOpcode();

364

365

366

367

368 if (Size == 4) {

369 MCInst TmpBr =

370 MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(BrImm).addImm(8);

371 uint32_t BrBinary = getBinaryCodeForInstr(TmpBr, Fixups, STI);

373 } else {

374 MCInst TmpBr =

375 MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(BrImm).addImm(10);

376 uint64_t BrBinary =

377 getBinaryCodeForInstr(TmpBr, Fixups, STI) & 0xffff'ffff'ffffu;

378 SmallVector<char, 8> Encoding;

380 assert(Encoding[6] == 0 && Encoding[7] == 0 &&

381 "Unexpected encoding for 48-bit instruction");

384 }

386

387 size_t FixupStartIndex = Fixups.size();

388

389 MCInst TmpJ =

390 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol);

391 uint32_t JBinary = getBinaryCodeForInstr(TmpJ, Fixups, STI);

393

394 Fixups.resize(FixupStartIndex);

395 if (SrcSymbol.isExpr())

397}

398

399void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,

400 SmallVectorImpl &CB,

401 SmallVectorImpl &Fixups,

402 const MCSubtargetInfo &STI) const {

403 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

404

405 unsigned Size = Desc.getSize();

406

407

408

409

410 switch (MI.getOpcode()) {

411 default:

412 break;

413 case RISCV::PseudoCALLReg:

414 case RISCV::PseudoCALL:

415 case RISCV::PseudoTAIL:

416 case RISCV::PseudoJump:

417 expandFunctionCall(MI, CB, Fixups, STI);

418 MCNumEmitted += 2;

419 return;

420 case RISCV::PseudoAddTPRel:

421 expandAddTPRel(MI, CB, Fixups, STI);

422 MCNumEmitted += 1;

423 return;

424 case RISCV::PseudoLongBEQ:

425 case RISCV::PseudoLongBNE:

426 case RISCV::PseudoLongBLT:

427 case RISCV::PseudoLongBGE:

428 case RISCV::PseudoLongBLTU:

429 case RISCV::PseudoLongBGEU:

430 expandLongCondBr(MI, CB, Fixups, STI);

431 MCNumEmitted += 2;

432 return;

433 case RISCV::PseudoLongQC_BEQI:

434 case RISCV::PseudoLongQC_BNEI:

435 case RISCV::PseudoLongQC_BLTI:

436 case RISCV::PseudoLongQC_BGEI:

437 case RISCV::PseudoLongQC_BLTUI:

438 case RISCV::PseudoLongQC_BGEUI:

439 expandQCLongCondBrImm(MI, CB, Fixups, STI, 4);

440 MCNumEmitted += 2;

441 return;

442 case RISCV::PseudoLongQC_E_BEQI:

443 case RISCV::PseudoLongQC_E_BNEI:

444 case RISCV::PseudoLongQC_E_BLTI:

445 case RISCV::PseudoLongQC_E_BGEI:

446 case RISCV::PseudoLongQC_E_BLTUI:

447 case RISCV::PseudoLongQC_E_BGEUI:

448 expandQCLongCondBrImm(MI, CB, Fixups, STI, 6);

449 MCNumEmitted += 2;

450 return;

451 case RISCV::PseudoTLSDESCCall:

452 expandTLSDESCCall(MI, CB, Fixups, STI);

453 MCNumEmitted += 1;

454 return;

455 }

456

457 switch (Size) {

458 default:

460 case 2: {

461 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);

463 break;

464 }

465 case 4: {

466 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);

468 break;

469 }

470 case 6: {

471 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI) & 0xffff'ffff'ffffu;

472 SmallVector<char, 8> Encoding;

474 assert(Encoding[6] == 0 && Encoding[7] == 0 &&

475 "Unexpected encoding for 48-bit instruction");

478 break;

479 }

480 case 8: {

481 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);

483 break;

484 }

485 }

486

487 ++MCNumEmitted;

488}

489

490uint64_t

491RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,

492 SmallVectorImpl &Fixups,

493 const MCSubtargetInfo &STI) const {

494

497

500

502 return 0;

503}

504

505uint64_t

506RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,

507 SmallVectorImpl &Fixups,

508 const MCSubtargetInfo &STI) const {

509 const MCOperand &MO = MI.getOperand(OpNo);

510

511 if (MO.isImm()) {

512 uint64_t Res = MO.getImm();

513 return (Res - 1);

514 }

515

517 return 0;

518}

519

520uint64_t

521RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,

522 SmallVectorImpl &Fixups,

523 const MCSubtargetInfo &STI) const {

524 const MCOperand &MO = MI.getOperand(OpNo);

525 assert(MO.isImm() && "Slist operand must be immediate");

526

527 uint64_t Res = MO.getImm();

528 switch (Res) {

529 case 0:

530 return 0;

531 case 1:

532 return 1;

533 case 2:

534 return 2;

535 case 4:

536 return 3;

537 case 8:

538 return 4;

539 case 16:

540 return 5;

541 case 15:

542 return 6;

543 case 31:

544 return 7;

545 default:

547 }

548}

549

550template

551unsigned

552RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,

553 SmallVectorImpl &Fixups,

554 const MCSubtargetInfo &STI) const {

555 const MCOperand &MO = MI.getOperand(OpNo);

556

557 if (MO.isImm()) {

558 uint64_t Res = MO.getImm();

559 assert((Res & ((1 << N) - 1)) == 0 && "LSB is non-zero");

560 return Res >> N;

561 }

562

563 return getImmOpValue(MI, OpNo, Fixups, STI);

564}

565

566uint64_t

567RISCVMCCodeEmitter::getImmOpValueZibi(const MCInst &MI, unsigned OpNo,

568 SmallVectorImpl &Fixups,

569 const MCSubtargetInfo &STI) const {

570 const MCOperand &MO = MI.getOperand(OpNo);

571 assert(MO.isImm() && "Zibi operand must be an immediate");

572 int64_t Res = MO.getImm();

573 if (Res == -1)

574 return 0;

575

576 return Res;

577}

578

579uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,

580 SmallVectorImpl &Fixups,

581 const MCSubtargetInfo &STI) const {

582 bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax);

583 const MCOperand &MO = MI.getOperand(OpNo);

584

585 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());

587

588

591

593 "getImmOpValue expects only expressions or immediates");

594 const MCExpr *Expr = MO.getExpr();

596

597

598

599

600

601

602

603

604 bool RelaxCandidate = false;

605 auto AsmRelaxToLinkerRelaxableWithFeature = [&](unsigned Feature) -> void {

607 RelaxCandidate = true;

608 };

609

613 FixupKind = RVExpr->getSpecifier();

614 switch (RVExpr->getSpecifier()) {

615 default:

617 "invalid specifier");

618 break;

619 case ELF::R_RISCV_TPREL_ADD:

620

621

622

623

625 "ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");

631 else

632 llvm_unreachable("VK_LO used with unexpected instruction format");

633 RelaxCandidate = true;

634 break;

635 case ELF::R_RISCV_HI20:

637 RelaxCandidate = true;

638 break;

644 else

645 llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");

646 RelaxCandidate = true;

647 break;

648 case ELF::R_RISCV_PCREL_HI20:

650 RelaxCandidate = true;

651 break;

654 FixupKind = ELF::R_RISCV_TPREL_LO12_I;

656 FixupKind = ELF::R_RISCV_TPREL_LO12_S;

657 else

658 llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");

659 RelaxCandidate = true;

660 break;

661 case ELF::R_RISCV_TPREL_HI20:

662 RelaxCandidate = true;

663 break;

664 case ELF::R_RISCV_CALL_PLT:

666 RelaxCandidate = true;

667 break;

670 RelaxCandidate = true;

671 break;

672 }

674

677 AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb);

680

681

684 AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb);

687

688

691 AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcili);

696

697

700 RelaxCandidate = true;

703 RelaxCandidate = true;

706 }

707 }

708

710

712

713

714

715 if (EnableRelax && RelaxCandidate)

716 Fixups.back().setLinkerRelaxable();

717 ++MCNumFixups;

718

719 return 0;

720}

721

722unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,

723 SmallVectorImpl &Fixups,

724 const MCSubtargetInfo &STI) const {

725 MCOperand MO = MI.getOperand(OpNo);

726 assert(MO.isReg() && "Expected a register.");

727

729 default:

731 case RISCV::V0:

732 return 0;

733 case RISCV::NoRegister:

734 return 1;

735 }

736}

737

738unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo,

739 SmallVectorImpl &Fixups,

740 const MCSubtargetInfo &STI) const {

741 const MCOperand &MO = MI.getOperand(OpNo);

742 assert(MO.isImm() && "Rlist operand must be immediate");

744 assert(Imm >= 4 && "EABI is currently not implemented");

745 return Imm;

746}

747unsigned

748RISCVMCCodeEmitter::getRlistS0OpValue(const MCInst &MI, unsigned OpNo,

749 SmallVectorImpl &Fixups,

750 const MCSubtargetInfo &STI) const {

751 const MCOperand &MO = MI.getOperand(OpNo);

752 assert(MO.isImm() && "Rlist operand must be immediate");

754 assert(Imm >= 4 && "EABI is currently not implemented");

756 return Imm;

757}

758

759#include "RISCVGenMCCodeEmitter.inc"

static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static unsigned getInvertedBranchOp(unsigned BrOp)

Definition RISCVMCCodeEmitter.cpp:250

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

const MCRegisterInfo * getRegisterInfo() const

Base class for the full range of assembler expressions which are needed for parsing.

@ SymbolRef

References to labels and assigned expressions.

@ Specifier

Expression with a relocation specifier.

@ Binary

Binary expressions.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

uint16_t getEncodingValue(MCRegister Reg) const

Returns the encoding for Reg.

constexpr unsigned id() const

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const FeatureBitset & getFeatureBits() const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void append(ItTy in_start, ItTy in_end)

Add the specified range to the end of the SmallVector.

void truncate(size_type N)

Like resize, but requires that N is less than size().

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ InstFormatNDS_BRANCH_10

static unsigned getFormat(uint64_t TSFlags)

static MCRegister getTailExpandUseRegNo(const FeatureBitset &FeatureBits)

@ fixup_riscv_pcrel_lo12_i

@ fixup_riscv_pcrel_lo12_s

@ fixup_riscv_nds_branch_10

@ fixup_riscv_qc_e_call_plt

@ fixup_riscv_qc_e_branch

NodeAddr< FuncNode * > Func

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Definition RISCVMCCodeEmitter.cpp:122

static Lanai::Fixups FixupKind(const MCExpr *Expr)

static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.