RISCVSubtarget.cpp Source File (original) (raw)

23using namespace llvm;

25#define DEBUG_TYPE "riscv-subtarget"

27#define GET_SUBTARGETINFO_TARGET_DESC

28#define GET_SUBTARGETINFO_CTOR

29#include "RISCVGenSubtargetInfo.inc"

31#define GET_RISCV_MACRO_FUSION_PRED_IMPL

32#include "RISCVGenMacroFusion.inc"

36#define GET_RISCVTuneInfoTable_IMPL

37#include "RISCVGenSearchableTables.inc"

38}

41 "riscv-v-fixed-length-vector-lmul-max",

42 cl::desc("The maximum LMUL value to use for fixed length vectors. "

43 "Fractional LMUL values are not supported."),

47 "riscv-disable-using-constant-pool-for-large-ints",

48 cl::desc("Disable using constant pool for large integers."),

52 "riscv-max-build-ints-cost",

53 cl::desc("The maximum cost used for building integers."), cl::init(0),

57 cl::desc("Enable the use of AA during codegen."));

60 "riscv-min-jump-table-entries", cl::Hidden,

61 cl::desc("Set minimum number of entries to use a jump table on RISCV"));

64 "use-riscv-mips-load-store-pairs",

65 cl::desc("Enable the load/store pair optimization pass"), cl::init(false),

69 cl::desc("Use 'mips.ccmov' instruction"),

73 "enable-p-ext-codegen",

74 cl::desc("Turn on P Extension codegen(This is a temporary switch where "

75 "only partial codegen is currently supported)"),

78void RISCVSubtarget::anchor() {}

81RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,

85 bool Is64Bit = TT.isArch64Bit();

86 if (CPU.empty() || CPU == "generic")

87 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";

89 if (TuneCPU.empty())

90 TuneCPU = CPU;

91 if (TuneCPU == "generic")

92 TuneCPU = Is64Bit ? "generic-rv64" : "generic-rv32";

94 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(TuneCPU);

96 if (!TuneInfo)

97 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo("generic");

98 assert(TuneInfo && "TuneInfo shouldn't be nullptr!");

103 return *this;

104}

105

108 StringRef ABIName, unsigned RVVVectorBitsMin,

109 unsigned RVVVectorBitsMax,

112 RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),

113 FrameLowering(

114 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),

115 InstrInfo(*this), TLInfo(TM, *this) {

116 TSInfo = std::make_unique();

117}

118

120

124

130

139

145

151

155

159

161

162

163

164

165

167 ? getSchedModel().LoadLatency + 1

169}

170

173 "Tried to get vector length without Zve or V extension support!");

174

175

176

177 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)

179 "than the Zvl*b limitation");

180

181 return RVVVectorBitsMax;

182}

183

186 "Tried to get vector length without Zve or V extension support!");

187

188 if (RVVVectorBitsMin == -1U)

189 return ZvlLen;

190

191

192

193 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)

195 "than the Zvl*b limitation");

196

197 return RVVVectorBitsMin;

198}

199

202 "Tried to get vector length without Zve or V extension support!");

205 "V extension requires a LMUL to be at most 8 and a power of 2!");

207}

208

213

215

217 return getSchedModel().hasInstrSchedModel();

218}

219

220

221

223

227 : TuneInfo->MinimumJumpTableEntries;

228}

229

232

233

236

237

238

240

241

242

244}

245

260

264

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))

This file describes how to lower LLVM calls to machine code calls.

This file declares the targeting of the Machinelegalizer class for RISC-V.

static cl::opt< bool > EnablePExtCodeGen("enable-p-ext-codegen", cl::desc("Turn on P Extension codegen(This is a temporary switch where " "only partial codegen is currently supported)"), cl::init(false), cl::Hidden)

static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)

static cl::opt< bool > UseAA("riscv-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))

static cl::opt< bool > UseMIPSCCMovInsn("use-riscv-mips-ccmov", cl::desc("Use 'mips.ccmov' instruction"), cl::init(true), cl::Hidden)

static cl::opt< unsigned > RISCVMinimumJumpTableEntries("riscv-min-jump-table-entries", cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on RISCV"))

static cl::opt< bool > UseMIPSLoadStorePairsOpt("use-riscv-mips-load-store-pairs", cl::desc("Enable the load/store pair optimization pass"), cl::init(false), cl::Hidden)

static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)

static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)

This class provides the information for the target register banks.

unsigned getMinimumJumpTableEntries() const

Definition RISCVSubtarget.cpp:224

const LegalizerInfo * getLegalizerInfo() const override

Definition RISCVSubtarget.cpp:140

void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Definition RISCVSubtarget.cpp:230

std::unique_ptr< LegalizerInfo > Legalizer

unsigned getMaxLMULForFixedLengthVectors() const

Definition RISCVSubtarget.cpp:200

bool useMIPSLoadStorePairs() const

Definition RISCVSubtarget.cpp:261

bool useRVVForFixedLengthVectors() const

Definition RISCVSubtarget.cpp:209

MISched::Direction getPostRASchedDirection() const

unsigned getMinRVVVectorSizeInBits() const

Definition RISCVSubtarget.cpp:184

std::unique_ptr< InstructionSelector > InstSelector

RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)

Definition RISCVSubtarget.cpp:106

bool useMIPSCCMovInsn() const

Definition RISCVSubtarget.cpp:265

const RISCVRegisterBankInfo * getRegBankInfo() const override

Definition RISCVSubtarget.cpp:146

const CallLowering * getCallLowering() const override

Definition RISCVSubtarget.cpp:125

InstructionSelector * getInstructionSelector() const override

Definition RISCVSubtarget.cpp:131

unsigned getMaxBuildIntsCost() const

Definition RISCVSubtarget.cpp:160

std::unique_ptr< const SelectionDAGTargetInfo > TSInfo

bool hasVInstructions() const

bool useAA() const override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...

Definition RISCVSubtarget.cpp:222

bool enableMachinePipeliner() const override

Definition RISCVSubtarget.cpp:216

bool useConstantPoolForLargeInts() const

Definition RISCVSubtarget.cpp:152

~RISCVSubtarget() override

unsigned getMaxRVVVectorSizeInBits() const

Definition RISCVSubtarget.cpp:171

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

std::unique_ptr< RISCVRegisterBankInfo > RegBankInfo

std::unique_ptr< CallLowering > CallLoweringInfo

const RISCVTargetLowering * getTargetLowering() const override

bool enablePExtCodeGen() const

Definition RISCVSubtarget.cpp:156

void overridePostRASchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Definition RISCVSubtarget.cpp:246

bool enableSubRegLiveness() const override

Definition RISCVSubtarget.cpp:214

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

Definition RISCVSubtarget.cpp:121

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

Primary interface to the complete machine description for the target machine.

Triple - Helper class for working with autoconf configuration names.

ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)

void validate(const Triple &TT, const FeatureBitset &FeatureBits)

Definition RISCVSubtarget.cpp:34

static constexpr unsigned RVVBitsPerBlock

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, const RISCVSubtarget &Subtarget, const RISCVRegisterBankInfo &RBI)

constexpr bool has_single_bit(T Value) noexcept

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

T bit_floor(T Value)

Returns the largest integral power of two no greater than Value if Value is nonzero.

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

bool DisableLatencyHeuristic

A region of an MBB for scheduling.