LLVM: lib/Target/Sparc/SparcISelLowering.cpp Source File (original) (raw)
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40using namespace llvm;
41
42
43
44
45
46
50{
52
53
55 0,
56 LocVT, LocInfo));
57 return true;
58}
59
63{
64 static const MCPhysReg RegList[] = {
65 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
66 };
67
68 if (Register Reg = State.AllocateReg(RegList)) {
70 } else {
71
73 ValNo, ValVT, State.AllocateStack(8, Align(4)), LocVT, LocInfo));
74 return true;
75 }
76
77
78 if (Register Reg = State.AllocateReg(RegList))
80 else
82 ValNo, ValVT, State.AllocateStack(4, Align(4)), LocVT, LocInfo));
83 return true;
84}
85
89{
90 static const MCPhysReg RegList[] = {
91 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
92 };
93
94
95 if (Register Reg = State.AllocateReg(RegList))
97 else
98 return false;
99
100
101 if (Register Reg = State.AllocateReg(RegList))
103 else
104 return false;
105
106 return true;
107}
108
109
113 assert((LocVT == MVT::f32 || LocVT == MVT::f128
115 "Can't handle non-64 bits locations");
116
117
118 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
119 Align alignment =
120 (LocVT == MVT::f128 || ArgFlags.isSplit()) ? Align(16) : Align(8);
121 unsigned Offset = State.AllocateStack(size, alignment);
122 unsigned Reg = 0;
123
124 if (LocVT == MVT::i64 && Offset < 6*8)
125
127 else if (LocVT == MVT::f64 && Offset < 16*8)
128
130 else if (LocVT == MVT::f32 && Offset < 16*8)
131
133 else if (LocVT == MVT::f128 && Offset < 16*8)
134
136
137
138 if (Reg) {
140 return true;
141 }
142
143
144
145 if (IsReturn)
146 return false;
147
148
149
150
151 if (LocVT == MVT::f32)
153
155 return true;
156}
157
158
159
160
164 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
165 unsigned Offset = State.AllocateStack(4, Align(4));
166
167 if (LocVT == MVT::f32 && Offset < 16*8) {
168
170 LocVT, LocInfo));
171 return true;
172 }
173
174 if (LocVT == MVT::i32 && Offset < 6*8) {
175
176 unsigned Reg = SP::I0 + Offset/8;
177 LocVT = MVT::i64;
179
180
183 LocVT, LocInfo));
184 else
186 return true;
187 }
188
189
190
191 if (IsReturn)
192 return false;
193
195 return true;
196}
197
204
211
218
225
226#include "SparcGenCallingConv.inc"
227
228
229
230
232 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
233 "Unexpected enum");
234 if (Reg >= SP::I0 && Reg <= SP::I7)
235 return Reg - SP::I0 + SP::O0;
236 return Reg;
237}
238
242 const Type *RetTy) const {
244 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
245 return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
246 : RetCC_Sparc32);
247}
248
251 bool IsVarArg,
255 if (Subtarget->is64Bit())
256 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
257 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
258}
259
262 bool IsVarArg,
267
268
270
271
274
275
277
280
282
283
284 for (unsigned i = 0, realRVLocIdx = 0;
285 i != RVLocs.size();
286 ++i, ++realRVLocIdx) {
288 assert(VA.isRegLoc() && "Can only return in registers!");
289
290 SDValue Arg = OutVals[realRVLocIdx];
291
294
295
296
298 Arg,
301 Arg,
303
307 VA = RVLocs[++i];
309 Glue);
310 } else
312
313
316 }
317
318 unsigned RetAddrOffset = 8;
319
323 if (!Reg)
324 llvm_unreachable("sret virtual register not created in the entry block");
327 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Glue);
330 RetAddrOffset = 12;
331 }
332
333 RetOps[0] = Chain;
334 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
335
336
339
340 return DAG.getNode(SPISD::RET_GLUE, DL, MVT::Other, RetOps);
341}
342
343
344
347 bool IsVarArg,
351
353
354
357
358
360
363
364
365
367
368
369 for (unsigned i = 0; i != RVLocs.size(); ++i) {
371 assert(VA.isRegLoc() && "Can only return in registers!");
372 SDValue OutVal = OutVals[i];
373
374
379 break;
382 break;
385 break;
386 default:
388 }
389
390
391
395
396
397
398 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
401
402 ++i;
403 }
404 }
405
407
408
411 }
412
413 RetOps[0] = Chain;
414
415
418
419 return DAG.getNode(SPISD::RET_GLUE, DL, MVT::Other, RetOps);
420}
421
426 if (Subtarget->is64Bit())
428 DL, DAG, InVals);
430 DL, DAG, InVals);
431}
432
433
434
435
444
445
450
453
454 unsigned InIdx = 0;
455 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
458
459 if (Ins[InIdx].Flags.isSRet()) {
460 if (InIdx != 0)
461 report_fatal_error("sparc only supports sret on the first parameter");
462
468 continue;
469 }
470
475
476 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
479
482
489 } else {
491 &SP::IntRegsRegClass);
492 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
493 }
494
495 if (IsLittleEndian)
497
500 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
502 continue;
503 }
504 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
508 if (VA.getLocVT() == MVT::f32)
509 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
510 else if (VA.getLocVT() != MVT::i32) {
514 }
516 continue;
517 }
518 } else {
520
522
525
526 if (Offset % 8 == 0) {
532 continue;
533 }
534
541
544
545 if (IsLittleEndian)
547
550 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
552 continue;
553 }
554
562 continue;
563 }
564 Arg = Load;
565 }
566
568
572
573 unsigned ArgIndex = Ins[InIdx].OrigArgIndex;
574 assert(Ins[InIdx].PartOffset == 0);
575 while (i + 1 != e && Ins[InIdx + 1].OrigArgIndex == ArgIndex) {
577 unsigned PartOffset = Ins[InIdx + 1].PartOffset;
582 ++i;
583 ++InIdx;
584 }
585 }
586
588
591 if (!Reg) {
594 }
597 }
598
599
600 if (isVarArg) {
601 static const MCPhysReg ArgRegs[] = {
602 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
603 };
605 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
607 if (NumAllocated == 6)
609 else {
611 ArgOffset = 68+4*NumAllocated;
612 }
613
614
616
617 std::vector OutChains;
618
619 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
620 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
623
625 true);
627
628 OutChains.push_back(
630 ArgOffset += 4;
631 }
632
633 if (!OutChains.empty()) {
634 OutChains.push_back(Chain);
636 }
637 }
638
639 return Chain;
640}
641
642
648
649
654
655
656 const unsigned ArgArea = 128;
657
659 if (VA.isRegLoc()) {
660
661
662
663
667
668
669 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
672
673
674
675 switch (VA.getLocInfo()) {
679 break;
683 break;
684 default:
685 break;
686 }
687
688
689 if (VA.isExtInLoc())
691
693 continue;
694 }
695
696
697 assert(VA.isMemLoc());
698
699
700 unsigned Offset = VA.getLocMemOffset() + ArgArea;
701 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
702
703
704
705 if (VA.isExtInLoc())
706 Offset += 8 - ValSize;
709 DAG.getLoad(VA.getValVT(), DL, Chain,
712 }
713
714 if (!IsVarArg)
715 return Chain;
716
717
718
719
720
721
722
723
726
728 Subtarget->getStackPointerBias());
729
730
731
732
734 for (; ArgOffset < 6*8; ArgOffset += 8) {
735 Register VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
742 }
743
744 if (!OutChains.empty())
746
747 return Chain;
748}
749
750
753
754
755
756 bool Outgoing =
758 return TRI->isReservedReg(MF, r);
759 });
762 return TRI->isReservedReg(MF, r);
763 });
765}
766
770 F, ("SPARC doesn't support"
771 " function calls if any of the argument registers is reserved.")});
772}
773
777 if (Subtarget->is64Bit())
780}
781
785 return Call->hasFnAttr(Attribute::ReturnsTwice);
786
787 const Function *CalleeFn = nullptr;
794 const char *CalleeName = E->getSymbol();
796 }
797
798 if (!CalleeFn)
799 return false;
800 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
801}
802
803
804
807
808 auto &Outs = CLI.Outs;
810
811
812 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
813 return false;
814
815
816
817
818 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
820 return false;
821
822
823
824 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
825 return false;
826
827
828
829 for (auto &Arg : Outs)
830 if (Arg.Flags.isByVal())
831 return false;
832
833 return true;
834}
835
836
849 bool isVarArg = CLI.IsVarArg;
853
854
859
862
863
865
866
867 ArgsSize = (ArgsSize+7) & ~7;
868
870
871
873 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
875 if (!Flags.isByVal())
876 continue;
877
878 SDValue Arg = OutVals[i];
879 unsigned Size = Flags.getByValSize();
880 Align Alignment = Flags.getNonZeroByValAlign();
881
882 if (Size > 0U) {
886
887 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
888 false,
889 (Size <= 32),
893 }
894 else {
897 }
898 }
899
900 assert(!isTailCall || ArgsSize == 0);
901
902 if (!isTailCall)
904
907
909 bool hasStructRetAttr = false;
910 unsigned SRetArgSize = 0;
911
912 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
913 i != e;
914 ++i, ++realArgIdx) {
916 SDValue Arg = OutVals[realArgIdx];
917
919
920
921 if (Flags.isByVal()) {
922 Arg = ByValArgs[byvalArgIdx++];
923 if (!Arg) {
924 continue;
925 }
926 }
927
928
933 break;
936 break;
939 break;
942 break;
945 break;
946 }
947
948 if (Flags.isSRet()) {
950
951 if (isTailCall)
952 continue;
953
954
957 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
960 hasStructRetAttr = true;
961
962 assert(Outs[realArgIdx].OrigArgIndex == 0);
963 SRetArgSize =
965 continue;
966 }
967
970
973
974 if (Offset % 8 == 0) {
977 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
980 continue;
981 }
982 }
983
984 if (VA.getLocVT() == MVT::f64) {
985
986
989 else
990 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
991 }
992
994 Arg,
997 Arg,
999
1006 } else {
1007
1011 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1014 }
1015 } else {
1017
1020 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1023
1025 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1028 }
1029 continue;
1030 }
1031
1033
1034 unsigned ArgIndex = Outs[realArgIdx].OrigArgIndex;
1035 assert(Outs[realArgIdx].PartOffset == 0);
1036
1037 EVT SlotVT;
1038 if (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1039 Type *OrigArgType = CLI.Args[ArgIndex].Ty;
1041 MVT PartVT =
1043 unsigned N =
1046 } else {
1047 SlotVT = Outs[realArgIdx].VT;
1048 }
1049
1053 DAG.getStore(Chain, dl, Arg, SpillSlot,
1055
1056
1057 while (i + 1 != e && Outs[realArgIdx + 1].OrigArgIndex == ArgIndex) {
1058 SDValue PartValue = OutVals[realArgIdx + 1];
1059 unsigned PartOffset = Outs[realArgIdx + 1].PartOffset;
1067 "Not enough space for argument part!");
1068 ++i;
1069 ++realArgIdx;
1070 }
1071
1072 Arg = SpillSlot;
1073 }
1074
1075
1076
1078 if (VA.getLocVT() != MVT::f32) {
1080 continue;
1081 }
1082 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1084 continue;
1085 }
1086
1088
1089
1092 dl);
1093 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1096 }
1097
1098
1099
1100 if (!MemOpChains.empty())
1102
1103
1104
1105
1106
1108 for (const auto &[OrigReg, N] : RegsToPass) {
1110 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue);
1112 }
1113
1115
1116
1117
1118
1123
1124
1127 Ops.push_back(Chain);
1128 Ops.push_back(Callee);
1129 if (hasStructRetAttr)
1131 for (const auto &[OrigReg, N] : RegsToPass) {
1134 }
1135
1136
1139 ((hasReturnsTwice)
1140 ? TRI->getRTCallPreservedMask(CallConv)
1142
1145
1146 assert(Mask && "Missing call preserved mask for calling convention");
1148
1150 Ops.push_back(InGlue);
1151
1152 if (isTailCall) {
1154 return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops);
1155 }
1156
1157 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
1159
1160 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, dl);
1162
1163
1167
1169
1170
1171 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1172 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1173 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1176 Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InGlue);
1177 Chain = Lo.getValue(1);
1178 InGlue = Lo.getValue(2);
1182 Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InGlue);
1183 Chain = Hi.getValue(1);
1184 InGlue = Hi.getValue(2);
1188 } else {
1189 Chain =
1191 RVLocs[i].getValVT(), InGlue)
1195 }
1196 }
1197
1198 return Chain;
1199}
1200
1201
1202
1206 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1207 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1208 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1209 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1210 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1211 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1212 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1213 .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1215
1216
1217
1218
1220 if (->isReservedReg(MF, Reg))
1222
1223 return Reg;
1224}
1225
1226
1227
1228
1229
1230
1231
1232
1233
1237 MVT ValTy = VA.getLocVT();
1238
1239
1240 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1241 continue;
1242
1243 if (!Outs[VA.getValNo()].Flags.isVarArg())
1244 continue;
1245
1246
1247
1248 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1249 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1250 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1251 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1252
1254
1255 unsigned IReg = SP::I0 + Offset/8;
1256 if (ValTy == MVT::f64)
1257
1260 else {
1261 assert(ValTy == MVT::f128 && "Unexpected type!");
1262
1263
1266 }
1267 } else {
1268
1270 VA.getLocVT(), VA.getLocInfo());
1271 }
1272 }
1273}
1274
1275
1284
1285
1290
1293
1294
1295
1296
1297
1298 unsigned StackReserved = 6 * 8u;
1299 unsigned ArgsSize = std::max(StackReserved, CCInfo.getStackSize());
1300
1301
1302 ArgsSize = alignTo(ArgsSize, 16);
1303
1304
1307
1309
1310
1311
1312
1315
1316
1317
1318
1320
1321
1322
1323
1325
1326 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1329
1330
1332 default:
1335 break;
1338 break;
1341 break;
1344 break;
1346
1347
1349 || VA.getLocVT() != MVT::i128)
1351 break;
1352 }
1353
1356 && VA.getLocVT() == MVT::i128) {
1357
1359 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1362 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1364 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1365
1366
1369
1374
1380 }
1381
1382 RegsToPass.push_back(std::make_pair(HiReg, Hi64));
1383 RegsToPass.push_back(std::make_pair(LoReg, Lo64));
1384 continue;
1385 }
1386
1387
1388
1392
1393
1394
1395 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1396 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1400
1401 ++i;
1402 }
1403 }
1404
1408 RegsToPass.push_back(std::make_pair(Reg, Arg));
1409 continue;
1410 }
1411
1413
1414
1416
1417
1419 Subtarget->getStackPointerBias() +
1420 128, DL);
1424 }
1425
1426
1427 if (!MemOpChains.empty())
1429
1430
1431
1432
1433
1435 for (const auto &[Reg, N] : RegsToPass) {
1438 }
1439
1440
1441
1442
1449
1450
1452 Ops.push_back(Chain);
1453 Ops.push_back(Callee);
1454 for (const auto &[Reg, N] : RegsToPass)
1456
1457
1460 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1463
1466
1467 assert(Mask && "Missing call preserved mask for calling convention");
1469
1470
1471
1473 Ops.push_back(InGlue);
1474
1475
1478 return DAG.getNode(SPISD::TAIL_CALL, DL, MVT::Other, Ops);
1479 }
1481 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1483
1484
1487
1488
1489
1490
1491
1495
1496
1497
1498 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1499 CLI.Ins[0].Flags.setInReg();
1500
1502
1503
1504 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1506 assert(VA.isRegLoc() && "Can only return in registers!");
1508
1509
1510
1511
1516
1517
1519 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1522 }
1523
1524
1528
1529
1530
1535 break;
1539 break;
1540 default:
1541 break;
1542 }
1543
1544
1547
1549 }
1550
1551 return Chain;
1552}
1553
1554
1555
1556
1557
1565
1566
1567
1569 switch (CC) {
1570 default:
1571 llvm_unreachable("Unknown/unsigned integer condition code!");
1584 }
1585}
1586
1587
1588
1590 switch (CC) {
1591 default: llvm_unreachable("Unknown integer condition code!");
1602 }
1603}
1604
1605
1606
1608 switch (CC) {
1630 }
1631}
1632
1637
1638
1639
1640
1641
1642
1645
1646
1648 if (!Subtarget->useSoftFloat()) {
1652 }
1653 if (Subtarget->is64Bit()) {
1655 } else {
1656
1657
1659
1660
1661
1664 }
1665
1670
1674
1677 }
1678
1683
1684
1687
1688
1689
1690
1691 }
1692
1693
1698 }
1699
1700
1703
1704
1711
1712
1717
1718
1722
1723
1728
1729
1730 if (Subtarget->is64Bit()) {
1735 }
1736
1737
1742
1743
1748
1749
1756
1761
1762
1767
1772
1773
1781
1786
1791
1792 if (Subtarget->isVIS3()) {
1795 }
1796
1797 if (Subtarget->is64Bit()) {
1806
1813 }
1814
1815
1816
1817
1818
1819 if (Subtarget->isV9()) {
1820
1821
1822 if (Subtarget->is64Bit())
1824 else
1826 } else if (Subtarget->hasLeonCasa())
1828 else
1830
1832
1834
1836
1837
1840
1841 if (Subtarget->is64Bit()) {
1846 }
1847
1848 if (!Subtarget->isV9()) {
1849
1852 }
1853
1864 Subtarget->isUA2007() ? Legal : Expand);
1870 Subtarget->isUA2007() ? Legal : Expand);
1880
1884
1885
1889
1890 if (Subtarget->useSoftMulDiv()) {
1891
1896 }
1897
1898 if (Subtarget->is64Bit()) {
1905
1909 }
1910
1911
1913
1915
1918
1919
1925
1927
1930
1931 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1934 } else {
1937 }
1938
1939 if (Subtarget->hasHardQuad()) {
1947 if (Subtarget->isV9()) {
1950 } else {
1953 }
1954 } else {
1955
1956
1964
1968 }
1969
1970 if (Subtarget->fixAllFDIVSQRT()) {
1971
1972
1975 }
1976
1977 if (Subtarget->hasNoFMULS()) {
1979 }
1980
1981
1982 if (!Subtarget->is64Bit())
1984
1985 if (Subtarget->hasLeonCycleCounter())
1987
1988 if (Subtarget->isVIS3()) {
1993
2000 } else if (Subtarget->usePopc()) {
2005
2010 } else {
2016
2017
2018
2023 }
2024
2026
2027
2028
2029
2031
2032
2034
2036
2038}
2039
2041 return Subtarget->useSoftFloat();
2042}
2043
2045 EVT VT) const {
2047 return MVT::i32;
2049}
2050
2051
2052
2053
2057 const APInt &DemandedElts,
2059 unsigned Depth) const {
2062
2063 switch (Op.getOpcode()) {
2064 default: break;
2065 case SPISD::SELECT_ICC:
2066 case SPISD::SELECT_XCC:
2067 case SPISD::SELECT_FCC:
2070
2071
2073 break;
2074 }
2075}
2076
2077
2078
2082 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2083 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2084 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
2085 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2086 (LHS.getOperand(3).getOpcode() == SPISD::CMPFCC ||
2087 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC_V9))) &&
2090 SPCC = LHS.getConstantOperandVal(2);
2093 }
2094}
2095
2096
2102 GA->getValueType(0),
2103 GA->getOffset(), TF);
2104
2107 CP->getAlign(), CP->getOffset(), TF);
2108
2111 Op.getValueType(),
2112 0,
2113 TF);
2114
2117 ES->getValueType(0), TF);
2118
2120}
2121
2122
2123
2125 unsigned HiTF, unsigned LoTF,
2128 EVT VT = Op.getValueType();
2132}
2133
2134
2135
2139
2140
2145
2147
2148 Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
2150 } else {
2151
2152 Idx = makeHiLoPair(Op, ELF::R_SPARC_GOT22, ELF::R_SPARC_GOT10, DAG);
2153 }
2154
2155 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
2157
2158
2163 }
2164
2165
2167 default:
2170
2171 return makeHiLoPair(Op, ELF::R_SPARC_HI22, ELF::R_SPARC_LO10, DAG);
2173
2177 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
2179 }
2181
2186 }
2187 }
2188}
2189
2194
2199
2204
2207
2211
2215
2217
2219 unsigned HiTF =
2221 : ELF::R_SPARC_TLS_LDM_HI22);
2222 unsigned LoTF =
2224 : ELF::R_SPARC_TLS_LDM_LO10);
2225 unsigned addTF =
2227 : ELF::R_SPARC_TLS_LDM_ADD);
2228 unsigned callTF =
2230 : ELF::R_SPARC_TLS_LDM_CALL);
2231
2236
2239
2245
2247 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2249 assert(Mask && "Missing call preserved mask for calling convention");
2251 Callee,
2252 Symbol,
2255 InGlue};
2256 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2261
2263 return Ret;
2264
2266 DAG.getNode(SPISD::Hi, DL, PtrVT,
2269 DAG.getNode(SPISD::Lo, DL, PtrVT,
2272 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2274 }
2275
2277 unsigned ldTF = ((PtrVT == MVT::i64) ? ELF::R_SPARC_TLS_IE_LDX
2278 : ELF::R_SPARC_TLS_IE_LD);
2279
2281
2282
2283
2286
2288 ELF::R_SPARC_TLS_IE_LO10, DAG);
2291 DL, PtrVT, Ptr,
2293 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2296 }
2297
2304
2307}
2308
2316
2318
2323 } else {
2324 Args.emplace_back(Arg, ArgTy);
2325 }
2326 return Chain;
2327}
2328
2331 const char *LibFuncName,
2332 unsigned numArgs) const {
2333
2335
2338
2340 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2341 Type *RetTyABI = RetTy;
2344
2346
2350 if (!Subtarget->is64Bit()) {
2351 Entry.IsSRet = true;
2352 Entry.IndirectType = RetTy;
2353 }
2354 Entry.IsReturned = false;
2355 Args.push_back(Entry);
2357 }
2358
2359 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2360 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2362 }
2366
2368
2369
2370 if (RetTyABI == RetTy)
2372
2373 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2374
2376
2377
2378 return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
2380}
2381
2385
2386 const char *LibCall = nullptr;
2387 bool is64Bit = Subtarget->is64Bit();
2388 switch(SPCC) {
2404 }
2405
2413
2417
2419
2420
2422
2423 switch(SPCC) {
2424 default: {
2427 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2428 }
2431 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2434 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2435 }
2439 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2440 }
2444 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2445 }
2449 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2450 }
2451
2455 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2456 }
2460 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2461 }
2464 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2467 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2468 }
2471 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2474 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2475 }
2476 }
2477}
2478
2482
2483 if (Op.getOperand(0).getValueType() == MVT::f64)
2486
2487 if (Op.getOperand(0).getValueType() == MVT::f32)
2490
2493}
2494
2498
2499 if (Op.getOperand(0).getValueType() != MVT::f128)
2500 return Op;
2501
2502 if (Op.getValueType() == MVT::f64)
2505 if (Op.getValueType() == MVT::f32)
2508
2511}
2512
2515 bool hasHardQuad) {
2517 EVT VT = Op.getValueType();
2518 assert(VT == MVT::i32 || VT == MVT::i64);
2519
2520
2521 if (Op.getOperand(0).getValueType() == MVT::f128
2522 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2523 const char *libName = TLI.getLibcallName(VT == MVT::i32
2524 ? RTLIB::FPTOSINT_F128_I32
2525 : RTLIB::FPTOSINT_F128_I64);
2527 }
2528
2529
2532
2533
2534 if (VT == MVT::i32)
2535 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2536 else
2537 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2538
2539 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2540}
2541
2544 bool hasHardQuad) {
2546 EVT OpVT = Op.getOperand(0).getValueType();
2547 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2548
2549 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2550
2551
2552 if (Op.getValueType() == MVT::f128
2553 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2554 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2555 ? RTLIB::SINTTOFP_I32_F128
2556 : RTLIB::SINTTOFP_I64_F128);
2558 }
2559
2560
2563
2564
2565 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2566 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2567 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2568}
2569
2572 bool hasHardQuad) {
2573 EVT VT = Op.getValueType();
2574
2575
2576
2577 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2580
2581 assert(VT == MVT::i32 || VT == MVT::i64);
2582
2585 ? RTLIB::FPTOUINT_F128_I32
2586 : RTLIB::FPTOUINT_F128_I64),
2587 1);
2588}
2589
2592 bool hasHardQuad) {
2593 EVT OpVT = Op.getOperand(0).getValueType();
2594 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2595
2596
2597
2598 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2600
2603 ? RTLIB::UINTTOFP_I32_F128
2604 : RTLIB::UINTTOFP_I64_F128),
2605 1);
2606}
2607
2610 bool isV9, bool is64Bit) {
2611 SDValue Chain = Op.getOperand(0);
2615 SDValue Dest = Op.getOperand(4);
2617 unsigned Opc, SPCC = ~0U;
2618
2619
2620
2622 assert(LHS.getValueType() == RHS.getValueType());
2623
2624
2626 if (LHS.getValueType().isInteger()) {
2627
2628
2629 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2631 return DAG.getNode(SPISD::BR_REG, dl, MVT::Other, Chain, Dest,
2634
2635 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2637 if (isV9)
2638
2639 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2640 else
2641
2642 Opc = SPISD::BRICC;
2643 } else {
2644 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2647 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2648 } else {
2649 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2650 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2652 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2653 }
2654 }
2655 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2657}
2658
2661 bool isV9, bool is64Bit) {
2665 SDValue TrueVal = Op.getOperand(2);
2666 SDValue FalseVal = Op.getOperand(3);
2668 unsigned Opc, SPCC = ~0U;
2669
2670
2671
2673 assert(LHS.getValueType() == RHS.getValueType());
2674
2676 if (LHS.getValueType().isInteger()) {
2677
2678
2679
2680
2681
2682
2683 EVT ValType = TrueVal.getValueType();
2684 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2685 ValType == MVT::f64 ||
2686 (ValType == MVT::f128 && hasHardQuad);
2687 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2690 SPISD::SELECT_REG, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2692
2693 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2694 Opc = LHS.getValueType() == MVT::i32 ?
2695 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2697 } else {
2698 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2701 Opc = SPISD::SELECT_ICC;
2702 } else {
2703 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2704 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2705 Opc = SPISD::SELECT_FCC;
2707 }
2708 }
2709 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2711}
2712
2718
2719
2721
2722
2723
2731}
2732
2735 EVT VT = Node->getValueType(0);
2737 SDValue VAListPtr = Node->getOperand(1);
2743
2746 DL));
2747
2750
2751
2755}
2756
2759 SDValue Chain = Op.getOperand(0);
2761 SDValue Alignment = Op.getOperand(2);
2764 EVT VT = Size->getValueType(0);
2766
2767 unsigned SPReg = SP::O6;
2769
2770
2771
2772 unsigned regSpillArea;
2773 if (Subtarget->is64Bit()) {
2774 regSpillArea = 128;
2775 } else {
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2799 regSpillArea = 96;
2800 }
2801
2803
2804
2805
2806
2807
2812
2813 bool IsOveraligned = MaybeAlignment.has_value();
2815 IsOveraligned
2818 : AllocatedPtr;
2819
2820
2822 DAG.getConstant(regSpillArea + Bias, dl, VT));
2824 SDValue Ops[2] = {AlignedPtr, Chain};
2826}
2827
2828
2835
2838 bool AlwaysFlush = false) {
2841
2842 EVT VT = Op.getValueType();
2844 unsigned FrameReg = SP::I6;
2846
2849
2850
2852
2853 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2854
2855 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2856
2857 while (depth--) {
2861 }
2862 if (Subtarget->is64Bit())
2865 return FrameAddr;
2866}
2867
2868
2871
2872 uint64_t depth = Op.getConstantOperandVal(0);
2873
2875
2876}
2877
2884
2885 EVT VT = Op.getValueType();
2887 uint64_t depth = Op.getConstantOperandVal(0);
2888
2890 if (depth == 0) {
2894 return RetAddr;
2895 }
2896
2897
2899
2900 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2902 dl, VT,
2903 FrameAddr,
2906
2907 return RetAddr;
2908}
2909
2911 unsigned opcode) {
2912 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2913 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2925 SrcReg64);
2927 SrcReg64);
2928
2930 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2931 else
2932 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2933
2935 dl, MVT::f64), 0);
2937 DstReg64, Hi32);
2939 DstReg64, Lo32);
2940 return DstReg64;
2941}
2942
2943
2945{
2949
2951
2961 Alignment);
2962
2965
2967 dl, MVT::f128);
2968 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2969 MVT::f128,
2971 Hi64,
2972 SubRegEven);
2973 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2974 MVT::f128,
2976 Lo64,
2977 SubRegOdd);
2983}
2984
2986{
2988
2990 if (MemVT == MVT::f128)
2992
2993 return Op;
2994}
2995
2996
3001
3004
3006 dl,
3007 MVT::f64,
3009 SubRegEven);
3011 dl,
3012 MVT::f64,
3014 SubRegOdd);
3015
3017
3019 OutChains[0] =
3022 Alignment);
3029 Alignment);
3031}
3032
3034{
3037
3039 if (MemVT == MVT::f128)
3041
3042 if (MemVT == MVT::i64) {
3043
3044
3049 return Chain;
3050 }
3051
3053}
3054
3056 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3057 && "invalid opcode");
3058
3060
3061 if (Op.getValueType() == MVT::f64)
3062 return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
3063 if (Op.getValueType() != MVT::f128)
3064 return Op;
3065
3066
3067
3068
3069
3070
3071 SDValue SrcReg128 = Op.getOperand(0);
3073 SrcReg128);
3075 SrcReg128);
3076
3078 if (isV9)
3079 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
3080 else
3081 Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
3082 } else {
3083 if (isV9)
3084 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
3085 else
3086 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
3087 }
3088
3090 dl, MVT::f128), 0);
3092 DstReg128, Hi64);
3094 DstReg128, Lo64);
3095 return DstReg128;
3096}
3097
3100
3102 }
3103
3104
3105 return Op;
3106}
3107
3110 unsigned IntNo = Op.getConstantOperandVal(0);
3111 switch (IntNo) {
3112 default: return SDValue();
3113 case Intrinsic::thread_pointer: {
3116 }
3117 }
3118}
3119
3122
3123 bool hasHardQuad = Subtarget->hasHardQuad();
3124 bool isV9 = Subtarget->isV9();
3125 bool is64Bit = Subtarget->is64Bit();
3126
3127 switch (Op.getOpcode()) {
3129
3131 Subtarget);
3133 Subtarget);
3139 hasHardQuad);
3141 hasHardQuad);
3143 hasHardQuad);
3145 hasHardQuad);
3146 case ISD::BR_CC:
3150 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
3151 case ISD::VAARG: return LowerVAARG(Op, DAG);
3153 Subtarget);
3154
3155 case ISD::LOAD: return LowerLOAD(Op, DAG);
3156 case ISD::STORE: return LowerSTORE(Op, DAG);
3167 case ISD::FABS:
3171 case ISD::ATOMIC_LOAD:
3174 }
3175}
3176
3180 APInt V = C->getValueAPF().bitcastToAPInt();
3186}
3187
3191 SDValue Src = N->getOperand(0);
3192
3194 Src.getSimpleValueType() == MVT::f64)
3196
3198}
3199
3202 switch (N->getOpcode()) {
3203 default:
3204 break;
3205 case ISD::BITCAST:
3207 }
3209}
3210
3214 switch (MI.getOpcode()) {
3216 case SP::SELECT_CC_Int_ICC:
3217 case SP::SELECT_CC_FP_ICC:
3218 case SP::SELECT_CC_DFP_ICC:
3219 case SP::SELECT_CC_QFP_ICC:
3220 if (Subtarget->isV9())
3223 case SP::SELECT_CC_Int_XCC:
3224 case SP::SELECT_CC_FP_XCC:
3225 case SP::SELECT_CC_DFP_XCC:
3226 case SP::SELECT_CC_QFP_XCC:
3228 case SP::SELECT_CC_Int_FCC:
3229 case SP::SELECT_CC_FP_FCC:
3230 case SP::SELECT_CC_DFP_FCC:
3231 case SP::SELECT_CC_QFP_FCC:
3232 if (Subtarget->isV9())
3235 }
3236}
3237
3240 unsigned BROpcode) const {
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3258
3261 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
3263 F->insert(It, IfFalseMBB);
3264 F->insert(It, SinkMBB);
3265
3266
3267 SinkMBB->splice(SinkMBB->begin(), ThisMBB,
3270
3271
3274
3275 BuildMI(ThisMBB, dl, TII.get(BROpcode))
3278
3279
3281
3282
3283 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
3284 MI.getOperand(0).getReg())
3285 .addReg(MI.getOperand(1).getReg())
3287 .addReg(MI.getOperand(2).getReg())
3288 .addMBB(IfFalseMBB);
3289
3290 MI.eraseFromParent();
3291 return SinkMBB;
3292}
3293
3294
3295
3296
3297
3298
3299
3302 if (Constraint.size() == 1) {
3303 switch (Constraint[0]) {
3304 default: break;
3305 case 'r':
3306 case 'f':
3307 case 'e':
3309 case 'I':
3311 }
3312 }
3313
3315}
3316
3319 const char *constraint) const {
3321 Value *CallOperandVal = info.CallOperandVal;
3322
3323
3324 if (!CallOperandVal)
3326
3327
3328 switch (*constraint) {
3329 default:
3331 break;
3332 case 'I':
3336 }
3337 break;
3338 }
3339 return weight;
3340}
3341
3342
3343
3348
3349
3350 if (Constraint.size() > 1)
3351 return;
3352
3353 char ConstraintLetter = Constraint[0];
3354 switch (ConstraintLetter) {
3355 default: break;
3356 case 'I':
3360 Op.getValueType());
3361 break;
3362 }
3363 return;
3364 }
3365 }
3366
3367 if (Result.getNode()) {
3368 Ops.push_back(Result);
3369 return;
3370 }
3372}
3373
3374std::pair<unsigned, const TargetRegisterClass *>
3377 MVT VT) const {
3378 if (Constraint.empty())
3379 return std::make_pair(0U, nullptr);
3380
3381 if (Constraint.size() == 1) {
3382 switch (Constraint[0]) {
3383 case 'r':
3384 if (VT == MVT::v2i32)
3385 return std::make_pair(0U, &SP::IntPairRegClass);
3386 else if (Subtarget->is64Bit())
3387 return std::make_pair(0U, &SP::I64RegsRegClass);
3388 else
3389 return std::make_pair(0U, &SP::IntRegsRegClass);
3390 case 'f':
3391 if (VT == MVT::f32 || VT == MVT::i32)
3392 return std::make_pair(0U, &SP::FPRegsRegClass);
3393 else if (VT == MVT::f64 || VT == MVT::i64)
3394 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3395 else if (VT == MVT::f128)
3396 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3397
3398 return std::make_pair(0U, nullptr);
3399 case 'e':
3400 if (VT == MVT::f32 || VT == MVT::i32)
3401 return std::make_pair(0U, &SP::FPRegsRegClass);
3402 else if (VT == MVT::f64 || VT == MVT::i64 )
3403 return std::make_pair(0U, &SP::DFPRegsRegClass);
3404 else if (VT == MVT::f128)
3405 return std::make_pair(0U, &SP::QFPRegsRegClass);
3406
3407 return std::make_pair(0U, nullptr);
3408 }
3409 }
3410
3411 if (Constraint.front() != '{')
3412 return std::make_pair(0U, nullptr);
3413
3414 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3417 return std::make_pair(0U, nullptr);
3418
3419 unsigned long long RegNo;
3420
3421 if (RegName[0] == 'r' &&
3423
3424
3425
3426
3427 if (RegNo > 31)
3428 return std::make_pair(0U, nullptr);
3429 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3430 char RegType = RegTypes[RegNo / 8];
3431 char RegIndex = '0' + (RegNo % 8);
3432 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3434 }
3435
3436
3437 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3439 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3442 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3445 } else {
3446 return std::make_pair(0U, nullptr);
3447 }
3448 }
3449
3450 auto ResultPair =
3452 if (!ResultPair.second)
3453 return std::make_pair(0U, nullptr);
3454
3455
3456 if (Subtarget->is64Bit() && VT == MVT::i64) {
3457 assert(ResultPair.second == &SP::IntRegsRegClass &&
3458 "Unexpected register class");
3459 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3460 }
3461
3462 return ResultPair;
3463}
3464
3465bool
3467
3468 return false;
3469}
3470
3474
3476
3477 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3478
3479 switch (N->getOpcode()) {
3480 default:
3481 llvm_unreachable("Do not know how to custom type legalize this operation!");
3482
3485
3486 if (N->getOperand(0).getValueType() != MVT::f128
3487 || N->getValueType(0) != MVT::i64)
3488 return;
3490 ? RTLIB::FPTOSINT_F128_I64
3491 : RTLIB::FPTOUINT_F128_I64);
3492
3494 DAG,
3496 1));
3497 return;
3498 case ISD::READCYCLECOUNTER: {
3499 assert(Subtarget->hasLeonCycleCounter());
3504 Results.push_back(Pair);
3505 Results.push_back(N->getOperand(0));
3506 return;
3507 }
3510
3511 if (N->getValueType(0) != MVT::f128
3512 || N->getOperand(0).getValueType() != MVT::i64)
3513 return;
3514
3516 ? RTLIB::SINTTOFP_I64_F128
3517 : RTLIB::UINTTOFP_I64_F128);
3518
3520 DAG,
3522 1));
3523 return;
3524 case ISD::LOAD: {
3526
3527
3529 return;
3530
3536
3537 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3540 return;
3541 }
3542 }
3543}
3544
3545
3547 if (!Subtarget->getTargetTriple().isOSLinux())
3549 return true;
3550}
3551
3553 if (Subtarget->isVIS3())
3554 return VT == MVT::f32 || VT == MVT::f64;
3555 return false;
3556}
3557
3559 bool ForCodeSize) const {
3560 if (VT != MVT::f32 && VT != MVT::f64)
3561 return false;
3562 if (Subtarget->isVIS() && Imm.isZero())
3563 return true;
3564 if (Subtarget->isVIS3())
3565 return Imm.isExactlyValue(+0.5) || Imm.isExactlyValue(-0.5) ||
3566 Imm.getExactLog2Abs() == -1;
3567 return false;
3568}
3569
3571
3573
3574
3575 if (Subtarget->is64Bit() && Subtarget->usePopc())
3576 return true;
3577
3579}
3580
3582 EVT VT) const {
3583 return Subtarget->isUA2007() && !Subtarget->useSoftFloat();
3584}
3585
3588 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3589
3590 if (->hasAnyUseOfValue(0))
3591 MI.getOperand(0).setReg(SP::G0);
3592}
3593
3597 bool HasStoreSemantics =
3601 return nullptr;
3602}
3603
3607
3608
3612
3613
3615 return Builder.CreateFence(Ord);
3616 return nullptr;
3617}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Module.h This file contains the declarations for the Module class.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
static constexpr MCPhysReg SPReg
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Definition SparcISelLowering.cpp:2570
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:86
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Definition SparcISelLowering.cpp:2590
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:60
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush=false)
Definition SparcISelLowering.cpp:2836
static unsigned toCallerWindow(unsigned Reg)
Definition SparcISelLowering.cpp:231
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
Definition SparcISelLowering.cpp:2997
static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC)
intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC rcond condition.
Definition SparcISelLowering.cpp:1568
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
Definition SparcISelLowering.cpp:2985
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
Definition SparcISelLowering.cpp:1234
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Definition SparcISelLowering.cpp:2513
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
Definition SparcISelLowering.cpp:1607
static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI, const MachineFunction &MF)
Definition SparcISelLowering.cpp:751
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
Definition SparcISelLowering.cpp:2829
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call)
Definition SparcISelLowering.cpp:782
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Definition SparcISelLowering.cpp:2757
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Definition SparcISelLowering.cpp:2869
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
Definition SparcISelLowering.cpp:2496
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
Definition SparcISelLowering.cpp:2910
static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:212
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
Definition SparcISelLowering.cpp:2608
static void emitReservedArgRegCallError(const MachineFunction &MF)
Definition SparcISelLowering.cpp:767
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
Definition SparcISelLowering.cpp:3098
static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:219
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
Definition SparcISelLowering.cpp:2659
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
Definition SparcISelLowering.cpp:2480
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
Definition SparcISelLowering.cpp:3055
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Definition SparcISelLowering.cpp:2733
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:205
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:198
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:47
static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:161
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
Definition SparcISelLowering.cpp:2944
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
Definition SparcISelLowering.cpp:2878
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
Definition SparcISelLowering.cpp:2079
static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition SparcISelLowering.cpp:110
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Definition SparcISelLowering.cpp:2542
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
This file describes how to lower LLVM code to machine code.
static bool is64Bit(const char *name)
Class for arbitrary precision integers.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
LLVM_ABI void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
LLVM_ABI bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
LLVM_ABI void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ABI void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
LLVM_ABI void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
int64_t getLocMemOffset() const
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
This is the shared class of boolean and integer constants.
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
LLVM_ABI TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Diagnostic information for unsupported feature in backend.
const Function & getFunction() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
Common base class shared among various IRBuilders.
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
static auto integer_fixedlen_vector_valuetypes()
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
LLVM_ABI void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
LLVM_ABI int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
BasicBlockListType::iterator iterator
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Flags getFlags() const
Return the raw flags of the source value,.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Align getBaseAlign() const
Returns alignment and volatility of the memory access.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
LLVM_ABI SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
LLVM_ABI SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_ABI MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
LLVM_ABI SDValue getRegister(Register Reg, EVT VT)
LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
const DataLayout & getDataLayout() const
LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
LLVM_ABI SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getSignedTargetConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
LLVM_ABI SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
LLVM_ABI SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
LLVM_ABI SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
LLVM_ABI SDValue getValueType(EVT)
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM_ABI KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
LLVM_ABI SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
LLVM_ABI SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
LLVM_ABI SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Register getSRetReturnReg() const
int getVarArgsFrameOffset() const
void setVarArgsFrameOffset(int Offset)
void setSRetReturnReg(Register Reg)
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition SparcISelLowering.cpp:3471
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2097
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition SparcISelLowering.cpp:239
bool useSoftFloat() const override
Definition SparcISelLowering.cpp:2040
SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:3177
MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const
Definition SparcISelLowering.cpp:3239
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition SparcISelLowering.cpp:3558
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition SparcISelLowering.cpp:3318
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition SparcISelLowering.cpp:1558
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition SparcISelLowering.cpp:3375
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
Definition SparcISelLowering.cpp:3570
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition SparcISelLowering.cpp:422
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition SparcISelLowering.cpp:3301
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
Definition SparcISelLowering.cpp:436
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition SparcISelLowering.cpp:775
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition SparcISelLowering.cpp:3572
bool IsEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
Definition SparcISelLowering.cpp:805
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition SparcISelLowering.cpp:3466
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition SparcISelLowering.cpp:3552
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2309
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2124
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2200
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2190
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition SparcISelLowering.cpp:3594
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition SparcISelLowering.cpp:3586
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
Definition SparcISelLowering.cpp:2055
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
Definition SparcISelLowering.cpp:1277
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition SparcISelLowering.cpp:3581
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition SparcISelLowering.cpp:250
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition SparcISelLowering.cpp:3604
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
Definition SparcISelLowering.cpp:2330
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2136
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition SparcISelLowering.cpp:3212
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:3108
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:261
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition SparcISelLowering.cpp:3200
SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition SparcISelLowering.cpp:3188
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:346
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2205
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition SparcISelLowering.cpp:2044
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
Definition SparcISelLowering.cpp:838
bool useLoadStackGuardNode(const Module &M) const override
Override to support customized stack guard loading.
Definition SparcISelLowering.cpp:3546
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition SparcISelLowering.cpp:3121
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2195
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
Definition SparcISelLowering.cpp:643
SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI)
Definition SparcISelLowering.cpp:1633
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition SparcISelLowering.cpp:3344
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition SparcISelLowering.cpp:1203
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const
Definition SparcISelLowering.cpp:2382
StackOffset holds a fixed and a scalable offset in bytes.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
char back() const
back - Get the last character in the string.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
TargetLowering(const TargetLowering &)=delete
virtual bool useLoadStackGuardNode(const Module &M) const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Primary interface to the complete machine description for the target machine.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
static LLVM_ABI Type * getVoidTy(LLVMContext &C)
bool isFP128Ty() const
Return true if this is 'fp128'.
LLVM_ABI TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ UNDEF
UNDEF - An undefined node.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
LLVM_ABI bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
decltype(auto) dyn_cast(const From &Val)
dyn_cast - Return the argument parameter cast to the specified type.
bool isStrongerThanMonotonic(AtomicOrdering AO)
std::string utostr(uint64_t X, bool isNeg=false)
bool isReleaseOrStronger(AtomicOrdering AO)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
bool isa(const From &Val)
isa - Return true if the parameter to the template is an instance of one of the template type argu...
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
bool isAcquireOrStronger(AtomicOrdering AO)
decltype(auto) cast(const From &Val)
cast - Return the argument parameter cast to the specified type.
LLVM_ABI bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
LLVM_ABI bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isVector() const
Return true if this is a vector value type.
LLVM_ABI Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Incoming for lane maks phi as machine instruction, incoming register Reg and incoming block Block are...
void resetAll()
Resets the known state of all bits.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
This class contains a discriminated union of information about pointers in memory operands,...
MachinePointerInfo getWithOffset(int64_t O) const
static LLVM_ABI MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})