TargetSubtargetInfo.h Source File (original) (raw)

13#ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H

14#define LLVM_CODEGEN_TARGETSUBTARGETINFO_H

25#include

26#include

28namespace llvm {

30class APInt;

31class MachineFunction;

32class ScheduleDAGMutation;

33class CallLowering;

34class GlobalValue;

35class InlineAsmLowering;

36class InstrItineraryData;

37struct InstrStage;

38class InstructionSelector;

39class LegalizerInfo;

40class MachineInstr;

41struct MachineSchedPolicy;

42struct MCReadAdvanceEntry;

43struct MCWriteLatencyEntry;

44struct MCWriteProcResEntry;

45class RegisterBankInfo;

46class SDep;

47class SelectionDAGTargetInfo;

48class SUnit;

49class TargetFrameLowering;

50class TargetInstrInfo;

51class TargetLowering;

52class TargetRegisterClass;

53class TargetRegisterInfo;

54class TargetSchedModel;

55class Triple;

64protected:

72 const unsigned *OC, const unsigned *FP);

74public:

77 using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };

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234 unsigned NumRegionInstrs) const {}

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252 int UseOpIdx, SDep &Dep,

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355};

356}

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358#endif

SI optimize exec mask operations pre RA

This file defines the SmallVector class.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Itinerary data supplied by a subtarget to be used by a target.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

Representation of each machine instruction.

Holds all the information related to register banks.

ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOptLevel) FunctionPassCtor

Wrapper class representing virtual and physical registers.

Scheduling unit. This is a node in the scheduling DAG.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

Information about stack frame layout on the target.

TargetInstrInfo - Interface to description of machine instruction set.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const

Classify a global function reference.

virtual bool requiresDisjointEarlyClobberAndUndef() const

Whether the target has instructions where an early-clobber result operand cannot overlap with an unde...

virtual bool enableJoinGlobalCopies() const

True if the subtarget should enable joining global copies.

~TargetSubtargetInfo() override

virtual bool enableIndirectBrExpand() const

True if the subtarget should run the indirectbr expansion pass.

enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode

virtual std::vector< MacroFusionPredTy > getMacroFusions() const

Get the list of MacroFusion predicates.

virtual bool enableRALocalReassignment(CodeGenOptLevel OptLevel) const

True if the subtarget should run the local reassignment heuristic of the register allocator.

virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const

virtual const InlineAsmLowering * getInlineAsmLowering() const

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual bool isRegisterReservedByUser(Register R) const

virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const

Return PBQPConstraint(s) for the target.

virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const

virtual bool enableMachineScheduler() const

True if the subtarget should run MachineScheduler after aggressive coalescing.

virtual CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const

virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOptLevel) const

Target can subclass this hook to select a different DAG scheduler.

virtual bool enableSpillageCopyElimination() const

Enable spillage copy elimination in MachineCopyPropagation pass.

virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const

Returns true if MI is a dependency breaking instruction for the subtarget.

virtual const CallLowering * getCallLowering() const

virtual bool isXRaySupported() const

virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const

Override generic post-ra scheduling policy within a region.

virtual const RegisterBankInfo * getRegBankInfo() const

If the information for the register banks is available, return it.

virtual bool useAA() const

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...

virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const

Override generic scheduling policy within a region.

TargetSubtargetInfo(const TargetSubtargetInfo &)=delete

virtual void mirFileLoaded(MachineFunction &MF) const

This is called after a .mir file was loaded.

virtual InstructionSelector * getInstructionSelector() const

virtual AntiDepBreakMode getAntiDepBreakMode() const

virtual bool enableWindowScheduler() const

True if the subtarget should run WindowScheduler.

virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const

virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const

virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, MCRegister PhysReg) const

True if the register allocator should use the allocation orders exactly as written in the tablegen de...

virtual bool enablePostRAMachineScheduler() const

True if the subtarget should run a machine scheduler after register allocation.

virtual bool enableAtomicExpand() const

True if the subtarget should run the atomic expansion pass.

virtual bool enableMachinePipeliner() const

True if the subtarget should run MachinePipeliner.

virtual const LegalizerInfo * getLegalizerInfo() const

virtual bool useDFAforSMS() const

Default to DFA for resource management, return false when target will use ProcResource in InstrSchedM...

virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const

virtual const TargetFrameLowering * getFrameLowering() const

virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const

Returns true if MI is a candidate for move elimination.

virtual const TargetInstrInfo * getInstrInfo() const

virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.

virtual bool enableMachineSchedDefaultSched() const

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...

virtual bool enablePostRAScheduler() const

True if the subtarget should run a scheduler after register allocation.

virtual bool enableSubRegLiveness() const

Enable tracking of subregister liveness in register allocator.

virtual const TargetLowering * getTargetLowering() const

virtual bool addrSinkUsingGEPs() const

Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.

virtual const InstrItineraryData * getInstrItineraryData() const

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.

virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...

TargetSubtargetInfo()=delete

TargetSubtargetInfo & operator=(const TargetSubtargetInfo &)=delete

virtual bool enableEarlyIfConversion() const

Enable the use of the early if conversion pass.

Triple - Helper class for working with autoconf configuration names.

A Use represents the edge between a Value definition and its users.

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

These values represent a non-pipelined step in the execution of an instruction.

Specify the number of cycles allowed after instruction issue before a particular use operand reads it...

Specify the latency in cpu cycles for a particular scheduling class and def index.

Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.