TargetSubtargetInfo.h Source File (original) (raw)

13#ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H

14#define LLVM_CODEGEN_TARGETSUBTARGETINFO_H

26#include

27#include

29namespace llvm {

67protected:

75 const unsigned *OC, const unsigned *FP);

77public:

80 using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };

102 return nullptr;

103 }

106 return nullptr;

107 }

109

111 return nullptr;

112 }

113

114

115

116

117

119 return nullptr;

120 }

121

122

125 return nullptr;

126 }

127

129

130

132

133

134

136

137

138

140 return nullptr;

141 }

142

143

144

145

146

148

149

150

151

152

158

159

160

161

162

163

164

165

166

167

171

172

173

174

175

176

177

178

182

183

184

185

186

187

188

189

190

191

195

196

197

198

199

200

201

202 virtual bool enableMachineScheduler() const;

203

204

205

207

208

210

211

213

214

215

216

217

218 virtual bool enableJoinGlobalCopies() const;

219

220

221

223

224

225

226

227

229

230

231

232 virtual bool enablePostRAMachineScheduler() const;

233

234

235 virtual bool enableAtomicExpand() const;

236

237

238 virtual bool enableIndirectBrExpand() const;

239

240

241

242

243

244

247

248

249

250

251

252

253

254

257

258

259

260

261

262

264 int UseOpIdx, SDep &Dep,

266 }

267

268

269

271

272

273

274

276 return CriticalPathRCs.clear();

277 }

278

279

280

282 std::vector<std::unique_ptr> &Mutations) const {

283 }

284

285

286

288 std::vector<std::unique_ptr> &Mutations) const {

289 }

290

291

292

294

295

296

300

301

302

303

304

305 virtual bool enableRALocalReassignment(CodeGenOptLevel OptLevel) const;

306

307

308

309 virtual bool useAA() const;

310

311

312

316

317

319

320

321

322

324 return nullptr;

325 }

326

327

328

329

331

332

334

335

336

337

342

343

344

345

346 virtual unsigned char

350

351

352

353

355

356

357 virtual std::vector getMacroFusions() const { return {}; };

358

359

360

362

363 return true;

364 }

365

367};

368}

369

370#endif

Analysis containing CSE Info

static bool enablePostRAScheduler(const TargetSubtargetInfo &ST, CodeGenOptLevel OptLevel)

SI optimize exec mask operations pre RA

This file defines the SmallVector class.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Itinerary data supplied by a subtarget to be used by a target.

Tracks which library functions to use for a particular subtarget.

Wrapper class representing physical registers. Should be passed by value.

MCSubtargetInfo(const MCSubtargetInfo &)=default

Representation of each machine instruction.

Holds all the information related to register banks.

ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOptLevel) FunctionPassCtor

Wrapper class representing virtual and physical registers.

Scheduling unit. This is a node in the scheduling DAG.

Mutate the DAG as a postpass after normal DAG building.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

Information about stack frame layout on the target.

TargetInstrInfo - Interface to description of machine instruction set.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Provide an instruction scheduling machine model to CodeGen passes.

virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const

Classify a global function reference.

Definition TargetSubtargetInfo.h:347

virtual bool requiresDisjointEarlyClobberAndUndef() const

Whether the target has instructions where an early-clobber result operand cannot overlap with an unde...

Definition TargetSubtargetInfo.h:361

~TargetSubtargetInfo() override

enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode

Definition TargetSubtargetInfo.h:80

SmallVectorImpl< const TargetRegisterClass * > RegClassVector

Definition TargetSubtargetInfo.h:81

virtual std::vector< MacroFusionPredTy > getMacroFusions() const

Get the list of MacroFusion predicates.

Definition TargetSubtargetInfo.h:357

virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const

Definition TargetSubtargetInfo.h:105

virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const

Override generic post-ra scheduling policy within a region.

Definition TargetSubtargetInfo.h:255

virtual const InlineAsmLowering * getInlineAsmLowering() const

Definition TargetSubtargetInfo.h:110

virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const

Override generic scheduling policy within a region.

Definition TargetSubtargetInfo.h:245

virtual void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const

Configure the LibcallLoweringInfo for this subtarget.

Definition TargetSubtargetInfo.h:147

virtual bool isRegisterReservedByUser(Register R) const

Definition TargetSubtargetInfo.h:366

virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const

Return PBQPConstraint(s) for the target.

Definition TargetSubtargetInfo.h:323

virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const

Definition TargetSubtargetInfo.h:275

virtual CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const

Definition TargetSubtargetInfo.h:297

TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)

virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOptLevel) const

Target can subclass this hook to select a different DAG scheduler.

Definition TargetSubtargetInfo.h:124

virtual bool enableSpillageCopyElimination() const

Enable spillage copy elimination in MachineCopyPropagation pass.

Definition TargetSubtargetInfo.h:354

virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const

Returns true if MI is a dependency breaking instruction for the subtarget.

Definition TargetSubtargetInfo.h:179

virtual const CallLowering * getCallLowering() const

Definition TargetSubtargetInfo.h:108

virtual bool isXRaySupported() const

Definition TargetSubtargetInfo.h:88

virtual const RegisterBankInfo * getRegBankInfo() const

If the information for the register banks is available, return it.

Definition TargetSubtargetInfo.h:135

virtual bool useAA() const

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...

TargetSubtargetInfo(const TargetSubtargetInfo &)=delete

virtual InstructionSelector * getInstructionSelector() const

Definition TargetSubtargetInfo.h:118

virtual AntiDepBreakMode getAntiDepBreakMode() const

Definition TargetSubtargetInfo.h:270

virtual bool enableWindowScheduler() const

True if the subtarget should run WindowScheduler.

Definition TargetSubtargetInfo.h:212

virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const

Definition TargetSubtargetInfo.h:281

virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const

Definition TargetSubtargetInfo.h:287

virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, MCRegister PhysReg) const

True if the register allocator should use the allocation orders exactly as written in the tablegen de...

Definition TargetSubtargetInfo.h:338

virtual bool enableMachinePipeliner() const

True if the subtarget should run MachinePipeliner.

Definition TargetSubtargetInfo.h:209

virtual const LegalizerInfo * getLegalizerInfo() const

Definition TargetSubtargetInfo.h:128

virtual bool useDFAforSMS() const

Default to DFA for resource management, return false when target will use ProcResource in InstrSchedM...

Definition TargetSubtargetInfo.h:293

virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const

Definition TargetSubtargetInfo.h:263

virtual const TargetFrameLowering * getFrameLowering() const

Definition TargetSubtargetInfo.h:101

virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const

Returns true if MI is a candidate for move elimination.

Definition TargetSubtargetInfo.h:192

virtual const TargetInstrInfo * getInstrInfo() const

Definition TargetSubtargetInfo.h:100

virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.

Definition TargetSubtargetInfo.h:168

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

virtual bool enableMachineSchedDefaultSched() const

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...

Definition TargetSubtargetInfo.h:206

virtual bool enableSubRegLiveness() const

Enable tracking of subregister liveness in register allocator.

Definition TargetSubtargetInfo.h:330

virtual const TargetLowering * getTargetLowering() const

Definition TargetSubtargetInfo.h:104

virtual bool addrSinkUsingGEPs() const

Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.

Definition TargetSubtargetInfo.h:313

virtual const InstrItineraryData * getInstrItineraryData() const

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.

Definition TargetSubtargetInfo.h:139

virtual bool enableTerminalRule() const

Hack to bring up option.

Definition TargetSubtargetInfo.h:222

virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...

Definition TargetSubtargetInfo.h:153

TargetSubtargetInfo()=delete

TargetSubtargetInfo & operator=(const TargetSubtargetInfo &)=delete

virtual bool enableEarlyIfConversion() const

Enable the use of the early if conversion pass.

Definition TargetSubtargetInfo.h:318

Triple - Helper class for working with autoconf configuration names.

A Use represents the edge between a Value definition and its users.

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

These values represent a non-pipelined step in the execution of an instruction.

Specify the number of cycles allowed after instruction issue before a particular use operand reads it...

Specify the latency in cpu cycles for a particular scheduling class and def index.

Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

A region of an MBB for scheduling.