LLVM: llvm::TargetSubtargetInfo Class Reference (original) (raw)

TargetSubtargetInfo - Generic base class for all target subtargets. More...

#include "[llvm/CodeGen/TargetSubtargetInfo.h](TargetSubtargetInfo%5F8h%5Fsource.html)"

Public Types
using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }
using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>
Public Types inherited from llvm::MCSubtargetInfo
enum HwModeType { HwMode_Default, HwMode_ValueType, HwMode_RegInfo, HwMode_EncodingInfo }
HwMode IDs are stored and accessed in a bit set format, enabling users to efficiently retrieve specific IDs, such as the RegInfo HwMode ID, from the set as required. More...
Public Member Functions
TargetSubtargetInfo ()=delete
TargetSubtargetInfo (const TargetSubtargetInfo &)=delete
TargetSubtargetInfo & operator= (const TargetSubtargetInfo &)=delete
~TargetSubtargetInfo () override
virtual bool isXRaySupported () const
virtual const TargetInstrInfo * getInstrInfo () const
virtual const TargetFrameLowering * getFrameLowering () const
virtual const TargetLowering * getTargetLowering () const
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo () const
virtual const CallLowering * getCallLowering () const
virtual const InlineAsmLowering * getInlineAsmLowering () const
virtual InstructionSelector * getInstructionSelector () const
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler (CodeGenOptLevel) const
Target can subclass this hook to select a different DAG scheduler.
virtual const LegalizerInfo * getLegalizerInfo () const
virtual const TargetRegisterInfo * getRegisterInfo () const =0
Return the target's register information.
virtual const RegisterBankInfo * getRegBankInfo () const
If the information for the register banks is available, return it.
virtual const InstrItineraryData * getInstrItineraryData () const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
virtual void initLibcallLoweringInfo (LibcallLoweringInfo &Info) const
Configure the LibcallLoweringInfo for this subtarget.
virtual unsigned resolveSchedClass (unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property.
virtual bool isZeroIdiom (const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.
virtual bool isDependencyBreaking (const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking instruction for the subtarget.
virtual bool isOptimizableRegisterMove (const MachineInstr *MI) const
Returns true if MI is a candidate for move elimination.
virtual bool enableMachineScheduler () const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableMachineSchedDefaultSched () const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.
virtual bool enableMachinePipeliner () const
True if the subtarget should run MachinePipeliner.
virtual bool enableWindowScheduler () const
True if the subtarget should run WindowScheduler.
virtual bool enableJoinGlobalCopies () const
True if the subtarget should enable joining global copies.
virtual bool enableTerminalRule () const
Hack to bring up option.
virtual bool enablePostRAScheduler () const
True if the subtarget should run a scheduler after register allocation.
virtual bool enablePostRAMachineScheduler () const
True if the subtarget should run a machine scheduler after register allocation.
virtual bool enableAtomicExpand () const
True if the subtarget should run the atomic expansion pass.
virtual bool enableIndirectBrExpand () const
True if the subtarget should run the indirectbr expansion pass.
virtual void overrideSchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const
Override generic scheduling policy within a region.
virtual void overridePostRASchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const
Override generic post-ra scheduling policy within a region.
virtual void adjustSchedDependency (SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const
virtual AntiDepBreakMode getAntiDepBreakMode () const
virtual void getCriticalPathRCs (RegClassVector &CriticalPathRCs) const
virtual void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const
virtual void getSMSMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const
virtual bool useDFAforSMS () const
Default to DFA for resource management, return false when target will use ProcResource in InstrSchedModel instead.
virtual CodeGenOptLevel getOptLevelToEnablePostRAScheduler () const
virtual bool enableRALocalReassignment (CodeGenOptLevel OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
virtual bool useAA () const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
virtual bool addrSinkUsingGEPs () const
Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.
virtual bool enableEarlyIfConversion () const
Enable the use of the early if conversion pass.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints () const
Return PBQPConstraint(s) for the target.
virtual bool enableSubRegLiveness () const
Enable tracking of subregister liveness in register allocator.
virtual void mirFileLoaded (MachineFunction &MF) const
This is called after a .mir file was loaded.
virtual bool ignoreCSRForAllocationOrder (const MachineFunction &MF, MCRegister PhysReg) const
True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions, false if it should allocate the specified physical register later if is it callee-saved.
virtual unsigned char classifyGlobalFunctionReference (const GlobalValue *GV) const
Classify a global function reference.
virtual bool enableSpillageCopyElimination () const
Enable spillage copy elimination in MachineCopyPropagation pass.
virtual std::vector< MacroFusionPredTy > getMacroFusions () const
Get the list of MacroFusion predicates.
virtual bool requiresDisjointEarlyClobberAndUndef () const
Whether the target has instructions where an early-clobber result operand cannot overlap with an undef input operand.
virtual bool isRegisterReservedByUser (Register R) const
Public Member Functions inherited from llvm::MCSubtargetInfo
MCSubtargetInfo (const MCSubtargetInfo &)=default
MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
MCSubtargetInfo ()=delete
MCSubtargetInfo & operator= (const MCSubtargetInfo &)=delete
MCSubtargetInfo & operator= (MCSubtargetInfo &&)=delete
virtual ~MCSubtargetInfo ()=default
const Triple & getTargetTriple () const
StringRef getCPU () const
StringRef getTuneCPU () const
const FeatureBitset & getFeatureBits () const
void setFeatureBits (const FeatureBitset &FeatureBits_)
StringRef getFeatureString () const
bool hasFeature (unsigned Feature) const
void setDefaultFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
FeatureBitset ToggleFeature (uint64_t FB)
Toggle a feature and return the re-computed feature bits.
FeatureBitset ToggleFeature (const FeatureBitset &FB)
Toggle a feature and return the re-computed feature bits.
FeatureBitset ToggleFeature (StringRef FS)
Toggle a set of features and return the re-computed feature bits.
FeatureBitset ApplyFeatureFlag (StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.
FeatureBitset SetFeatureBitsTransitively (const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
FeatureBitset ClearFeatureBitsTransitively (const FeatureBitset &FB)
bool checkFeatures (StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.
const MCSchedModel & getSchedModelForCPU (StringRef CPU) const
Get the machine model of a CPU.
const MCSchedModel & getSchedModel () const
Get the machine model for this subtarget's CPU.
const MCWriteProcResEntry * getWriteProcResBegin (const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
const MCWriteProcResEntry * getWriteProcResEnd (const MCSchedClassDesc *SC) const
const MCWriteLatencyEntry * getWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
int getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries (const MCSchedClassDesc &SC) const
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
InstrItineraryData getInstrItineraryForCPU (StringRef CPU) const
Get scheduling itinerary of a CPU.
void initInstrItins (InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
virtual unsigned resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
virtual bool isCPUStringValid (StringRef CPU) const
Check whether the CPU string is valid.
ArrayRef< SubtargetSubTypeKV > getAllProcessorDescriptions () const
Return processor descriptions.
ArrayRef< SubtargetFeatureKV > getAllProcessorFeatures () const
Return processor features.
std::vector< SubtargetFeatureKV > getEnabledProcessorFeatures () const
Return the list of processor features currently enabled.
virtual unsigned getHwModeSet () const
Return a bit set containing all HwMode IDs of the current subtarget.
virtual unsigned getHwMode (enum HwModeType type=HwMode_Default) const
HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current subtarget.
virtual std::optional< unsigned > getCacheSize (unsigned Level) const
Return the cache size in bytes for the given level of cache.
virtual std::optional< unsigned > getCacheAssociativity (unsigned Level) const
Return the cache associatvity for the given level of cache.
virtual std::optional< unsigned > getCacheLineSize (unsigned Level) const
Return the target cache line size in bytes at a given level.
virtual unsigned getCacheLineSize () const
Return the target cache line size in bytes.
virtual unsigned getPrefetchDistance () const
Return the preferred prefetch distance in terms of instructions.
virtual unsigned getMaxPrefetchIterationsAhead () const
Return the maximum prefetch distance in terms of loop iterations.
virtual bool enableWritePrefetching () const
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
virtual bool shouldPrefetchAddressSpace (unsigned AS) const
Protected Member Functions
TargetSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
Protected Member Functions inherited from llvm::MCSubtargetInfo
void InitMCProcessorInfo (StringRef CPU, StringRef TuneCPU, StringRef FS)
Initialize the scheduling model and feature bits.

TargetSubtargetInfo - Generic base class for all target subtargets.

All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.

Definition at line 66 of file TargetSubtargetInfo.h.

◆ AntiDepBreakMode

using llvm::TargetSubtargetInfo::AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }

◆ RegClassVector

TargetSubtargetInfo::TargetSubtargetInfo ( const Triple & TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< StringRef > PN, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry * WPR, const MCWriteLatencyEntry * WL, const MCReadAdvanceEntry * RA, const InstrStage * IS, const unsigned * OC, const unsigned * FP ) protected

◆ TargetSubtargetInfo() [2/3]

llvm::TargetSubtargetInfo::TargetSubtargetInfo ( ) delete

◆ TargetSubtargetInfo() [3/3]

◆ ~TargetSubtargetInfo()

TargetSubtargetInfo::~TargetSubtargetInfo ( ) overridedefault

◆ addrSinkUsingGEPs()

virtual bool llvm::TargetSubtargetInfo::addrSinkUsingGEPs ( ) const inlinevirtual

Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.

Definition at line 313 of file TargetSubtargetInfo.h.

References useAA().

◆ adjustSchedDependency()

virtual void llvm::TargetSubtargetInfo::adjustSchedDependency ( SUnit * Def, int DefOpIdx, SUnit * Use, int UseOpIdx, SDep & Dep, const TargetSchedModel * SchedModel ) const inlinevirtual

◆ classifyGlobalFunctionReference()

Classify a global function reference.

This mainly used to fetch target special flags for lowering a function address. For example mark a function call should be plt or pc-related addressing.

Definition at line 347 of file TargetSubtargetInfo.h.

◆ enableAtomicExpand()

bool TargetSubtargetInfo::enableAtomicExpand ( ) const virtual

◆ enableEarlyIfConversion()

virtual bool llvm::TargetSubtargetInfo::enableEarlyIfConversion ( ) const inlinevirtual

◆ enableIndirectBrExpand()

bool TargetSubtargetInfo::enableIndirectBrExpand ( ) const virtual

◆ enableJoinGlobalCopies()

bool TargetSubtargetInfo::enableJoinGlobalCopies ( ) const virtual

◆ enableMachinePipeliner()

virtual bool llvm::TargetSubtargetInfo::enableMachinePipeliner ( ) const inlinevirtual

◆ enableMachineSchedDefaultSched()

virtual bool llvm::TargetSubtargetInfo::enableMachineSchedDefaultSched ( ) const inlinevirtual

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.

Definition at line 206 of file TargetSubtargetInfo.h.

◆ enableMachineScheduler()

bool TargetSubtargetInfo::enableMachineScheduler ( ) const virtual

◆ enablePostRAMachineScheduler()

bool TargetSubtargetInfo::enablePostRAMachineScheduler ( ) const virtual

◆ enablePostRAScheduler()

bool TargetSubtargetInfo::enablePostRAScheduler ( ) const virtual

◆ enableRALocalReassignment()

True if the subtarget should run the local reassignment heuristic of the register allocator.

This heuristic may be compile time intensive, OptLevel provides a finer grain to tune the register allocator.

Definition at line 44 of file TargetSubtargetInfo.cpp.

◆ enableSpillageCopyElimination()

virtual bool llvm::TargetSubtargetInfo::enableSpillageCopyElimination ( ) const inlinevirtual

Enable spillage copy elimination in MachineCopyPropagation pass.

This helps removing redundant copies generated by register allocator when handling complex eviction chains.

Definition at line 354 of file TargetSubtargetInfo.h.

◆ enableSubRegLiveness()

virtual bool llvm::TargetSubtargetInfo::enableSubRegLiveness ( ) const inlinevirtual

◆ enableTerminalRule()

virtual bool llvm::TargetSubtargetInfo::enableTerminalRule ( ) const inlinevirtual

Hack to bring up option.

This should be unconditionally true, all targets should enable it and delete this.

Definition at line 222 of file TargetSubtargetInfo.h.

◆ enableWindowScheduler()

virtual bool llvm::TargetSubtargetInfo::enableWindowScheduler ( ) const inlinevirtual

◆ getAntiDepBreakMode()

virtual AntiDepBreakMode llvm::TargetSubtargetInfo::getAntiDepBreakMode ( ) const inlinevirtual

◆ getCallLowering()

virtual const CallLowering * llvm::TargetSubtargetInfo::getCallLowering ( ) const inlinevirtual

◆ getCriticalPathRCs()

virtual void llvm::TargetSubtargetInfo::getCriticalPathRCs ( RegClassVector & CriticalPathRCs) const inlinevirtual

◆ getCustomPBQPConstraints()

virtual std::unique_ptr< PBQPRAConstraint > llvm::TargetSubtargetInfo::getCustomPBQPConstraints ( ) const inlinevirtual

◆ getDAGScheduler()

◆ getFrameLowering()

Definition at line 101 of file TargetSubtargetInfo.h.

Referenced by llvm::CodeViewDebug::beginFunctionImpl(), checkNumAlignedDPRCS2Regs(), computeFPBPAlignmentGap(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::LoongArchRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::MachineFrameInfo::estimateStackSize(), fixupBlock(), getAddressForMemoryInput(), getFnStackAlignment(), llvm::AVRRegisterInfo::getFrameRegister(), llvm::M68kRegisterInfo::getFrameRegister(), llvm::XtensaRegisterInfo::getFrameRegister(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::XtensaRegisterInfo::getReservedRegs(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), llvm::MIRParserImpl::initializeFrameInfo(), insertCSRRestores(), insertCSRRestores(), insertCSRSaves(), insertCSRSaves(), llvm::MipsCallLowering::lowerCall(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LegalizerHelper::lowerDynStackAlloc(), mayCombineMisaligned(), llvm::MachineFrameInfo::print(), llvm::CFIFixup::runOnMachineFunction(), and llvm::X86FrameLowering::spillFPBP().

◆ getInlineAsmLowering()

◆ getInstrInfo()

Definition at line 100 of file TargetSubtargetInfo.h.

Referenced by llvm::MachineBasicBlock::addLiveIn(), allowPGOOutlining(), attemptDebugCopyProp(), llvm::avoidZeroOffsetLandingPad(), llvm::DwarfDebug::beginInstruction(), llvm::calculateRegAllocScore(), llvm::MachineBasicBlock::canSplitCriticalEdge(), combineFPFusedMultiply(), llvm::MachineFrameInfo::computeMaxCallFrameSize(), llvm::createBURRListDAGScheduler(), createDedicatedExit(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::VLIWResourceModel::createPacketizer(), createPHIsForCMOVsInSinkBB(), createPHIsForSelects(), llvm::createSourceListDAGScheduler(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), emitBuildPairF64Pseudo(), emitComments(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::NVPTXFrameLowering::emitPrologue(), emitQuietFCMP(), emitReadCounterWidePseudo(), emitSelectPseudo(), emitSplitPairF64Pseudo(), emitThumb2LoadConstPool(), emitVFROUND_NOEXCEPT_MASK(), llvm::MachineFunction::estimateFunctionSizeInBytes(), llvm::finalizeBundle(), llvm::MachineFunction::finalizeDebugInstrRefs(), findLoopIncrementValue(), findPrologueEndLoc(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), generateGatherLanePattern(), genIndexedMultiply(), genShXAddAddShift(), llvm::getEHScopeMembership(), llvm::MachineBasicBlock::getFallThrough(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MSP430InstrInfo::getInstSizeInBytes(), getOrCreateFrameHelper(), getSchedRegions(), getTargetIndexName(), llvm::TargetSchedModel::init(), llvm::MipsFunctionInfo::initGlobalBaseReg(), llvm::ConvergingVLIWScheduler::initialize(), llvm::TailDuplicator::initMF(), insertCSRRestores(), insertCSRRestores(), insertCSRSaves(), insertCSRSaves(), insertDivByZeroTrap(), llvm::insertMultibyteShift(), insertRememberRestorePair(), interpretValues(), jumpTableHasOtherUses(), llvm::AArch64CallLowering::lowerCall(), llvm::X86CallLowering::lowerCall(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), llvm::RISCVRegisterInfo::materializeFrameBaseRegister(), llvm::MachineInstr::mayAlias(), llvm::MachineBasicBlock::print(), llvm::MachineInstr::print(), llvm::MachineOperand::printTargetFlags(), llvm::AArch64FrameLowering::processFunctionBeforeFrameFinalized(), llvm::TargetInstrInfo::reassociateOps(), llvm::TargetInstrInfo::reduceAccumulatorTree(), replaceFI(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::RAGreedy::run(), llvm::ReachingDefInfo::run(), runImpl(), llvm::ExecutionDomainFix::runOnMachineFunction(), llvm::MachineFunction::salvageCopySSA(), llvm::MachineFunction::salvageCopySSAImpl(), setCallTargetReg(), llvm::MachineIRBuilder::setMF(), llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg(), llvm::MachineBasicBlock::SkipPHIsAndLabels(), llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::CSKYFrameLowering::spillCalleeSavedRegisters(), llvm::LoongArchFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), and llvm::MachineBasicBlock::updateTerminator().

◆ getInstrItineraryData()

◆ getInstructionSelector()

virtual InstructionSelector * llvm::TargetSubtargetInfo::getInstructionSelector ( ) const inlinevirtual

◆ getLegalizerInfo()

virtual const LegalizerInfo * llvm::TargetSubtargetInfo::getLegalizerInfo ( ) const inlinevirtual

◆ getMacroFusions()

virtual std::vector< MacroFusionPredTy > llvm::TargetSubtargetInfo::getMacroFusions ( ) const inlinevirtual

◆ getOptLevelToEnablePostRAScheduler()

virtual CodeGenOptLevel llvm::TargetSubtargetInfo::getOptLevelToEnablePostRAScheduler ( ) const inlinevirtual

◆ getPostRAMutations()

virtual void llvm::TargetSubtargetInfo::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation > > & Mutations) const inlinevirtual

◆ getRegBankInfo()

◆ getRegisterInfo()

Return the target's register information.

Referenced by addLiveInRegs(), llvm::MachineFunction::allocateRegMask(), llvm::TargetFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(), llvm::A57ChainingConstraint::apply(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), llvm::CodeViewDebug::beginFunctionImpl(), buildAnyextOrCopy(), llvm::LiveRangeEdit::calculateRegClassAndHint(), cannotInsertTailCall(), checkNumAlignedDPRCS2Regs(), computeFPBPAlignmentGap(), computeLiveOuts(), llvm::TargetSchedModel::computeOutputLatency(), convertCallSiteObjects(), convertEntryValueObjects(), convertStackObjects(), llvm::createBURRListDAGScheduler(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::createSourceListDAGScheduler(), createTuple(), llvm::MipsInstrInfo::describeLoadedValue(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::CSKYFrameLowering::determineCalleeSaves(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::SystemZELFFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::DwarfDebug::emitDebugLocValue(), emitDebugValueComment(), llvm::ARMFrameLowering::emitEpilogue(), emitFakeUse(), emitFrameOffsetAdj(), emitKill(), llvm::CSKYFrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), emitVFROUND_NOEXCEPT_MASK(), llvm::MachineFrameInfo::estimateStackSize(), llvm::finalizeBundle(), findLoopIncrementValue(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::TargetFrameLowering::getCalleeSaves(), llvm::TargetFrameLowering::getDwarfFrameBase(), llvm::X86FrameLowering::getDwarfFrameBase(), llvm::CSKYFrameLowering::getFrameIndexReference(), llvm::LoongArchFrameLowering::getFrameIndexReference(), llvm::RISCVFrameLowering::getFrameIndexReference(), llvm::TargetFrameLowering::getFrameIndexReference(), llvm::AArch64FrameLowering::getFrameIndexReferencePreferSP(), getGatherLanePattern(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::MachineFrameInfo::getPristineRegs(), getRegistersForValue(), getRegistersForValue(), getRegTy(), llvm::AArch64FrameLowering::hasFPImpl(), llvm::ARCFrameLowering::hasFPImpl(), llvm::ARMFrameLowering::hasFPImpl(), llvm::CSKYFrameLowering::hasFPImpl(), llvm::LoongArchFrameLowering::hasFPImpl(), llvm::RISCVFrameLowering::hasFPImpl(), llvm::VEFrameLowering::hasFPImpl(), llvm::LiveRegMatrix::init(), llvm::LiveStacks::init(), llvm::RegBankSelect::init(), llvm::RegPressureTracker::init(), initRegisterMaskIds(), insertCSRRestores(), insertCSRRestores(), insertCSRSaves(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), interpretValues(), isNonFoldablePartialRegisterLoad(), llvm::MipsCallLowering::lowerCall(), llvm::InlineAsmLowering::lowerInlineAsm(), patchMatchingInput(), llvm::MachineBasicBlock::print(), llvm::MachineFunction::print(), printMF(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::MachineBasicBlock::removeLiveInOverlappedWith(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::ReachingDefInfo::run(), llvm::LiveDebugVariables::LDVImpl::runOnMachineFunction(), llvm::InstructionSelect::selectMachineFunction(), setAliasRegs(), llvm::MIRParserImpl::setupRegisterInfo(), llvm::MachineBasicBlock::splitAt(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::X86InstrInfo::unfoldMemoryOperand(), UpdateOperandRegClass(), and llvm::RegisterBankInfo::InstructionMapping::verify().

◆ getSelectionDAGInfo()

◆ getSMSMutations()

virtual void llvm::TargetSubtargetInfo::getSMSMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation > > & Mutations) const inlinevirtual

◆ getTargetLowering()

virtual const TargetLowering * llvm::TargetSubtargetInfo::getTargetLowering ( ) const inlinevirtual

Definition at line 104 of file TargetSubtargetInfo.h.

Referenced by llvm::MachineIRBuilder::buildBoolExtInReg(), llvm::calculateDbgEntityHistory(), createAtomicLibcall(), llvm::createLibcall(), llvm::createMemLibcall(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::SystemZELFFrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::MachineIRBuilder::getBoolExtOp(), llvm::SystemZELFRegisters::getCalleeSavedRegs(), llvm::SystemZELFRegisters::getCallPreservedMask(), getRegistersForValue(), llvm::SelectionDAG::init(), llvm::GenericScheduler::initPolicy(), InsertStackProtectors(), interpretValues(), llvm::isInTailCallPosition(), isRegOtherThanSPAndFP(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MachineBasicBlock::liveout_begin(), llvm::LegalizerHelper::lowerMemCpyFamily(), llvm::ExpandFpPass::run(), llvm::ExpandLargeDivRemPass::run(), llvm::SafeStackPass::run(), runImpl(), llvm::InstructionSelect::selectMachineFunction(), and llvm::AArch64GISelUtils::tryEmitBZero().

◆ ignoreCSRForAllocationOrder()

True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions, false if it should allocate the specified physical register later if is it callee-saved.

Definition at line 338 of file TargetSubtargetInfo.h.

◆ initLibcallLoweringInfo()

virtual void llvm::TargetSubtargetInfo::initLibcallLoweringInfo ( LibcallLoweringInfo & Info) const inlinevirtual

◆ isDependencyBreaking()

Returns true if MI is a dependency breaking instruction for the subtarget.

Similar in behavior to isZeroIdiom. However, it knows how to identify all dependency breaking instructions (i.e. not just zero-idioms).

As for isZeroIdiom, this method returns a mask of "broken" dependencies. (See method isZeroIdiom for a detailed description of Mask).

Definition at line 179 of file TargetSubtargetInfo.h.

References isZeroIdiom(), and MI.

◆ isOptimizableRegisterMove()

virtual bool llvm::TargetSubtargetInfo::isOptimizableRegisterMove ( const MachineInstr * MI) const inlinevirtual

Returns true if MI is a candidate for move elimination.

A candidate for move elimination may be optimized out at register renaming stage. Subtargets can specify the set of optimizable moves by instantiating tablegen class IsOptimizableRegisterMove (see llvm/Target/TargetInstrPredicate.td).

SubtargetEmitter is responsible for processing all the definitions of class IsOptimizableRegisterMove, and auto-generate an override for this method.

Definition at line 192 of file TargetSubtargetInfo.h.

References MI.

◆ isRegisterReservedByUser()

virtual bool llvm::TargetSubtargetInfo::isRegisterReservedByUser ( Register R) const inlinevirtual

◆ isXRaySupported()

virtual bool llvm::TargetSubtargetInfo::isXRaySupported ( ) const inlinevirtual

◆ isZeroIdiom()

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.

This function also sets bits in Mask related to input operands that are not in a data dependency relationship. There is one bit for each machine operand; implicit operands follow explicit operands in the bit representation used for Mask. An empty (i.e. a mask with all bits cleared) means: data dependencies are "broken" for all the explicit input machine operands of MI.

Definition at line 168 of file TargetSubtargetInfo.h.

References MI.

Referenced by isDependencyBreaking().

◆ mirFileLoaded()

void TargetSubtargetInfo::mirFileLoaded ( MachineFunction & MF) const virtual

◆ operator=()

◆ overridePostRASchedPolicy()

Override generic post-ra scheduling policy within a region.

This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic post-ra scheduling policy. Note that some options like tracking register pressure won't take effect in post-ra scheduling.

Definition at line 255 of file TargetSubtargetInfo.h.

Referenced by llvm::PostGenericScheduler::initPolicy().

◆ overrideSchedPolicy()

◆ requiresDisjointEarlyClobberAndUndef()

virtual bool llvm::TargetSubtargetInfo::requiresDisjointEarlyClobberAndUndef ( ) const inlinevirtual

Whether the target has instructions where an early-clobber result operand cannot overlap with an undef input operand.

Definition at line 361 of file TargetSubtargetInfo.h.

◆ resolveSchedClass()

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property.

This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.

Definition at line 153 of file TargetSubtargetInfo.h.

References MI.

◆ useAA()

bool TargetSubtargetInfo::useAA ( ) const virtual

◆ useDFAforSMS()

virtual bool llvm::TargetSubtargetInfo::useDFAforSMS ( ) const inlinevirtual

The documentation for this class was generated from the following files: