Thumb2ITBlockPass.cpp Source File (original) (raw)

26#include

27#include

29using namespace llvm;

31#define DEBUG_TYPE "thumb2-it"

32#define PASS_NAME "Thumb IT blocks insertion pass"

34 STATISTIC(NumITs, "Number of IT blocks inserted");

35 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");

39namespace {

42 public:

43 static char ID;

45 bool restrictIT;

56 MachineFunctionProperties::Property::NoVRegs);

57 }

61 }

63 private:

68 };

70 char Thumb2ITBlock::ID = 0;

72}

82 RegList LocalDefs;

83 RegList LocalUses;

85 for (auto &MO : MI->operands()) {

86 if (!MO.isReg())

87 continue;

89 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)

90 continue;

91 if (MO.isUse())

92 LocalUses.push_back(Reg);

93 else

94 LocalDefs.push_back(Reg);

95 }

97 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {

98 for (unsigned Reg : Regs)

99 for (MCPhysReg Subreg : TRI->subregs_inclusive(Reg))

100 UsesDefs.insert(Subreg);

101 };

102

103 InsertUsesDefs(LocalDefs, Defs);

104 InsertUsesDefs(LocalUses, Uses);

105}

106

107

108

109

112 if (!MO.isReg() || MO.isDef() || !MO.isKill())

113 continue;

114 if ( Uses .count(MO.getReg()))

115 continue;

116 MO.setIsKill(false);

117 }

118}

119

121 switch (MI->getOpcode()) {

122 default:

123 return false;

124 case ARM::MOVr:

125 case ARM::MOVr_TC:

126 case ARM::tMOVr:

127 case ARM::t2MOVr:

128 return true;

129 }

130}

131

132bool

137 return false;

138

139

140

141 assert(MI->getOperand(0).getSubReg() == 0 &&

142 MI->getOperand(1).getSubReg() == 0 &&

143 "Sub-register indices still around?");

144

145 Register DstReg = MI->getOperand(0).getReg();

146 Register SrcReg = MI->getOperand(1).getReg();

147

148

149 if (Uses.count(DstReg) || Defs.count(SrcReg))

150 return false;

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

169 if (MI->hasOptionalDef() &&

170 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)

171 return false;

172

173

174

176 ++I;

178

179 while (I != E && I->isDebugInstr())

180 ++I;

181

182 if (I != E) {

185 if (NCC == CC || NCC == OCC)

186 return true;

187 }

188 return false;

189}

190

195

196 while (MBBI != E) {

203 continue;

204 }

205

207 Uses.clear();

209

210

213

214

216 true, false));

217

221

222

224 unsigned Mask = 0, Pos = 3;

225

226

227

228 if (!restrictIT) {

230

231

232 for (; MBBI != E && Pos &&

233 (->isBranch() && ->isReturn()) ; ++MBBI) {

234 if (MBBI->isDebugInstr())

235 continue;

236

238 MI = NMI;

239

242 if (NCC == CC || NCC == OCC) {

243 Mask |= ((NCC ^ CC) & 1) << Pos;

244

246 true, false));

247 LastITMI = NMI;

248 } else {

250 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {

255 ++NumMovedInsts;

256 continue;

257 }

258 break;

259 }

261 --Pos;

262 }

263 }

264

265

266 Mask |= (1 << Pos);

268

269

272

273

276

278 ++NumITs;

279 }

280

282}

283

284bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {

287 return false;

292

293 if (!AFI->isThumbFunction())

294 return false;

295

297 for (auto &MBB : Fn )

299

301 AFI->setHasITBlocks(true);

302

304}

305

306

307

MachineBasicBlock MachineBasicBlock::iterator MBBI

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

Remove Loads Into Fake Uses

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallSet class.

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

SmallSet< unsigned, 4 > RegisterSet

static bool isCopy(MachineInstr *MI)

static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses)

Clear kill flags for any uses in the given set.

static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, const TargetRegisterInfo *TRI)

TrackDefUses - Tracking what registers are being defined and used by instructions in the IT block.

ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...

const ARMBaseInstrInfo * getInstrInfo() const override

const ARMBaseRegisterInfo * getRegisterInfo() const override

FunctionPass class - This class is used to implement most global optimizations.

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

MachineInstr * remove(MachineInstr *I)

Remove the unbundled instruction from the instruction list without deleting it.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

virtual MachineFunctionProperties getRequiredProperties() const

Properties which a MachineFunction may have at a given point in time.

MachineFunctionProperties & set(Property P)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

instr_iterator getInstrIterator() const

Representation of each machine instruction.

void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false)

Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

MachineOperand class - Representation of each machine instruction operand.

void setIsKill(bool Val=true)

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Wrapper class representing virtual and physical registers.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

self_iterator getIterator()

static CondCodes getOppositeCondition(CondCodes CC)

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)

finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)

getITInstrPredicate - Valid only in Thumb2 mode.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionPass * createThumb2ITBlockPass()

createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.