VLIWMachineScheduler.cpp Source File (original) (raw)

33#include

34#include

35#include

36#include

37#include

39using namespace llvm;

41#define DEBUG_TYPE "machine-scheduler"

62 cl::desc("High register pressure threhold."));

87 if (SUd->Succs.size() == 0)

88 return false;

90 for (const auto &S : SUd->Succs) {

93 if (S.isCtrl())

94 continue;

96 if (S.getSUnit() == SUu && S.getLatency() > 0)

97 return true;

98 }

99 return false;

100}

101

102

103

104

105

106

109 return false;

110

111

112

114 default:

116 return false;

117 break;

118 case TargetOpcode::EXTRACT_SUBREG:

119 case TargetOpcode::INSERT_SUBREG:

120 case TargetOpcode::SUBREG_TO_REG:

121 case TargetOpcode::REG_SEQUENCE:

122 case TargetOpcode::IMPLICIT_DEF:

123 case TargetOpcode::COPY:

124 case TargetOpcode::INLINEASM:

125 case TargetOpcode::INLINEASM_BR:

126 break;

127 }

128

129

130

131 if (IsTop) {

134 return false;

135 } else {

138 return false;

139 }

140 return true;

141}

142

143

145 bool startNewCycle = false;

146

147 if (!SU) {

150 return false;

151 }

152

153

158 startNewCycle = true;

159 }

160

162 default:

164 break;

165 case TargetOpcode::EXTRACT_SUBREG:

166 case TargetOpcode::INSERT_SUBREG:

167 case TargetOpcode::SUBREG_TO_REG:

168 case TargetOpcode::REG_SEQUENCE:

169 case TargetOpcode::IMPLICIT_DEF:

170 case TargetOpcode::KILL:

171 case TargetOpcode::CFI_INSTRUCTION:

172 case TargetOpcode::EH_LABEL:

173 case TargetOpcode::COPY:

174 case TargetOpcode::INLINEASM:

175 case TargetOpcode::INLINEASM_BR:

176 break;

177 }

178 Packet.push_back(SU);

179

180#ifndef NDEBUG

182 for (unsigned i = 0, e = Packet.size(); i != e; ++i) {

186 }

187#endif

188

189 return startNewCycle;

190}

191

196

197

198

199

201 LLVM_DEBUG(dbgs() << "********** MI Converging Scheduling VLIW "

203 << " in_func " << BB->getParent()->getName()

204 << " at loop depth " << MLI->getLoopDepth(BB) << " \n");

205

207

208 Topo.InitDAGTopologicalSorting();

209

210

212

215

216

218

220 unsigned maxH = 0;

222 if (SU.getHeight() > maxH)

223 maxH = SU.getHeight();

224 dbgs() << "Max Height " << maxH << "\n";

225 });

227 unsigned maxD = 0;

229 if (SU.getDepth() > maxD)

230 maxD = SU.getDepth();

231 dbgs() << "Max Depth " << maxD << "\n";

232 });

236

238

239 bool IsTopNode = false;

240 while (true) {

242 dbgs() << "** VLIWMachineScheduler::schedule picking next node\n");

244 if (!SU)

245 break;

246

248 break;

249

251

252

253 SchedImpl->schedNode(SU, IsTopNode);

254

256 }

258

260

262 dbgs() << "*** Final schedule for "

265 dbgs() << '\n';

266 });

267}

268

272

275

276

277

281 delete Top.HazardRec;

282 delete Bot.HazardRec;

283 Top.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG);

284 Bot.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG);

285

286 delete Top.ResourceModel;

287 delete Bot.ResourceModel;

290

291 const std::vector &MaxPressure =

292 DAG->getRegPressure().MaxSetPressure;

294 for (unsigned i = 0, e = MaxPressure.size(); i < e; ++i) {

295 unsigned Limit = DAG->getRegClassInfo()->getRegPressureSetLimit(i);

297 ((float)MaxPressure[i] > ((float)Limit * RPThreshold));

298 }

299}

300

305

307 for (const SDep &PI : SU->Preds) {

309 unsigned MinLatency = PI.getLatency();

310#ifndef NDEBUG

311 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);

312#endif

313 if (SU->TopReadyCycle < PredReadyCycle + MinLatency)

315 }

316

319}

320

322 assert(SU->getInstr() && "Scheduled SUnit must have instr");

323

325 ++I) {

326 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;

327 unsigned MinLatency = I->getLatency();

328#ifndef NDEBUG

329 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);

330#endif

331 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)

333 }

334

337}

338

343

344

345

346

347

348

349

350

351

352

353

354

355

356

360

363 return true;

364

365 return false;

366}

367

369 SUnit *SU, unsigned ReadyCycle) {

372

373

374

376

378 else

380}

381

382

384 unsigned Width = SchedModel->getIssueWidth();

386

388 "MinReadyCycle uninitialized");

390

392

394 } else {

395

399 else

401 }

402 }

404

407}

408

409

411 bool startNewCycle = false;

412

413

416

417

419 }

421 }

422

423

425

426

427

429 if (startNewCycle) {

432 } else

435}

436

437

438

440

442 MinReadyCycle = std::numeric_limits::max();

443

444

445

446 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {

449

452

454 continue;

455

457 continue;

458

461 --i;

462 --e;

463 }

465}

466

467

471 else {

472 assert(Pending.isInQueue(SU) && "bad ready count");

474 }

475}

476

477

478

479

483

484 auto AdvanceCycle = [this]() {

486 return true;

490 return false;

491 };

492 for (unsigned i = 0; AdvanceCycle(); ++i) {

494 "permanent hazard");

495 (void)i;

499 }

502 return nullptr;

503}

504

505#ifndef NDEBUG

509 dbgs() << Label << " " << Q.getName() << " ";

510 if (P.isValid())

511 dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":"

512 << P.getUnitInc() << " ";

513 else

514 dbgs() << " ";

515 dbgs() << "cost(" << Cost << ")\t";

516 DAG->dumpNode(*SU);

517}

518

519

524

529 DAG->getRegionCriticalPSets(),

530 DAG->getRegPressure().MaxSetPressure);

531 std::stringstream dbgstr;

532 dbgstr << "SU(" << std::setw(3) << (*I)->NodeNum << ")";

533 dbgs() << dbgstr.str();

535 dbgs() << "\t";

536 (*I)->getInstr()->dump();

537 }

538 dbgs() << "\n";

539}

540#endif

541

542

543

546 return false;

547

548 for (auto &Pred : SU->Preds) {

549

550 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2))

551 return false;

552 }

553

554 return true;

555}

556

557

558

561 return false;

562

563 for (auto &Succ : SU->Succs) {

564

565 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2))

566 return false;

567 }

568 return true;

569}

570

571

572

573

574

575

578 for (const auto &P : PD) {

579 if (.isValid())

580 continue;

581

582

583

585 return (isBotUp ? P.getUnitInc() : -P.getUnitInc());

586 }

587 return 0;

588}

589

590

591

595 bool verbose) {

596

597 int ResCount = 1;

598

599

601 return ResCount;

602

604 << ((Q.getID() == TopQID) ? "(top|" : "(bot|"));

605

609 }

610

611 unsigned IsAvailableAmt = 0;

612

614 if (Top.isLatencyBound(SU)) {

617 }

618

620 std::stringstream dbgstr;

621 dbgstr << "h" << std::setw(3) << SU->getHeight() << "|";

622 dbgs() << dbgstr.str();

623 });

624

625

626

627 if (Top.ResourceModel->isResourceAvailable(SU, true)) {

629 ResCount += IsAvailableAmt;

631 } else

633 } else {

634 if (Bot.isLatencyBound(SU)) {

637 }

638

640 std::stringstream dbgstr;

641 dbgstr << "d" << std::setw(3) << SU->getDepth() << "|";

642 dbgs() << dbgstr.str();

643 });

644

645

646

647 if (Bot.ResourceModel->isResourceAvailable(SU, false)) {

649 ResCount += IsAvailableAmt;

651 } else

653 }

654

655 unsigned NumNodesBlocking = 0;

657

658

659

660

661 if (Top.isLatencyBound(SU))

664 ++NumNodesBlocking;

665 } else {

666

667 if (Bot.isLatencyBound(SU))

670 ++NumNodesBlocking;

671 }

672 ResCount += (NumNodesBlocking * ScaleTwo);

673

675 std::stringstream dbgstr;

676 dbgstr << "blk " << std::setw(2) << NumNodesBlocking << ")|";

677 dbgs() << dbgstr.str();

678 });

679

680

682

684

686

687

689

690

691

695 ResCount -= IsAvailableAmt;

700 });

701 }

702

703

704

706 for (const SDep &PI : SU->Preds) {

709 Top.ResourceModel->isInPacket(PI.getSUnit())) {

712 }

713 }

716 if (.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() &&

717 SI.getLatency() == 0 &&

718 Bot.ResourceModel->isInPacket(SI.getSUnit())) {

721 }

722 }

723 }

724

725

726

727

728

729

732 for (const auto &PI : SU->Preds) {

733 if (PI.getLatency() > 0 &&

734 Top.ResourceModel->isInPacket(PI.getSUnit())) {

737 }

738 }

739 } else {

740 for (const auto &SI : SU->Succs) {

741 if (SI.getLatency() > 0 &&

742 Bot.ResourceModel->isInPacket(SI.getSUnit())) {

745 }

746 }

747 }

748 }

749

751 std::stringstream dbgstr;

752 dbgstr << "Total " << std::setw(4) << ResCount << ")";

753 dbgs() << dbgstr.str();

754 });

755

756 return ResCount;

757}

758

759

760

761

762

763

771 else Q.dump(););

772

773

775

776

780 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,

781 DAG->getRegionCriticalPSets(),

782 DAG->getRegPressure().MaxSetPressure);

783

784 int CurrentCost = SchedulingCost(Q, *I, Candidate, RPDelta, false);

785

786

787 if (!Candidate.SU) {

789 Candidate.SU = *I;

790 Candidate.RPDelta = RPDelta;

791 Candidate.SCost = CurrentCost;

793 continue;

794 }

795

796

797

798 if (CurrentCost < 0 && Candidate.SCost < 0) {

802 Candidate.SU = *I;

803 Candidate.RPDelta = RPDelta;

804 Candidate.SCost = CurrentCost;

806 }

807 continue;

808 }

809

810

811 if (CurrentCost > Candidate.SCost) {

813 Candidate.SU = *I;

814 Candidate.RPDelta = RPDelta;

815 Candidate.SCost = CurrentCost;

817 continue;

818 }

819

820

823 if (CurrWeak != CandWeak) {

824 if (CurrWeak < CandWeak) {

826 Candidate.SU = *I;

827 Candidate.RPDelta = RPDelta;

828 Candidate.SCost = CurrentCost;

829 FoundCandidate = Weak;

830 }

831 continue;

832 }

833

835 unsigned CurrSize, CandSize;

837 CurrSize = (*I)->Succs.size();

838 CandSize = Candidate.SU->Succs.size();

839 } else {

840 CurrSize = (*I)->Preds.size();

841 CandSize = Candidate.SU->Preds.size();

842 }

843 if (CurrSize > CandSize) {

845 Candidate.SU = *I;

846 Candidate.RPDelta = RPDelta;

847 Candidate.SCost = CurrentCost;

849 }

850

851

852 if (CurrSize != CandSize)

853 continue;

854 }

855

856

857

858

863 Candidate.SU = *I;

864 Candidate.RPDelta = RPDelta;

865 Candidate.SCost = CurrentCost;

867 continue;

868 }

869 }

870

871

872

873 if (FoundCandidate == NoCand)

874 continue;

875 }

876 return FoundCandidate;

877}

878

879

881

882

883 if (SUnit *SU = Bot.pickOnlyChoice()) {

885 IsTopNode = false;

886 return SU;

887 }

888 if (SUnit *SU = Top.pickOnlyChoice()) {

890 IsTopNode = true;

891 return SU;

892 }

894

897 assert(BotResult != NoCand && "failed to find the first candidate");

898

899

900

901

902

903

904

905

908 IsTopNode = false;

909 return BotCand.SU;

910 }

911

915 assert(TopResult != NoCand && "failed to find the first candidate");

916

919 IsTopNode = true;

920 return TopCand.SU;

921 }

922

923

925 LLVM_DEBUG(dbgs() << "Prefered Bottom Node SingleMax\n");

926 IsTopNode = false;

927 return BotCand.SU;

928 }

930 LLVM_DEBUG(dbgs() << "Prefered Top Node SingleMax\n");

931 IsTopNode = true;

932 return TopCand.SU;

933 }

936 IsTopNode = true;

937 return TopCand.SU;

938 }

939

940 LLVM_DEBUG(dbgs() << "Prefered Bottom in Node order\n");

941 IsTopNode = false;

942 return BotCand.SU;

943}

944

945

947 if (DAG->top() == DAG->bottom()) {

948 assert(Top.Available.empty() && Top.Pending.empty() &&

949 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");

950 return nullptr;

951 }

954 SU = Top.pickOnlyChoice();

955 if (!SU) {

959 assert(TopResult != NoCand && "failed to find the first candidate");

960 (void)TopResult;

961 SU = TopCand.SU;

962 }

963 IsTopNode = true;

965 SU = Bot.pickOnlyChoice();

966 if (!SU) {

970 assert(BotResult != NoCand && "failed to find the first candidate");

971 (void)BotResult;

972 SU = BotCand.SU;

973 }

974 IsTopNode = false;

975 } else {

977 }

979 Top.removeReady(SU);

981 Bot.removeReady(SU);

982

983 LLVM_DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")

984 << " Scheduling instruction in cycle "

985 << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " ("

987 DAG->dumpNode(*SU));

988 return SU;

989}

990

991

992

993

994

996 if (IsTopNode) {

997 Top.bumpNode(SU);

999 } else {

1000 Bot.bumpNode(SU);

1002 }

1003}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static const Function * getParent(const Value *V)

This file defines the SmallVector class.

static bool isSingleUnscheduledPred(SUnit *SU, SUnit *SU2)

isSingleUnscheduledPred - If SU2 is the only unscheduled predecessor of SU, return true (we may have ...

Definition VLIWMachineScheduler.cpp:544

static cl::opt< bool > CheckEarlyAvail("check-early-avail", cl::Hidden, cl::init(true))

static cl::opt< bool > IgnoreBBRegPressure("ignore-bb-reg-pressure", cl::Hidden, cl::init(false))

static cl::opt< float > RPThreshold("vliw-misched-reg-pressure", cl::Hidden, cl::init(0.75f), cl::desc("High register pressure threhold."))

static cl::opt< bool > UseNewerCandidate("use-newer-candidate", cl::Hidden, cl::init(true))

static bool isSingleUnscheduledSucc(SUnit *SU, SUnit *SU2)

isSingleUnscheduledSucc - If SU2 is the only unscheduled successor of SU, return true (we may have du...

Definition VLIWMachineScheduler.cpp:559

static cl::opt< unsigned > SchedDebugVerboseLevel("misched-verbose-level", cl::Hidden, cl::init(1))

VLIWMachineScheduler * DAG

void releaseBottomNode(SUnit *SU) override

When all successor dependencies have been resolved, free this node for bottom-up scheduling.

Definition VLIWMachineScheduler.cpp:321

static constexpr unsigned PriorityOne

SUnit * pickNode(bool &IsTopNode) override

Pick the best node to balance the schedule. Implements MachineSchedStrategy.

Definition VLIWMachineScheduler.cpp:946

virtual VLIWResourceModel * createVLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const

Definition VLIWMachineScheduler.cpp:301

int pressureChange(const SUnit *SU, bool isBotUp)

Check if the instruction changes the register pressure of a register in the high pressure set.

Definition VLIWMachineScheduler.cpp:576

SmallVector< bool > HighPressureSets

List of pressure sets that have a high pressure level in the region.

static constexpr unsigned ScaleTwo

CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)

Pick the best candidate from the top queue.

Definition VLIWMachineScheduler.cpp:765

void schedNode(SUnit *SU, bool IsTopNode) override

Update the scheduler's state after scheduling a node.

Definition VLIWMachineScheduler.cpp:995

void readyQueueVerboseDump(const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)

Definition VLIWMachineScheduler.cpp:520

void releaseTopNode(SUnit *SU) override

When all predecessor dependencies have been resolved, free this node for top-down scheduling.

Definition VLIWMachineScheduler.cpp:306

SUnit * pickNodeBidrectional(bool &IsTopNode)

Pick the best candidate node from either the top or bottom queue.

Definition VLIWMachineScheduler.cpp:880

static constexpr unsigned PriorityTwo

static constexpr unsigned PriorityThree

const TargetSchedModel * SchedModel

void initialize(ScheduleDAGMI *dag) override

Initialize the strategy after building the DAG for a new region.

Definition VLIWMachineScheduler.cpp:269

virtual int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)

Single point to compute overall scheduling cost.

Definition VLIWMachineScheduler.cpp:592

void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P=PressureChange())

Definition VLIWMachineScheduler.cpp:506

CandResult

Represent the type of SchedCandidate found within a single queue.

Itinerary data supplied by a subtarget to be used by a target.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

bool isPseudo(QueryType Type=IgnoreBundle) const

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Capture a change in pressure for a single pressure set.

List of PressureChanges in order of increasing, unique PSetID.

Helpers for implementing custom MachineSchedStrategy classes.

LLVM_ABI void dump() const

std::vector< SUnit * >::iterator iterator

StringRef getName() const

Track the current register pressure at some position in the instruction stream, and remember the high...

void getMaxPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)

Find the pressure set with the most change beyond its pressure limit after traversing this instructio...

unsigned getLatency() const

Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...

bool isAssignedRegDep() const

Tests if this is a Data dependence that is associated with a register.

Scheduling unit. This is a node in the scheduling DAG.

bool isCall

Is a function call.

unsigned TopReadyCycle

Cycle relative to start when node is ready.

unsigned NodeNum

Entry # of node in the node vector.

unsigned getHeight() const

Returns the height of this node, which is the length of the maximum path down to any node which has n...

bool isScheduleHigh

True if preferable to schedule high.

unsigned getDepth() const

Returns the depth of this node, which is the length of the maximum path up to any node which has no p...

bool isScheduled

True once scheduled.

unsigned BotReadyCycle

Cycle relative to end when node is ready.

SmallVector< SDep, 4 > Succs

All sunit successors.

bool isBottomReady() const

SmallVector< SDep, 4 > Preds

All sunit predecessors.

SmallVectorImpl< SDep >::iterator succ_iterator

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

MachineBasicBlock * BB

The block in which to insert instructions.

ScheduleDAGTopologicalSort Topo

Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.

MachineBasicBlock::iterator begin() const

Returns an iterator to the top of the current scheduling region.

const MachineLoopInfo * MLI

void scheduleMI(SUnit *SU, bool IsTopNode)

Move an instruction and update register pressure.

void initQueues(ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)

Release ExitSU predecessors and setup scheduler queues.

void buildDAGWithRegPressure()

Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled.

void dump() const override

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

void dumpSchedule() const

dump the scheduled Sequence.

std::unique_ptr< MachineSchedStrategy > SchedImpl

void postProcessDAG()

Apply each ScheduleDAGMutation step in order.

void findRootsAndBiasEdges(SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)

MachineBasicBlock::iterator CurrentBottom

The bottom of the unscheduled zone.

void viewGraph() override

Out-of-line implementation with no arguments is handy for gdb.

void updateQueues(SUnit *SU, bool IsTopNode)

Update scheduler DAG and queues after scheduling an instruction.

void placeDebugValues()

Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.

MachineBasicBlock::iterator CurrentTop

The top of the unscheduled zone.

std::vector< SUnit > SUnits

The scheduling units.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const

Create machine specific model for scheduling.

Provide an instruction scheduling machine model to CodeGen passes.

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetInstrInfo * getInstrInfo() const

Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...

void schedule() override

Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work.

Definition VLIWMachineScheduler.cpp:200

unsigned TotalPackets

Total packets created.

virtual ~VLIWResourceModel()

Definition VLIWMachineScheduler.cpp:83

virtual bool hasDependence(const SUnit *SUd, const SUnit *SUu)

Return true if there is a dependence between SUd and SUu.

Definition VLIWMachineScheduler.cpp:86

virtual DFAPacketizer * createPacketizer(const TargetSubtargetInfo &STI) const

Definition VLIWMachineScheduler.cpp:193

virtual bool reserveResources(SUnit *SU, bool IsTop)

Keep track of available resources.

Definition VLIWMachineScheduler.cpp:144

DFAPacketizer * ResourcesModel

ResourcesModel - Represents VLIW state.

SmallVector< SUnit * > Packet

Local packet/bundle model.

const TargetSchedModel * SchedModel

VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)

Definition VLIWMachineScheduler.cpp:64

virtual void reset()

Definition VLIWMachineScheduler.cpp:78

virtual bool isResourceAvailable(SUnit *SU, bool IsTop)

Check if scheduling of this SU is possible in the current packet.

Definition VLIWMachineScheduler.cpp:107

const TargetInstrInfo * TII

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

LLVM_ABI unsigned getWeakLeft(const SUnit *SU, bool isTop)

cl::opt< bool > ViewMISchedDAGs

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI cl::opt< MISched::Direction > PreRADirection

LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

Store the state used by ConvergingVLIWScheduler heuristics, required for the lifetime of one invocati...

Each Scheduling boundary is associated with ready queues.

const TargetSchedModel * SchedModel

~VLIWSchedBoundary()

Definition VLIWMachineScheduler.cpp:339

bool isLatencyBound(SUnit *SU)

void releaseNode(SUnit *SU, unsigned ReadyCycle)

Definition VLIWMachineScheduler.cpp:368

void removeReady(SUnit *SU)

Remove SU from the ready set for this boundary.

Definition VLIWMachineScheduler.cpp:468

ScheduleHazardRecognizer * HazardRec

void bumpNode(SUnit *SU)

Move the boundary of scheduled code by one SUnit.

Definition VLIWMachineScheduler.cpp:410

unsigned MinReadyCycle

MinReadyCycle - Cycle of the soonest available instruction.

VLIWResourceModel * ResourceModel

void releasePending()

Release pending ready nodes in to the available queue.

Definition VLIWMachineScheduler.cpp:439

SUnit * pickOnlyChoice()

If this queue only has one ready candidate, return it.

Definition VLIWMachineScheduler.cpp:480

void bumpCycle()

Move the boundary of scheduled code by one cycle.

Definition VLIWMachineScheduler.cpp:383

bool checkHazard(SUnit *SU)

Does this SU have a hazard within the current instruction group.

Definition VLIWMachineScheduler.cpp:357

Store the effects of a change in pressure on things that MI scheduler cares about.

PressureChange CriticalMax

PressureChange CurrentMax