X86MCCodeEmitter.cpp Source File (original) (raw)

31#include

32#include

33#include

35using namespace llvm;

37#define DEBUG_TYPE "mccodeemitter"

39namespace {

41enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX };

45class X86OpcodePrefixHelper {

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145

146private:

147 unsigned W : 1;

148 unsigned R : 1;

149 unsigned X : 1;

150 unsigned B : 1;

151 unsigned M : 1;

152 unsigned R2 : 1;

153 unsigned X2 : 1;

154 unsigned B2 : 1;

155 unsigned VEX_4V : 4;

156 unsigned VEX_L : 1;

157 unsigned VEX_PP : 2;

158 unsigned VEX_5M : 5;

159 unsigned EVEX_z : 1;

160 unsigned EVEX_L2 : 1;

161 unsigned EVEX_b : 1;

162 unsigned EVEX_V2 : 1;

163 unsigned EVEX_aaa : 3;

164 PrefixKind Kind = None;

166

167 unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {

168 return MRI.getEncodingValue(MI.getOperand(OpNum).getReg());

169 }

170

171 void setR(unsigned Encoding) { R = Encoding >> 3 & 1; }

172 void setR2(unsigned Encoding) {

173 R2 = Encoding >> 4 & 1;

174 assert(( || (Kind <= REX2 || Kind == EVEX)) && "invalid setting");

175 }

176 void setX(unsigned Encoding) { X = Encoding >> 3 & 1; }

177 void setX2(unsigned Encoding) {

178 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");

179 X2 = Encoding >> 4 & 1;

180 }

181 void setB(unsigned Encoding) { B = Encoding >> 3 & 1; }

182 void setB2(unsigned Encoding) {

183 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");

184 B2 = Encoding >> 4 & 1;

185 }

186 void set4V(unsigned Encoding) { VEX_4V = Encoding & 0xf; }

187 void setV2(unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }

188

189public:

190 void setW(bool V) { W = V; }

191 void setR(const MCInst &MI, unsigned OpNum) {

192 setR(getRegEncoding(MI, OpNum));

193 }

194 void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {

196

198 return;

199 unsigned Encoding = MRI.getEncodingValue(Reg);

200 X = Encoding >> Shift & 1;

201 }

202 void setB(const MCInst &MI, unsigned OpNum) {

203 B = getRegEncoding(MI, OpNum) >> 3 & 1;

204 }

205 void set4V(const MCInst &MI, unsigned OpNum, bool IsImm = false) {

206

207 if (IsImm)

208 set4V(~(MI.getOperand(OpNum).getImm()));

209 else

210 set4V(getRegEncoding(MI, OpNum));

211 }

212 void setL(bool V) { VEX_L = V; }

213 void setPP(unsigned V) { VEX_PP = V; }

214 void set5M(unsigned V) { VEX_5M = V; }

215 void setR2(const MCInst &MI, unsigned OpNum) {

216 setR2(getRegEncoding(MI, OpNum));

217 }

218 void setRR2(const MCInst &MI, unsigned OpNum) {

219 unsigned Encoding = getRegEncoding(MI, OpNum);

220 setR(Encoding);

221 setR2(Encoding);

222 }

223 void setM(bool V) { M = V; }

224 void setXX2(const MCInst &MI, unsigned OpNum) {

226 unsigned Encoding = MRI.getEncodingValue(Reg);

227 setX(Encoding);

228

230 setX2(Encoding);

231 }

232 void setBB2(const MCInst &MI, unsigned OpNum) {

234 unsigned Encoding = MRI.getEncodingValue(Reg);

235 setB(Encoding);

236

238 setB2(Encoding);

239 }

240 void setZ(bool V) { EVEX_z = V; }

241 void setL2(bool V) { EVEX_L2 = V; }

242 void setEVEX_b(bool V) { EVEX_b = V; }

243 void setEVEX_U(bool V) { X2 = V; }

244 void setV2(const MCInst &MI, unsigned OpNum, bool HasVEX_4V) {

245

246 if (HasVEX_4V)

247 return;

250 return;

251 setV2(MRI.getEncodingValue(Reg));

252 }

253 void set4VV2(const MCInst &MI, unsigned OpNum) {

254 unsigned Encoding = getRegEncoding(MI, OpNum);

255 set4V(Encoding);

256 setV2(Encoding);

257 }

258 void setAAA(const MCInst &MI, unsigned OpNum) {

259 EVEX_aaa = getRegEncoding(MI, OpNum);

260 }

261 void setNF(bool V) { EVEX_aaa |= V << 2; }

262 void setSC(const MCInst &MI, unsigned OpNum) {

263 unsigned Encoding = MI.getOperand(OpNum).getImm();

264 EVEX_V2 = ~(Encoding >> 3) & 0x1;

265 EVEX_aaa = Encoding & 0x7;

266 }

267

269 : W(0), R(0), X(0), B(0), M(0), R2(0), X2(0), B2(0), VEX_4V(0), VEX_L(0),

270 VEX_PP(0), VEX_5M(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0),

271 EVEX_aaa(0), MRI(MRI) {}

272

273 void setLowerBound(PrefixKind K) { Kind = K; }

274

275 PrefixKind determineOptimalKind() {

276 switch (Kind) {

278

279

280

281 Kind = (R2 | X2 | B2) ? REX2 : (W | R | X | B) ? REX : None;

282 break;

283 case REX:

284 Kind = (R2 | X2 | B2) ? REX2 : REX;

285 break;

286 case REX2:

287 case XOP:

288 case VEX3:

289 case EVEX:

290 break;

291 case VEX2:

292 Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;

293 break;

294 }

295 return Kind;

296 }

297

300 ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;

301 uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;

302 switch (Kind) {

304 return;

305 case REX:

306 emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, CB);

307 return;

308 case REX2:

309 emitByte(0xD5, CB);

310 emitByte(M << 7 | R2 << 6 | X2 << 5 | B2 << 4 | W << 3 | R << 2 | X << 1 |

311 B,

312 CB);

313 return;

314 case VEX2:

315 emitByte(0xC5, CB);

316 emitByte(((~R) & 1) << 7 | LastPayload, CB);

317 return;

318 case VEX3:

319 case XOP:

320 emitByte(Kind == VEX3 ? 0xC4 : 0x8F, CB);

321 emitByte(FirstPayload | VEX_5M, CB);

322 emitByte(W << 7 | LastPayload, CB);

323 return;

324 case EVEX:

325 assert(VEX_5M && !(VEX_5M & 0x8) && "invalid mmm fields for EVEX!");

326 emitByte(0x62, CB);

327 emitByte(FirstPayload | ((~R2) & 0x1) << 4 | B2 << 3 | VEX_5M, CB);

328 emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | ((~X2) & 0x1) << 2 | VEX_PP,

329 CB);

330 emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |

331 ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,

332 CB);

333 return;

334 }

335 }

336};

337

341

342public:

344 : MCII(mcii), Ctx(ctx) {}

345 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;

346 X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;

347 ~X86MCCodeEmitter() override = default;

348

351

355

356private:

357 unsigned getX86RegNum(const MCOperand &MO) const;

358

359 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;

360

362 bool IsPCRel, uint64_t StartByte,

365

366 void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,

368

369 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,

371

372 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,

377 bool ForceSIB = false) const;

378

379 PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,

382

383 PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,

386

387 void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,

389

390 PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,

393

394 PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,

397};

398

399}

400

402 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");

403 return RM | (RegOpcode << 3) | (Mod << 6);

404}

405

408

409 for (unsigned i = 0; i != Size; ++i) {

410 emitByte(Val & 255, CB);

411 Val >>= 8;

412 }

413}

414

415

416

417

420

421 unsigned CD8_Scale =

423 CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;

424 if (!HasEVEX || !CD8_Scale)

426

428 if (Value & (CD8_Scale - 1))

429 return false;

430

431 int CDisp8 = Value / static_cast<int>(CD8_Scale);

433 return false;

434

435

436 ImmOffset = CDisp8 - Value;

437 return true;

438}

439

440

441

445 switch (Size) {

446 default:

448 case 4:

450 }

451 }

452 switch (Size) {

453 default:

455 case 1:

457 case 2:

459 case 4:

461 case 8:

463 }

464}

465

467

468

469

470

471

472

473

474

475

483 }

484

487

490 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")

495}

496

501 }

502 return false;

503}

504

506 unsigned Opcode = MI.getOpcode();

508 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&

509 Opcode != X86::JCC_4) ||

512 return false;

513

516 if (.isExpr())

517 return false;

518

521}

522

523unsigned X86MCCodeEmitter::getX86RegNum(const MCOperand &MO) const {

525}

526

527unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,

528 unsigned OpNum) const {

530}

531

532void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,

534 uint64_t StartByte,

535 SmallVectorImpl &CB,

536 SmallVectorImpl &Fixups,

537 int ImmOffset) const {

538 unsigned Size = 4;

542 break;

545 break;

548 break;

549 }

550 const MCExpr *Expr = nullptr;

551 if (DispOp.isImm()) {

552

553

555 PCRel)) {

557 return;

558 }

560 } else {

562 }

563

564

569 assert(ImmOffset == 0);

570

571 if (Size == 8) {

573 } else {

576 }

577

579 ImmOffset = static_cast<int>(CB.size() - StartByte);

583 }

585 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);

589 }

590 }

591 }

592

593 if (ImmOffset)

595 Ctx, Expr->getLoc());

596

597

601}

602

603void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,

604 unsigned RegOpcodeFld,

605 SmallVectorImpl &CB) const {

606 emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CB);

607}

608

609void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,

610 SmallVectorImpl &CB) const {

611

613}

614

615void X86MCCodeEmitter::emitMemModRMByte(

616 const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags,

617 PrefixKind Kind, uint64_t StartByte, SmallVectorImpl &CB,

618 SmallVectorImpl &Fixups, const MCSubtargetInfo &STI,

619 bool ForceSIB) const {

625

626

627 if (BaseReg == X86::RIP ||

628 BaseReg == X86::EIP) {

630 "Rip-relative addressing requires 64-bit mode");

631 assert(!IndexReg.getReg() && !ForceSIB && "Invalid rip-relative address");

632 emitByte(modRMByte(0, RegOpcodeField, 5), CB);

633

634 unsigned Opcode = MI.getOpcode();

636

637

640

641

642

643 switch (Opcode) {

644 default:

646 case X86::MOV64rm:

647

648

649

652 case X86::ADC32rm:

653 case X86::ADD32rm:

654 case X86::AND32rm:

655 case X86::CMP32rm:

656 case X86::MOV32rm:

657 case X86::OR32rm:

658 case X86::SBB32rm:

659 case X86::SUB32rm:

660 case X86::TEST32mr:

661 case X86::XOR32rm:

662 case X86::CALL64m:

663 case X86::JMP64m:

664 case X86::TAILJMPm64:

665 case X86::TEST64mr:

666 case X86::ADC64rm:

667 case X86::ADD64rm:

668 case X86::AND64rm:

669 case X86::CMP64rm:

670 case X86::OR64rm:

671 case X86::SBB64rm:

672 case X86::SUB64rm:

673 case X86::XOR64rm:

674 case X86::LEA64r:

678 case X86::ADD64rm_NF:

679 case X86::ADD64rm_ND:

680 case X86::ADD64mr_ND:

681 case X86::ADD64mr_NF_ND:

682 case X86::ADD64rm_NF_ND:

684 }

685 }();

686

687

688

689

690

691

692

693

696 : 0;

697

698 emitImmediate(Disp, MI.getLoc(), FixupKind, true, StartByte, CB, Fixups,

699 -ImmSize);

700 return;

701 }

702

703 unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;

704

705 bool IsAdSize16 = STI.hasFeature(X86::Is32Bit) &&

707

708

709

711 if (BaseReg) {

712

713

714

715

716

717

718

719

720

721

722

723 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};

724 unsigned RMfield = R16Table[BaseRegNo];

725

726 assert(RMfield && "invalid 16-bit base register");

727

728 if (IndexReg.getReg()) {

729 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];

730

731 assert(IndexReg16 && "invalid 16-bit index register");

732

733 assert(((IndexReg16 ^ RMfield) & 2) &&

734 "invalid 16-bit base/index register combination");

736 "invalid scale for 16-bit memory reference");

737

738

739 if (IndexReg16 & 2)

740 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);

741 else

742 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);

743 }

744

746 if (Disp.getImm() == 0 && RMfield != 6) {

747

748 emitByte(modRMByte(0, RegOpcodeField, RMfield), CB);

749 return;

750 }

751

752 emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);

753 emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,

754 Fixups);

755 return;

756 }

757

758 emitByte(modRMByte(2, RegOpcodeField, RMfield), CB);

759 } else {

760 assert(!IndexReg.getReg() && "Unexpected index register!");

761

762 emitByte(modRMByte(0, RegOpcodeField, 6), CB);

763 }

764

765

766 emitImmediate(Disp, MI.getLoc(), FK_Data_2, false, StartByte, CB, Fixups);

767 return;

768 }

769

770

773

774

775 bool AllowNoDisp = !UseDisp8 && !UseDisp32;

776

777 bool AllowDisp8 = !UseDisp32;

778

779

782 if (!BaseReg) {

783 emitByte(modRMByte(0, RegOpcodeField, 5), CB);

784 emitImmediate(Disp, MI.getLoc(), FK_Data_4, false, StartByte, CB, Fixups);

785 return;

786 }

787

788

789

790

791

792

794 if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {

795 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);

796 return;

797 }

798

799

803

804

806 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);

807 return;

808 }

809 }

810 }

811

812

813

814

815

816 if (Disp.isImm() && AllowDisp8) {

817 int ImmOffset = 0;

819 emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);

820 emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB,

821 Fixups, ImmOffset);

822 return;

823 }

824 }

825

826

827

828

829 emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CB);

830 unsigned Opcode = MI.getOpcode();

834 CB, Fixups);

835 return;

836 }

837

838

839 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&

840 "Cannot use ESP as index reg!");

841

842 bool ForceDisp32 = false;

843 bool ForceDisp8 = false;

844 int ImmOffset = 0;

845 if (!BaseReg) {

846

847

848 BaseRegNo = 5;

849 emitByte(modRMByte(0, RegOpcodeField, 4), CB);

850 ForceDisp32 = true;

851 } else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&

852

853

854

855

857

858 emitByte(modRMByte(0, RegOpcodeField, 4), CB);

859 } else if (Disp.isImm() && AllowDisp8 &&

861

862

863

864 emitByte(modRMByte(1, RegOpcodeField, 4), CB);

865 ForceDisp8 = true;

866 } else {

867

868 emitByte(modRMByte(2, RegOpcodeField, 4), CB);

869 ForceDisp32 = true;

870 }

871

872

873 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};

874 unsigned SS = SSTable[Scale.getImm()];

875

876 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4;

877

878 emitSIBByte(SS, IndexRegNo, BaseRegNo, CB);

879

880

881 if (ForceDisp8)

882 emitImmediate(Disp, MI.getLoc(), FK_Data_1, false, StartByte, CB, Fixups,

883 ImmOffset);

884 else if (ForceDisp32)

886 CB, Fixups);

887}

888

889

890

891

892

893PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,

894 const MCSubtargetInfo &STI,

895 SmallVectorImpl &CB) const {

896 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;

897

899

900 if (MemoryOperand != -1) {

901 MemoryOperand += CurOp;

903 }

904

905

906 unsigned Flags = MI.getFlags();

908 emitByte(0xF3, CB);

910 emitByte(0xF2, CB);

911

912

915 emitByte(0x67, CB);

916

918 switch (Form) {

919 default:

920 break;

922

923 if (MI.getOperand(2).getReg() != X86::DS)

924 emitSegmentOverridePrefix(2, MI, CB);

925 CurOp += 3;

926 break;

927 }

929

930 if (MI.getOperand(1).getReg() != X86::DS)

931 emitSegmentOverridePrefix(1, MI, CB);

932 CurOp += 2;

933 break;

934 }

936 ++CurOp;

937 break;

938 }

940

941 emitSegmentOverridePrefix(1, MI, CB);

942 break;

943 }

944 }

945

946

947

949 ? emitVEXOpcodePrefix(MemoryOperand, MI, STI, CB)

950 : emitOpcodePrefix(MemoryOperand, MI, STI, CB);

951}

952

953

954

955

956

957

958

959

960

961

962

963

964

965

966PrefixKind

967X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,

968 const MCSubtargetInfo &STI,

969 SmallVectorImpl &CB) const {

970 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

971 uint64_t TSFlags = Desc.TSFlags;

972

974

975#ifndef NDEBUG

976 unsigned NumOps = MI.getNumOperands();

978 ++I) {

979 const MCOperand &MO = MI.getOperand(I);

981 continue;

983 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)

985 "Cannot encode high byte register in VEX/EVEX-prefixed instruction");

986 }

987#endif

988

991 default:

992 break;

994 Prefix.setLowerBound(XOP);

995 break;

997

999 break;

1001 Prefix.setLowerBound(EVEX);

1002 break;

1003 }

1004

1007

1012

1014 default:

1017 Prefix.set5M(0x1);

1018 break;

1020 Prefix.set5M(0x2);

1021 break;

1023 Prefix.set5M(0x3);

1024 break;

1027 break;

1030 break;

1033 break;

1036 break;

1039 break;

1042 break;

1045 break;

1046 }

1047

1052 Prefix.setPP(0x1);

1053 break;

1055 Prefix.setPP(0x2);

1056 break;

1058 Prefix.setPP(0x3);

1059 break;

1060 }

1061

1065

1066 bool EncodeRC = false;

1067 uint8_t EVEX_rc = 0;

1068

1071

1073 default:

1074 llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");

1076

1081 Prefix.set4VV2(MI, CurOp++);

1082 break;

1083 }

1086 break;

1090

1091

1092

1093

1094

1095

1096

1100

1101 if (IsND)

1102 Prefix.set4VV2(MI, CurOp++);

1103

1105

1106 if (HasEVEX_K)

1108

1109 if (!IsND && HasVEX_4V)

1110 Prefix.set4VV2(MI, CurOp++);

1111

1113 if (HasTwoConditionalOps) {

1114 Prefix.set4V(MI, CurOp++, true);

1116 }

1117 break;

1118 }

1122

1123

1124

1125

1126

1127

1128

1129

1130

1131

1132

1133 if (IsND)

1134 Prefix.set4VV2(MI, CurOp++);

1135

1137

1138 if (HasEVEX_K)

1140

1141 if (!IsND && HasVEX_4V)

1142 Prefix.set4VV2(MI, CurOp++);

1143

1148 if (HasTwoConditionalOps) {

1149 Prefix.set4V(MI, CurOp++, true);

1151 }

1152 break;

1153 }

1155

1156

1161 break;

1162 }

1164

1169 break;

1170 }

1180

1181

1182

1183 if (HasVEX_4V)

1184 Prefix.set4VV2(MI, CurOp++);

1185

1186 if (HasEVEX_K)

1188

1193 if (HasTwoConditionalOps) {

1194 Prefix.set4V(MI, CurOp++, true);

1196 }

1197 break;

1198 }

1201

1202

1203

1204

1205

1206

1207

1208

1209

1210

1211 if (IsND)

1212 Prefix.set4VV2(MI, CurOp++);

1214

1215 if (HasEVEX_K)

1217

1218 if (!IsND && HasVEX_4V)

1219 Prefix.set4VV2(MI, CurOp++);

1220

1223 ++CurOp;

1224

1225 if (HasTwoConditionalOps) {

1226 Prefix.set4V(MI, CurOp++, true);

1228 }

1229

1231 if (HasEVEX_RC) {

1232 unsigned NumOps = Desc.getNumOperands();

1233 unsigned RcOperand = NumOps - 1;

1234 assert(RcOperand >= CurOp);

1235 EVEX_rc = MI.getOperand(RcOperand).getImm();

1236 assert(EVEX_rc <= 3 && "Invalid rounding control!");

1237 }

1238 EncodeRC = true;

1239 }

1240 break;

1241 }

1243

1244

1247 Prefix.set4VV2(MI, CurOp++);

1248 break;

1249 }

1251

1254

1255 ++CurOp;

1256

1259 ++CurOp;

1260 break;

1261 }

1264

1265

1266

1267

1268

1269

1270

1271 if (IsND)

1272 Prefix.set4VV2(MI, CurOp++);

1275 ++CurOp;

1276

1277 if (HasEVEX_K)

1279

1280 if (!IsND && HasVEX_4V)

1281 Prefix.set4VV2(MI, CurOp++);

1282

1284 if (HasTwoConditionalOps) {

1285 Prefix.set4V(MI, CurOp++, true);

1287 }

1289 EncodeRC = true;

1290 break;

1291 }

1293

1294

1295

1297 break;

1298 }

1308

1309

1310 if (HasVEX_4V)

1311 Prefix.set4VV2(MI, CurOp++);

1312

1313 if (HasEVEX_K)

1315

1318 ++CurOp;

1319 if (HasTwoConditionalOps) {

1320 Prefix.set4V(MI, ++CurOp, true);

1322 }

1323 break;

1324 }

1325 }

1326 if (EncodeRC) {

1327 Prefix.setL(EVEX_rc & 0x1);

1328 Prefix.setL2(EVEX_rc & 0x2);

1329 }

1330 PrefixKind Kind = Prefix.determineOptimalKind();

1332 return Kind;

1333}

1334

1335

1336

1337

1338

1339

1340

1341PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,

1342 const MCSubtargetInfo &STI,

1343 SmallVectorImpl &CB) const {

1345 return None;

1347 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

1348 uint64_t TSFlags = Desc.TSFlags;

1350 unsigned NumOps = MI.getNumOperands();

1351 bool UsesHighByteReg = false;

1352#ifndef NDEBUG

1353 bool HasRegOp = false;

1354#endif

1356 for (unsigned i = CurOp; i != NumOps; ++i) {

1357 const MCOperand &MO = MI.getOperand(i);

1358 if (MO.isReg()) {

1359#ifndef NDEBUG

1360 HasRegOp = true;

1361#endif

1363 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)

1364 UsesHighByteReg = true;

1365

1367 Prefix.setLowerBound(REX);

1369

1370

1371

1372

1373

1377 Prefix.setLowerBound(REX);

1378 }

1379 }

1380 }

1382 Prefix.setLowerBound(REX);

1385 Prefix.setLowerBound(REX2);

1387 default:

1388 assert(!HasRegOp && "Unexpected form in emitREXPrefix!");

1389 break;

1395 break;

1398 break;

1403 break;

1410 break;

1414 break;

1420 break;

1433 break;

1445 break;

1446 }

1448 PrefixKind Kind = Prefix.determineOptimalKind();

1449 if (Kind && UsesHighByteReg)

1451 "Cannot encode high byte register in REX-prefixed instruction");

1453 return Kind;

1454}

1455

1456

1457void X86MCCodeEmitter::emitSegmentOverridePrefix(

1458 unsigned SegOperand, const MCInst &MI, SmallVectorImpl &CB) const {

1459

1460 if (MCRegister Reg = MI.getOperand(SegOperand).getReg())

1462}

1463

1464

1465

1466

1467

1468

1469

1470PrefixKind X86MCCodeEmitter::emitOpcodePrefix(int MemOperand, const MCInst &MI,

1471 const MCSubtargetInfo &STI,

1472 SmallVectorImpl &CB) const {

1473 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

1474 uint64_t TSFlags = Desc.TSFlags;

1475

1476

1479 emitByte(0x66, CB);

1480

1481

1483 emitByte(0xF0, CB);

1484

1485

1487 emitByte(0x3E, CB);

1488

1491 emitByte(0x66, CB);

1492 break;

1494 emitByte(0xF3, CB);

1495 break;

1497 emitByte(0xF2, CB);

1498 break;

1499 }

1500

1501

1503 "REX.W requires 64bit mode.");

1504 PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, CB);

1505

1506

1508 case X86II::TB:

1509

1510 if (Kind == REX2)

1511 break;

1512 [[fallthrough]];

1515 case X86II::ThreeDNow:

1516 emitByte(0x0F, CB);

1517 break;

1518 }

1519

1522 emitByte(0x38, CB);

1523 break;

1525 emitByte(0x3A, CB);

1526 break;

1527 }

1528

1529 return Kind;

1530}

1531

1532void X86MCCodeEmitter::emitPrefix(const MCInst &MI, SmallVectorImpl &CB,

1533 const MCSubtargetInfo &STI) const {

1534 unsigned Opcode = MI.getOpcode();

1535 const MCInstrDesc &Desc = MCII.get(Opcode);

1536 uint64_t TSFlags = Desc.TSFlags;

1537

1538

1540 return;

1541

1543

1544 emitPrefixImpl(CurOp, MI, STI, CB);

1545}

1546

1549 static_cast<X86MCCodeEmitter &>(MCE).emitPrefix(MI, CB, STI);

1550}

1551

1552void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,

1556 unsigned Opcode = MI.getOpcode();

1559

1560

1562 return;

1563

1564 unsigned NumOps = Desc.getNumOperands();

1566

1568

1569 PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, CB);

1570

1571

1574

1575

1578

1579

1580 unsigned I8RegNum = 0;

1581

1583

1585 BaseOpcode = 0x0F;

1586

1587 unsigned OpcodeOffset = 0;

1588

1591

1593 switch (Form) {

1594 default:

1595 errs() << "FORM: " << Form << "\n";

1596 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");

1598 llvm_unreachable("Pseudo instruction shouldn't be emitted");

1603 emitByte(BaseOpcode, CB);

1604 break;

1606

1607 OpcodeOffset = MI.getOperand(NumOps - 1).getImm();

1608 assert(OpcodeOffset < 16 && "Unexpected opcode offset!");

1609 --NumOps;

1610 [[fallthrough]];

1612 emitByte(BaseOpcode + OpcodeOffset, CB);

1613

1615 break;

1616

1619 StartByte, CB, Fixups);

1620 break;

1621 }

1623 emitByte(BaseOpcode, CB);

1624 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),

1626 ++CurOp;

1627 break;

1629 emitByte(BaseOpcode, CB);

1630 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),

1632 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_1, false,

1633 StartByte, CB, Fixups);

1634 break;

1636 emitByte(BaseOpcode, CB);

1637 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), getImmFixupKind(TSFlags),

1639 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), FK_Data_2, false,

1640 StartByte, CB, Fixups);

1641 break;

1642

1644 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CB);

1645 break;

1646

1648 emitByte(BaseOpcode, CB);

1649 unsigned SrcRegNum = CurOp + 1;

1650

1651 if (HasEVEX_K)

1652 ++SrcRegNum;

1653

1654 if (HasVEX_4V)

1655 ++SrcRegNum;

1656 if (IsND)

1657 ++CurOp;

1658

1659 emitRegModRMByte(MI.getOperand(CurOp),

1660 getX86RegNum(MI.getOperand(SrcRegNum)), CB);

1661 CurOp = SrcRegNum + 1;

1662 break;

1663 }

1665 unsigned FirstOp = CurOp++;

1666 unsigned SecondOp = CurOp++;

1667 unsigned CC = MI.getOperand(CurOp++).getImm();

1668 emitByte(BaseOpcode + CC, CB);

1669 emitRegModRMByte(MI.getOperand(FirstOp),

1670 getX86RegNum(MI.getOperand(SecondOp)), CB);

1671 break;

1672 }

1674 unsigned CC = MI.getOperand(8).getImm();

1675 emitByte(BaseOpcode + CC, CB);

1677 emitMemModRMByte(MI, CurOp + 1, getX86RegNum(MI.getOperand(0)), TSFlags,

1678 Kind, StartByte, CB, Fixups, STI, false);

1679 CurOp = SrcRegNum + 3;

1680 break;

1681 }

1684 emitByte(BaseOpcode, CB);

1686

1687 if (HasEVEX_K)

1688 ++SrcRegNum;

1689

1690 if (HasVEX_4V)

1691 ++SrcRegNum;

1692

1693 if (IsND)

1694 ++CurOp;

1695

1697 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,

1698 Kind, StartByte, CB, Fixups, STI, ForceSIB);

1699 CurOp = SrcRegNum + 1;

1700 break;

1701 }

1703 unsigned MemOp = CurOp;

1705 unsigned RegOp = CurOp++;

1706 unsigned CC = MI.getOperand(CurOp++).getImm();

1707 emitByte(BaseOpcode + CC, CB);

1708 emitMemModRMByte(MI, MemOp, getX86RegNum(MI.getOperand(RegOp)), TSFlags,

1709 Kind, StartByte, CB, Fixups, STI);

1710 break;

1711 }

1713 emitByte(BaseOpcode, CB);

1714 unsigned SrcRegNum = CurOp + 1;

1715

1716 if (HasEVEX_K)

1717 ++SrcRegNum;

1718

1719 if (HasVEX_4V)

1720 ++SrcRegNum;

1721

1722 if (IsND)

1723 ++CurOp;

1724

1725 emitRegModRMByte(MI.getOperand(SrcRegNum),

1726 getX86RegNum(MI.getOperand(CurOp)), CB);

1727 CurOp = SrcRegNum + 1;

1728 if (HasVEX_I8Reg)

1729 I8RegNum = getX86RegEncoding(MI, CurOp++);

1730

1731 if (HasEVEX_RC)

1733 break;

1734 }

1736 emitByte(BaseOpcode, CB);

1737 unsigned SrcRegNum = CurOp + 1;

1738

1739 emitRegModRMByte(MI.getOperand(SrcRegNum),

1740 getX86RegNum(MI.getOperand(CurOp)), CB);

1741 CurOp = SrcRegNum + 1;

1742 ++CurOp;

1743 break;

1744 }

1746 emitByte(BaseOpcode, CB);

1747 unsigned SrcRegNum = CurOp + 1;

1748

1749

1750 ++SrcRegNum;

1751

1752

1753 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");

1754 I8RegNum = getX86RegEncoding(MI, SrcRegNum++);

1755

1756 emitRegModRMByte(MI.getOperand(SrcRegNum),

1757 getX86RegNum(MI.getOperand(CurOp)), CB);

1758 CurOp = SrcRegNum + 1;

1759 break;

1760 }

1762 if (IsND)

1763 ++CurOp;

1764 unsigned FirstOp = CurOp++;

1765 unsigned SecondOp = CurOp++;

1766

1767 unsigned CC = MI.getOperand(CurOp++).getImm();

1768 emitByte(BaseOpcode + CC, CB);

1769

1770 emitRegModRMByte(MI.getOperand(SecondOp),

1771 getX86RegNum(MI.getOperand(FirstOp)), CB);

1772 break;

1773 }

1776 unsigned FirstMemOp = CurOp + 1;

1777

1778 if (IsND)

1779 CurOp++;

1780

1781 if (HasEVEX_K)

1782 ++FirstMemOp;

1783

1784 if (HasVEX_4V)

1785 ++FirstMemOp;

1786

1787 emitByte(BaseOpcode, CB);

1788

1790 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),

1791 TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);

1793 if (HasVEX_I8Reg)

1794 I8RegNum = getX86RegEncoding(MI, CurOp++);

1795 break;

1796 }

1798 unsigned FirstMemOp = CurOp + 1;

1799

1800 emitByte(BaseOpcode, CB);

1801

1802 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),

1803 TSFlags, Kind, StartByte, CB, Fixups, STI);

1805 ++CurOp;

1806 break;

1807 }

1809 unsigned FirstMemOp = CurOp + 1;

1810

1811 ++FirstMemOp;

1812

1813

1814 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");

1815 I8RegNum = getX86RegEncoding(MI, FirstMemOp++);

1816

1817 emitByte(BaseOpcode, CB);

1818

1819 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),

1820 TSFlags, Kind, StartByte, CB, Fixups, STI);

1822 break;

1823 }

1825 if (IsND)

1826 ++CurOp;

1827 unsigned RegOp = CurOp++;

1828 unsigned FirstMemOp = CurOp;

1830

1831 unsigned CC = MI.getOperand(CurOp++).getImm();

1832 emitByte(BaseOpcode + CC, CB);

1833

1834 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),

1835 TSFlags, Kind, StartByte, CB, Fixups, STI);

1836 break;

1837 }

1838

1840 unsigned RegOp = CurOp++;

1841

1842 unsigned CC = MI.getOperand(CurOp++).getImm();

1843 emitByte(BaseOpcode + CC, CB);

1844 emitRegModRMByte(MI.getOperand(RegOp), 0, CB);

1845 break;

1846 }

1847

1857 if (HasVEX_4V)

1858 ++CurOp;

1859 if (HasEVEX_K)

1860 ++CurOp;

1861 emitByte(BaseOpcode, CB);

1862 emitRegModRMByte(MI.getOperand(CurOp++),

1864 break;

1866 emitByte(BaseOpcode, CB);

1867 emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)), 0), CB);

1868 break;

1869

1871 unsigned FirstMemOp = CurOp;

1873

1874 unsigned CC = MI.getOperand(CurOp++).getImm();

1875 emitByte(BaseOpcode + CC, CB);

1876

1877 emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Kind, StartByte, CB, Fixups,

1878 STI);

1879 break;

1880 }

1881

1891 if (HasVEX_4V)

1892 ++CurOp;

1893 if (HasEVEX_K)

1894 ++CurOp;

1895 emitByte(BaseOpcode, CB);

1896 emitMemModRMByte(MI, CurOp,

1898 Kind, StartByte, CB, Fixups, STI);

1900 break;

1901

1910 emitByte(BaseOpcode, CB);

1911 emitByte(0xC0 + ((Form - X86II::MRM0X) << 3), CB);

1912 break;

1913

1978 emitByte(BaseOpcode, CB);

1980 break;

1981 }

1982

1983 if (HasVEX_I8Reg) {

1984

1985

1986 assert(I8RegNum < 16 && "Register encoding out of range");

1987 I8RegNum <<= 4;

1988 if (CurOp != NumOps) {

1989 unsigned Val = MI.getOperand(CurOp++).getImm();

1990 assert(Val < 16 && "Immediate operand value out of range");

1991 I8RegNum |= Val;

1992 }

1994 StartByte, CB, Fixups);

1995 } else {

1996

1997

1998

1999

2000

2001 unsigned RemainingOps = NumOps - CurOp - 2 * HasTwoConditionalOps;

2002 while (RemainingOps) {

2003 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),

2006 --RemainingOps;

2007 }

2008 CurOp += 2 * HasTwoConditionalOps;

2009 }

2010

2013

2014 if (CB.size() - StartByte > 15)

2015 Ctx.reportError(MI.getLoc(), "instruction length exceeds the limit of 15");

2016#ifndef NDEBUG

2017

2018 if ( CurOp != NumOps) {

2019 errs() << "Cannot encode all operands of: ";

2021 errs() << '\n';

2022 abort();

2023 }

2024#endif

2025}

2026

2029 return new X86MCCodeEmitter(MCII, Ctx);

2030}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

if(auto Err=PB.parsePassPipeline(MPM, Passes)) return wrap(std MPM run * Mod

This file defines the SmallVector class.

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

static MCFixupKind getImmFixupKind(uint64_t TSFlags)

Definition X86MCCodeEmitter.cpp:442

static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII)

Definition X86MCCodeEmitter.cpp:505

static GlobalOffsetTableExprKind startsWithGlobalOffsetTable(const MCExpr *Expr)

Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is of the form GLOBAL_OFFSET_TABLE...

Definition X86MCCodeEmitter.cpp:477

static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM)

Definition X86MCCodeEmitter.cpp:401

static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset)

Determine if this immediate can fit in a disp8 or a compressed disp8 for EVEX instructions.

Definition X86MCCodeEmitter.cpp:418

GlobalOffsetTableExprKind

Definition X86MCCodeEmitter.cpp:466

@ GOT_Normal

Definition X86MCCodeEmitter.cpp:466

@ GOT_None

Definition X86MCCodeEmitter.cpp:466

@ GOT_SymDiff

Definition X86MCCodeEmitter.cpp:466

static void emitConstant(uint64_t Val, unsigned Size, SmallVectorImpl< char > &CB)

Definition X86MCCodeEmitter.cpp:406

static bool hasSecRelSymbolRef(const MCExpr *Expr)

Definition X86MCCodeEmitter.cpp:497

Binary assembler expressions.

const MCExpr * getLHS() const

Get the left-hand side expression of the binary operator.

static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())

const MCExpr * getRHS() const

Get the right-hand side expression of the binary operator.

MCCodeEmitter - Generic instruction encoding interface.

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

const MCRegisterInfo * getRegisterInfo() const

LLVM_ABI void reportError(SMLoc L, const Twine &Msg)

Base class for the full range of assembler expressions which are needed for parsing.

@ SymbolRef

References to labels and assigned expressions.

@ Binary

Binary expressions.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Instances of this class represent operands of the MCInst class.

static MCOperand createImm(int64_t Val)

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

uint16_t getEncodingValue(MCRegister Reg) const

Returns the encoding for Reg.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

Represent a reference to a symbol from inside an expression.

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

StringRef getName() const

getName - Get the symbol name.

Represents a location in source code.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

bool isX32() const

Tests whether the target is X32.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

bool hasImm(uint64_t TSFlags)

bool hasNewDataDest(uint64_t TSFlags)

bool isX86_64NonExtLowByteReg(MCRegister Reg)

@ MRM0X

MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but ignore r/m.

@ RawFrm

Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...

@ RawFrmDstSrc

RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...

@ EVEX

EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...

@ ExplicitREX2Prefix

For instructions that require REX2 prefix even if EGPR is not used.

@ MRMSrcMemCC

MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...

@ MRM_C0

MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.

@ RawFrmDst

RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.

@ MRMDestMem4VOp3CC

MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...

@ AddCCFrm

AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...

@ T_MAP4

MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.

@ PrefixByte

PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.

@ MRMr0

Instructions operate on a register Reg/Opcode operand not the r/m field.

@ MRMXm

MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...

@ MRM0r

MRM0r-MRM7r - Instructions that operate on a register r/m operand and use reg field to hold extended ...

@ MRMDestMemFSIB

MRMDestMem - But force to use the SIB field.

@ AddRegFrm

AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...

@ VEX

VEX - encoding using 0xC4/0xC5.

@ RawFrmImm8

RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...

@ TB

TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...

@ XOP

XOP - Opcode prefix used by XOP instructions.

@ MRMXr

MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...

@ MRMSrcMem4VOp3

MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....

@ XOP8

XOP8 - Prefix to include use of imm byte.

@ MRMDestRegCC

MRMDestRegCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...

@ PD

PD - Prefix code for packed double precision vector floating point operations performed in the SSE re...

@ MRMDestMem

MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...

@ MRMSrcMemFSIB

MRMSrcMem - But force to use the SIB field.

@ MRMSrcRegOp4

MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...

@ MRMXrCC

MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...

@ T8

T8, TA - Prefix after the 0x0F prefix.

@ MRMDestMemCC

MRMDestMemCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...

@ XOP9

XOP9 - Prefix to exclude use of imm byte.

@ MRMXmCC

MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...

@ RawFrmImm16

RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...

@ MRMSrcReg

MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...

@ RawFrmSrc

RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...

@ MRMDestReg

MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...

@ MRMSrcMem

MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...

@ MRMSrcMemOp4

MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...

@ Pseudo

PseudoFrm - This represents an instruction that is a pseudo instruction or one that has not been impl...

@ CD8_Scale_Shift

The scaling factor for the AVX512's 8-bit compressed displacement.

@ MRMSrcRegCC

MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...

@ MRM0m

MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use reg field to hold extended op...

@ ThreeDNow

ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!

@ XS

XS, XD - These prefix codes are for single and double precision scalar floating point operations perf...

@ XOPA

XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.

@ MRMSrcReg4VOp3

MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....

@ RawFrmMemOffs

RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...

bool isPseudo(uint64_t TSFlags)

bool isImmPCRel(uint64_t TSFlags)

unsigned getSizeOfImm(uint64_t TSFlags)

Decode the "size of immediate" field from the TSFlags field of the specified instruction.

bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode)

uint8_t getBaseOpcodeFor(uint64_t TSFlags)

int getMemoryOperandNo(uint64_t TSFlags)

bool isApxExtendedReg(MCRegister Reg)

unsigned getOperandBias(const MCInstrDesc &Desc)

Compute whether all of the def operands are repeated in the uses and therefore should be skipped.

bool isImmSigned(uint64_t TSFlags)

bool is16BitMemOperand(const MCInst &MI, unsigned Op, const MCSubtargetInfo &STI)

bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)

Returns true if this instruction needs an Address-Size override prefix.

void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)

Definition X86MCCodeEmitter.cpp:1547

EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(MCRegister Reg)

Given a segment register, return the encoding of the segment override prefix for it.

@ reloc_riprel_4byte_movq_load_rex2

@ reloc_signed_4byte_relax

@ reloc_branch_4byte_pcrel

@ reloc_riprel_4byte_relax

@ reloc_riprel_4byte_relax_evex

@ reloc_riprel_4byte_relax_rex

@ reloc_global_offset_table

@ reloc_riprel_4byte_movq_load

@ reloc_riprel_4byte_relax_rex2

BaseReg

Stack frame base register. Bit 0 of FREInfo.Info.

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Definition X86MCCodeEmitter.cpp:2027

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

static Lanai::Fixups FixupKind(const MCExpr *Expr)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

@ Ref

The access may reference the value stored in memory.

@ FirstLiteralRelocationKind

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_SecRel_4

A four-byte section relative fixup.

@ FK_Data_2

A two-byte fixup.

DWARFExpression::Operation Op

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.