X86TargetMachine.cpp Source File (original) (raw)

51#include

52#include

53#include

55using namespace llvm;

58 cl::desc("Enable the machine combiner pass"),

63 cl::desc("Enable the tile register allocation pass"),

108}

109

110static std::unique_ptr createTLOF(const Triple &TT) {

111 if (TT.isOSBinFormatMachO()) {

113 return std::make_unique<X86_64MachoTargetObjectFile>();

114 return std::make_unique();

115 }

116

117 if (TT.isOSBinFormatCOFF())

118 return std::make_unique();

119

121 return std::make_unique<X86_64ELFTargetObjectFile>();

122 return std::make_unique();

123}

124

126

127 std::string Ret = "e";

128

130

131 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())

132 Ret += "-p:32:32";

133

134

135 Ret += "-p270:32:32-p271:32:32-p272:64:64";

136

137

138

139

140 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())

141 Ret += "-i64:64-i128:128";

142 else if (TT.isOSIAMCU())

143 Ret += "-i64:32-f64:32";

144 else

145 Ret += "-i128:128-f64:32:64";

146

147

148 if (TT.isOSNaCl() || TT.isOSIAMCU())

149 ;

150 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())

151 Ret += "-f80:128";

152 else

153 Ret += "-f80:32";

154

155 if (TT.isOSIAMCU())

156 Ret += "-f128:32";

157

158

159 if (TT.isArch64Bit())

160 Ret += "-n8:16:32:64";

161 else

162 Ret += "-n8:16:32";

163

164

165 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())

166 Ret += "-a:0:32-S32";

167 else

168 Ret += "-S128";

169

170 return Ret;

171}

172

174 std::optionalReloc::Model RM) {

176 if (!RM) {

177

178

179 if (JIT)

181

182

183

184

185 if (TT.isOSDarwin()) {

189 }

190 if (TT.isOSWindows() && is64Bit)

193 }

194

195

196

197

198

202 if (!TT.isOSDarwin())

204 }

205

206

207

210

211 return *RM;

212}

213

216 bool JIT) {

218 if (CM) {

220 report_fatal_error("Target does not support the tiny CodeModel", false);

221 return *CM;

222 }

223 if (JIT)

226}

227

228

229

233 std::optionalReloc::Model RM,

234 std::optionalCodeModel::Model CM,

239 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {

240

241

242

243

244

245 if (TT.isPS() || TT.isOSBinFormatMachO()) {

248 }

249

251

252

254

256}

257

259

262 Attribute CPUAttr = F.getFnAttribute("target-cpu");

263 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

264 Attribute FSAttr = F.getFnAttribute("target-features");

265

268

269

270

272 : CPU == "x86-64" ? "generic"

276

278

279

280

281

282

283

284 unsigned PreferVectorWidthOverride = 0;

285 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");

286 if (PreferVecWidthAttr.isValid()) {

288 unsigned Width;

290 Key += 'p';

291 Key += Val;

292 PreferVectorWidthOverride = Width;

293 }

294 }

295

296

297 unsigned RequiredVectorWidth = UINT32_MAX;

298 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");

299 if (MinLegalVecWidthAttr.isValid()) {

301 unsigned Width;

303 Key += 'm';

304 Key += Val;

305 RequiredVectorWidth = Width;

306 }

307 }

308

309

310 Key += CPU;

311

312

313 Key += TuneCPU;

314

315

316 unsigned FSStart = Key.size();

317

318

319

320

321

322

323 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();

324

325

326 if (SoftFloat)

327 Key += FS.empty() ? "+soft-float" : "+soft-float,";

328

329 Key += FS;

330

331

332

333 FS = Key.substr(FSStart);

334

335 auto &I = SubtargetMap[Key];

336 if () {

337

338

339

341 I = std::make_unique(

343 MaybeAlign(F.getParent()->getOverrideStackAlignment()),

344 PreferVectorWidthOverride, RequiredVectorWidth);

345 }

346 return I.get();

347}

348

351}

352

357}

358

364 return false;

365}

366

368 unsigned DestAS) const {

369 assert(SrcAS != DestAS && "Expected different address spaces!");

371 return false;

372 return SrcAS < 256 && DestAS < 256;

373}

374

375void X86TargetMachine::reset() { SubtargetMap.clear(); }

376

377

378

379

380

384}

385

386

387

388

389

390namespace {

391

392

394public:

397

399 return getTM();

400 }

401

406 return DAG;

407 }

408

413 return DAG;

414 }

415

416 void addIRPasses() override;

417 bool addInstSelector() override;

418 bool addIRTranslator() override;

419 bool addLegalizeMachineIR() override;

420 bool addRegBankSelect() override;

421 bool addGlobalInstructionSelect() override;

422 bool addILPOpts() override;

423 bool addPreISel() override;

424 void addMachineSSAOptimization() override;

425 void addPreRegAlloc() override;

426 bool addPostFastRegAllocRewrite() override;

427 void addPostRegAlloc() override;

428 void addPreEmitPass() override;

429 void addPreEmitPass2() override;

430 void addPreSched2() override;

431 bool addRegAssignAndRewriteOptimized() override;

432

433 std::unique_ptr getCSEConfig() const override;

434};

435

437public:

438 static char ID;

440 StringRef getPassName() const override {

441 return "X86 Execution Dependency Fix";

442 }

443};

444char X86ExecutionDomainFix::ID;

445

446}

447

449 "X86 Execution Domain Fix", false, false)

453

455 return new X86PassConfig(*this, PM);

456}

457

461 return X86MachineFunctionInfo::create(Allocator, F,

463}

464

465void X86PassConfig::addIRPasses() {

467

468

469

472

474

478 }

479

480

481

482

484

485

486 const Triple &TT = TM->getTargetTriple();

487 if (TT.isOSWindows()) {

490 } else {

492 }

493 }

494

495 if (TM->Options.JMCInstrument)

497}

498

499bool X86PassConfig::addInstSelector() {

500

501 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));

502

503

504 if (TM->getTargetTriple().isOSBinFormatELF() &&

507

510 return false;

511}

512

513bool X86PassConfig::addIRTranslator() {

515 return false;

516}

517

518bool X86PassConfig::addLegalizeMachineIR() {

520 return false;

521}

522

523bool X86PassConfig::addRegBankSelect() {

525 return false;

526}

527

528bool X86PassConfig::addGlobalInstructionSelect() {

530

531 if (isGlobalISelAbortEnabled())

533 return false;

534}

535

536bool X86PassConfig::addILPOpts() {

541 return true;

542}

543

544bool X86PassConfig::addPreISel() {

545

546 const Triple &TT = TM->getTargetTriple();

549 return true;

550}

551

552void X86PassConfig::addPreRegAlloc() {

560 }

561

565

568 else

570}

571

572void X86PassConfig::addMachineSSAOptimization() {

575}

576

577void X86PassConfig::addPostRegAlloc() {

580

581

582

583

586}

587

588void X86PassConfig::addPreSched2() {

591}

592

593void X86PassConfig::addPreEmitPass() {

595 addPass(new X86ExecutionDomainFix());

597 }

598

600

602

609 }

614}

615

616void X86PassConfig::addPreEmitPass2() {

617 const Triple &TT = TM->getTargetTriple();

618 const MCAsmInfo *MAI = TM->getMCAsmInfo();

619

620

621

622

623

624

625

626

627

628

632

633

634

637

638

639

640

641 if (.isOSDarwin() &&

642 (.isOSWindows() ||

645

646 if (TT.isOSWindows()) {

647

649

651 }

653

654

656

657

658

660

661

663 const Module *M = F.getParent();

664 return M->getModuleFlag("kcfi") ||

665 (TT.isOSDarwin() &&

666 (M->getFunction("objc_retainAutoreleasedReturnValue") ||

667 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));

668 }));

669}

670

671bool X86PassConfig::addPostFastRegAllocRewrite() {

673 return true;

674}

675

676std::unique_ptr X86PassConfig::getCSEConfig() const {

678}

679

684 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(RC);

685}

686

687bool X86PassConfig::addRegAssignAndRewriteOptimized() {

688

690

693 }

695}

unsigned const MachineRegisterInfo * MRI

This file contains the simple types necessary to represent the attributes associated with functions a...

Provides analysis for continuously CSEing during GISel passes.

This file describes how to lower LLVM calls to machine code calls.

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

This file declares the IRTranslator pass.

static std::string computeDataLayout()

unsigned const TargetRegisterInfo * TRI

static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")

static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallString class.

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

static std::unique_ptr< TargetLoweringObjectFile > createTLOF()

static bool is64Bit(const char *name)

static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

static CodeModel::Model getEffectiveX86CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)

static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)

LLVM_C_ABI void LLVMInitializeX86Target()

static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)

This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.

StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

Allocate memory in an ever growing pool, as if by bump-pointer.

implements a set of functionality in the TargetMachine class for targets that make use of the indepen...

static const char * getManglingComponent(const Triple &T)

Lightweight error class with error context and mandatory checking.

This pass is responsible for selecting generic machine instructions to target-specific instructions.

This class is intended to be used as a base class for asm properties and features specific to the tar...

ExceptionHandling getExceptionHandlingType() const

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This class provides the reaching def analysis.

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

Wrapper class representing virtual and physical registers.

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

Add a postprocessing step to the DAG builder.

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

StringRef - Represent a constant reference to a string, i.e.

bool getAsInteger(unsigned Radix, T &Result) const

Parse the current string as an integer of the specified radix.

void setSupportsDebugEntryValues(bool Enable)

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

void setMachineOutliner(bool Enable)

unsigned getPointerSize(unsigned AS) const

Get the pointer size for this target.

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

unsigned NoTrapAfterNoreturn

Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...

unsigned TrapUnreachable

Emit target-specific trap instruction for 'unreachable' IR instructions.

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

virtual void addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

virtual bool addRegAssignAndRewriteOptimized()

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...

bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override

Returns true if a cast between SrcAS and DestAS is a noop.

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.

const X86Subtarget * getSubtargetImpl() const =delete

bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override

Parse out the target's MachineFunctionInfo from the YAML reprsentation.

~X86TargetMachine() override

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override

Allocate and return a default initialized instance of the YAML representation for the MachineFunction...

X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Create an X86 target.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

@ C

The default llvm calling convention, compatible with C.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ X86

Windows x64, Windows Itanium (IA-64)

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createX86FloatingPointStackifierPass()

This function returns a pass which converts floating-point register references and pseudo instruction...

FunctionPass * createIndirectBrExpandPass()

FunctionPass * createX86WinEHStatePass()

Return an IR pass that inserts EH registration stack objects and explicit EH state updates.

void initializeX86TileConfigPass(PassRegistry &)

void initializeX86PartialReductionPass(PassRegistry &)

void initializeX86CallFrameOptimizationPass(PassRegistry &)

void initializeFixupBWInstPassPass(PassRegistry &)

void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)

FunctionPass * createX86LoadValueInjectionLoadHardeningPass()

FunctionPass * createX86IssueVZeroUpperPass()

This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...

FunctionPass * createGreedyRegisterAllocator()

Greedy register allocation pass - This pass implements a global register allocator for optimized buil...

void initializeX86ArgumentStackSlotPassPass(PassRegistry &)

void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)

void initializeWinEHStatePassPass(PassRegistry &)

FunctionPass * createX86InsertPrefetchPass()

This pass applies profiling information to insert cache prefetches.

@ DwarfCFI

DWARF-like instruction based exceptions.

FunctionPass * createPseudoProbeInserter()

This pass inserts pseudo probe annotation for callsite profiling.

FunctionPass * createX86LowerAMXIntrinsicsPass()

The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...

Target & getTheX86_32Target()

FunctionPass * createX86GlobalBaseRegPass()

This pass initializes a global base register for PIC on x86-32.

FunctionPass * createX86FixupBWInsts()

Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...

void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)

FunctionPass * createX86DomainReassignmentPass()

Return a Machine IR pass that reassigns instruction chains from one domain to another,...

FunctionPass * createX86LoadValueInjectionRetHardeningPass()

FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()

FunctionPass * createCleanupLocalDynamicTLSPass()

This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...

FunctionPass * createX86FlagsCopyLoweringPass()

Return a pass that lowers EFLAGS copy pseudo instructions.

void initializeX86FastTileConfigPass(PassRegistry &)

FunctionPass * createCFGuardDispatchPass()

Insert Control FLow Guard dispatches on indirect function calls.

std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)

FunctionPass * createX86CompressEVEXPass()

This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...

void initializeX86ExpandPseudoPass(PassRegistry &)

void initializeX86AvoidTrailingCallPassPass(PassRegistry &)

ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)

Create the standard converging machine scheduler.

FunctionPass * createX86ArgumentStackSlotPass()

void initializeX86PreTileConfigPass(PassRegistry &)

char & EarlyIfConverterLegacyID

EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.

FunctionPass * createX86CmovConverterPass()

This pass converts X86 cmov instructions into branch when profitable.

FunctionPass * createX86TileConfigPass()

Return a pass that config the tile registers.

FunctionPass * createX86PadShortFunctions()

Return a pass that pads short functions with NOOPs.

void initializeX86DomainReassignmentPass(PassRegistry &)

void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)

FunctionPass * createX86FastPreTileConfigPass()

Return a pass that preconfig the tile registers before fast reg allocation.

ModulePass * createJMCInstrumenterPass()

JMC instrument pass.

std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()

Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...

void initializeX86AvoidSFBPassPass(PassRegistry &)

FunctionPass * createX86LowerTileCopyPass()

Return a pass that lower the tile copy instruction.

char & MachineCombinerID

This pass performs instruction combining using trace metrics to estimate critical-path and resource d...

void initializeX86FastPreTileConfigPass(PassRegistry &)

FunctionPass * createX86SpeculativeLoadHardeningPass()

FunctionPass * createX86FixupSetCC()

Return a pass that transforms setcc + movzx pairs into xor + setcc.

FunctionPass * createX86IndirectBranchTrackingPass()

This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...

FunctionPass * createX86InsertX87waitPass()

This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...

void initializeX86FixupSetCCPassPass(PassRegistry &)

FunctionPass * createKCFIPass()

Lowers KCFI operand bundles for indirect calls.

char & LiveRangeShrinkID

LiveRangeShrink pass.

FunctionPass * createX86ExpandPseudoPass()

Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

FunctionPass * createX86FixupInstTuning()

Return a pass that replaces equivalent slower instructions with faster ones.

FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)

This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.

void initializeX86LowerTileCopyPass(PassRegistry &)

void initializeX86OptimizeLEAPassPass(PassRegistry &)

CodeGenOptLevel

Code generation optimization level.

FunctionPass * createX86FastTileConfigPass()

Return a pass that config the tile registers after fast reg allocation.

FunctionPass * createCFGuardLongjmpPass()

Creates CFGuard longjmp target identification pass.

FunctionPass * createX86PartialReductionPass()

This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...

FunctionPass * createX86FixupLEAs()

Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...

FunctionPass * createInterleavedAccessPass()

InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...

void initializeGlobalISel(PassRegistry &)

Initialize all passes linked into the GlobalISel library.

ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)

Create a generic scheduler with no vreg liveness or DAG mutation passes.

void initializeX86FixupInstTuningPassPass(PassRegistry &)

void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)

void initializeX86CmovConverterPassPass(PassRegistry &)

FunctionPass * createBreakFalseDeps()

Creates Break False Dependencies pass.

FunctionPass * createX86CallFrameOptimization()

Return a pass that optimizes the code-size of x86 call sequences.

void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)

void initializeFPSPass(PassRegistry &)

FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)

FunctionPass * createX86AvoidTrailingCallPass()

Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.

FunctionPass * createX86DynAllocaExpander()

Return a pass that expands DynAlloca pseudo-instructions.

void initializeKCFIPass(PassRegistry &)

void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)

void initializeCompressEVEXPassPass(PassRegistry &)

FunctionPass * createCFGuardCheckPass()

Insert Control FLow Guard checks on indirect function calls.

FunctionPass * createX86OptimizeLEAs()

Return a pass that removes redundant LEA instructions and redundant address recalculations.

void initializeX86FixupVectorConstantsPassPass(PassRegistry &)

FunctionPass * createX86LowerAMXTypePass()

The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...

FunctionPass * createCFIInstrInserter()

Creates CFI Instruction Inserter pass.

FunctionPass * createX86WinFixupBufferSecurityCheckPass()

Return a pass that transform inline buffer security check into seperate bb.

FunctionPass * createX86IndirectThunksPass()

This pass creates the thunks for the retpoline feature.

FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

FunctionPass * createEHContGuardCatchretPass()

Creates EHContGuard catchret target identification pass.

void initializeX86DynAllocaExpanderPass(PassRegistry &)

Target & getTheX86_64Target()

void initializePseudoProbeInserterPass(PassRegistry &)

FunctionPass * createX86FixupVectorConstants()

Return a pass that reduces the size of vector constant pool loads.

void initializeX86ExecutionDomainFixPass(PassRegistry &)

FunctionPass * createX86PreTileConfigPass()

Return a pass that insert pseudo tile config instruction.

FunctionPass * createX86ReturnThunksPass()

This pass replaces ret instructions with jmp's to __x86_return thunk.

FunctionPass * createX86AvoidStoreForwardingBlocks()

Return a pass that avoids creating store forward block issues in the hardware.

void initializeX86ReturnThunksPass(PassRegistry &)

void initializeX86DAGToDAGISelLegacyPass(PassRegistry &)

FunctionPass * createX86DiscriminateMemOpsPass()

This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...

void initializeFixupLEAPassPass(PassRegistry &)

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.

RegisterTargetMachine - Helper template for registering a target machine implementation,...

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.