X86TargetMachine.cpp Source File (original) (raw)

51#include

52#include

54using namespace llvm;

57 cl::desc("Enable the machine combiner pass"),

62 cl::desc("Enable the tile register allocation pass"),

111

112static std::unique_ptr createTLOF(const Triple &TT) {

113 if (TT.isOSBinFormatMachO()) {

114 if (TT.isX86_64())

115 return std::make_unique<X86_64MachoTargetObjectFile>();

116 return std::make_unique();

117 }

118

119 if (TT.isOSBinFormatCOFF())

120 return std::make_unique();

121

122 if (TT.isX86_64())

123 return std::make_unique<X86_64ELFTargetObjectFile>();

124 return std::make_unique();

125}

126

128 std::optionalReloc::Model RM) {

129 bool is64Bit = TT.isX86_64();

130 if (!RM) {

131

132

133 if (JIT)

135

136

137

138

139 if (TT.isOSDarwin()) {

143 }

144 if (TT.isOSWindows() && is64Bit)

147 }

148

149

150

151

152

156 if (!TT.isOSDarwin())

158 }

159

160

161

164

165 return *RM;

166}

167

170 bool JIT) {

171 bool Is64Bit = TT.isX86_64();

172 if (CM) {

175 return *CM;

176 }

177 if (JIT)

180}

181

182

183

187 std::optionalReloc::Model RM,

188 std::optionalCodeModel::Model CM,

194

195

196

197

198

199 if (TT.isPS() || TT.isOSBinFormatMachO()) {

200 this->Options.TrapUnreachable = true;

201 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();

202 }

203

205

206

208

210}

211

213

216 Attribute CPUAttr = F.getFnAttribute("target-cpu");

217 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

218 Attribute FSAttr = F.getFnAttribute("target-features");

219

222

223

224

226 : CPU == "x86-64" ? "generic"

230

232

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234

235

236

237

238 unsigned PreferVectorWidthOverride = 0;

239 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");

240 if (PreferVecWidthAttr.isValid()) {

242 unsigned Width;

244 Key += 'p';

245 Key += Val;

246 PreferVectorWidthOverride = Width;

247 }

248 }

249

250

251 unsigned RequiredVectorWidth = UINT32_MAX;

252 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");

253 if (MinLegalVecWidthAttr.isValid()) {

255 unsigned Width;

257 Key += 'm';

258 Key += Val;

259 RequiredVectorWidth = Width;

260 }

261 }

262

263

264 Key += CPU;

265

266

267 Key += TuneCPU;

268

269

270 unsigned FSStart = Key.size();

271

272

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274

275

276

277 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();

278

279

280 if (SoftFloat)

281 Key += FS.empty() ? "+soft-float" : "+soft-float,";

282

283 Key += FS;

284

285

286

287 FS = Key.substr(FSStart);

288

289 auto &I = SubtargetMap[Key];

290 if () {

291

292

293

295 I = std::make_unique(

297 MaybeAlign(F.getParent()->getOverrideStackAlignment()),

298 PreferVectorWidthOverride, RequiredVectorWidth);

299 }

300 return I.get();

301}

302

306

312

320

322 unsigned DestAS) const {

323 assert(SrcAS != DestAS && "Expected different address spaces!");

325 return false;

326 return SrcAS < 256 && DestAS < 256;

327}

328

330

337

344

345

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348

353

354

355

356

357

358namespace {

359

360

362public:

365

368 }

369

370 void addIRPasses() override;

371 bool addInstSelector() override;

372 bool addIRTranslator() override;

373 bool addLegalizeMachineIR() override;

374 bool addRegBankSelect() override;

375 bool addGlobalInstructionSelect() override;

376 bool addILPOpts() override;

377 bool addPreISel() override;

378 void addMachineSSAOptimization() override;

379 void addPreRegAlloc() override;

380 bool addPostFastRegAllocRewrite() override;

381 void addPostRegAlloc() override;

382 void addPreEmitPass() override;

383 void addPreEmitPass2() override;

384 void addPreSched2() override;

385 bool addRegAssignAndRewriteOptimized() override;

386

387 std::unique_ptr getCSEConfig() const override;

388};

389

391public:

392 static char ID;

393 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}

394 StringRef getPassName() const override {

395 return "X86 Execution Dependency Fix";

396 }

397};

398char X86ExecutionDomainFix::ID;

399

400}

401

403 "X86 Execution Domain Fix", false, false)

407

409 return new X86PassConfig(*this, PM);

410}

411

418

419void X86PassConfig::addIRPasses() {

421

422

423

426

428

432 }

433

434

435

436

438

439

440 const Triple &TT = TM->getTargetTriple();

441 if (TT.isOSWindows()) {

442 if (TT.isX86_64()) {

444 } else {

446 }

447 }

448

449 if (TM->Options.JMCInstrument)

451}

452

453bool X86PassConfig::addInstSelector() {

454

455 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));

456

457

458 if (TM->getTargetTriple().isOSBinFormatELF() &&

461

464 return false;

465}

466

467bool X86PassConfig::addIRTranslator() {

469 return false;

470}

471

472bool X86PassConfig::addLegalizeMachineIR() {

474 return false;

475}

476

477bool X86PassConfig::addRegBankSelect() {

479 return false;

480}

481

482bool X86PassConfig::addGlobalInstructionSelect() {

484

485 if (isGlobalISelAbortEnabled())

487 return false;

488}

489

490bool X86PassConfig::addILPOpts() {

495 return true;

496}

497

498bool X86PassConfig::addPreISel() {

499

500 const Triple &TT = TM->getTargetTriple();

501 if (TT.isOSWindows() && TT.isX86_32())

503 return true;

504}

505

506void X86PassConfig::addPreRegAlloc() {

513 }

514

516

520

523 else

525}

526

527void X86PassConfig::addMachineSSAOptimization() {

530}

531

532void X86PassConfig::addPostRegAlloc() {

535

536

537

538

541}

542

543void X86PassConfig::addPreSched2() {

546}

547

548void X86PassConfig::addPreEmitPass() {

550 addPass(new X86ExecutionDomainFix());

552 }

553

555

557

564 }

567}

568

569void X86PassConfig::addPreEmitPass2() {

570 const Triple &TT = TM->getTargetTriple();

571 const MCAsmInfo *MAI = TM->getMCAsmInfo();

572

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586

587

588 if (TT.isOSWindows() && TT.isX86_64())

590

591

592

593

594 if (.isOSDarwin() &&

595 (.isOSWindows() ||

598

599 if (TT.isOSWindows()) {

600

602

604 }

606

607

609

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613

614

616 const Module *M = F.getParent();

617 return M->getModuleFlag("kcfi") ||

618 (TT.isOSDarwin() &&

619 (M->getFunction("objc_retainAutoreleasedReturnValue") ||

620 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));

621 }));

622

623

624

625 if (TT.isOSWindows() && TT.isX86_64())

627}

628

629bool X86PassConfig::addPostFastRegAllocRewrite() {

631 return true;

632}

633

634std::unique_ptr X86PassConfig::getCSEConfig() const {

636}

637

644

645bool X86PassConfig::addRegAssignAndRewriteOptimized() {

646

648

651 }

653}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)

static Reloc::Model getEffectiveRelocModel()

This file contains the simple types necessary to represent the attributes associated with functions a...

Provides analysis for continuously CSEing during GISel passes.

This file describes how to lower LLVM calls to machine code calls.

This file declares the IRTranslator pass.

static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

const GCNTargetMachine & getTM(const GCNSubtarget *STI)

This file defines the SmallString class.

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

static std::unique_ptr< TargetLoweringObjectFile > createTLOF()

#define LLVM_C_ABI

LLVM_C_ABI is the export/visibility macro used to mark symbols declared in llvm-c as exported when bu...

static bool is64Bit(const char *name)

static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

static CodeModel::Model getEffectiveX86CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)

Definition X86TargetMachine.cpp:169

static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)

Definition X86TargetMachine.cpp:638

LLVM_C_ABI void LLVMInitializeX86Target()

Definition X86TargetMachine.cpp:65

This file a TargetTransformInfoImplBase conforming object specific to the X86 target machine.

Functions, function parameters, and return types can have attributes to indicate how they should be t...

LLVM_ABI StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)

virtual void reset()

Reset internal state.

Lightweight error class with error context and mandatory checking.

This pass is responsible for selecting generic machine instructions to target-specific instructions.

This class is intended to be used as a base class for asm properties and features specific to the tar...

ExceptionHandling getExceptionHandlingType() const

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A Module instance is used to store all the information related to an LLVM module.

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

Wrapper class representing virtual and physical registers.

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

Add a postprocessing step to the DAG builder.

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

StringRef - Represent a constant reference to a string, i.e.

bool getAsInteger(unsigned Radix, T &Result) const

Parse the current string as an integer of the specified radix.

void setSupportsDebugEntryValues(bool Enable)

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

const Triple & getTargetTriple() const

void setMachineOutliner(bool Enable)

unsigned getPointerSize(unsigned AS) const

Get the pointer size for this target.

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

virtual void addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

virtual bool addRegAssignAndRewriteOptimized()

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...

bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override

Returns true if a cast between SrcAS and DestAS is a noop.

Definition X86TargetMachine.cpp:321

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

Definition X86TargetMachine.cpp:412

yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.

Definition X86TargetMachine.cpp:308

const X86Subtarget * getSubtargetImpl() const =delete

ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...

Definition X86TargetMachine.cpp:332

ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Definition X86TargetMachine.cpp:339

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

Definition X86TargetMachine.cpp:408

bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override

Parse out the target's MachineFunctionInfo from the YAML reprsentation.

Definition X86TargetMachine.cpp:313

~X86TargetMachine() override

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

Definition X86TargetMachine.cpp:350

yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override

Allocate and return a default initialized instance of the YAML representation for the MachineFunction...

Definition X86TargetMachine.cpp:303

X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Create an X86 target.

Definition X86TargetMachine.cpp:184

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

@ X86

Windows x64, Windows Itanium (IA-64)

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)

Create the standard converging machine scheduler.

LLVM_ABI FunctionPass * createIndirectBrExpandPass()

FunctionPass * createX86WinEHStatePass()

Return an IR pass that inserts EH registration stack objects and explicit EH state updates.

void initializeX86TileConfigPass(PassRegistry &)

FunctionPass * createX86LowerAMXIntrinsicsLegacyPass()

void initializeX86PartialReductionLegacyPass(PassRegistry &)

FunctionPass * createX86SuppressAPXForRelocationPass()

void initializeX86CallFrameOptimizationPass(PassRegistry &)

LLVM_ABI ModulePass * createJMCInstrumenterPass()

JMC instrument pass.

void initializeFixupBWInstPassPass(PassRegistry &)

void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)

FunctionPass * createX86LoadValueInjectionLoadHardeningPass()

FunctionPass * createX86IssueVZeroUpperPass()

This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...

LLVM_ABI FunctionPass * createGreedyRegisterAllocator()

Greedy register allocation pass - This pass implements a global register allocator for optimized buil...

void initializeX86ArgumentStackSlotPassPass(PassRegistry &)

void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)

FunctionPass * createX86DynAllocaExpanderLegacyPass()

void initializeWinEHStatePassPass(PassRegistry &)

@ DwarfCFI

DWARF-like instruction based exceptions.

LLVM_ABI FunctionPass * createPseudoProbeInserter()

This pass inserts pseudo probe annotation for callsite profiling.

Target & getTheX86_32Target()

FunctionPass * createX86GlobalBaseRegPass()

This pass initializes a global base register for PIC on x86-32.

FunctionPass * createX86FixupBWInsts()

Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...

void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)

FunctionPass * createX86DomainReassignmentPass()

Return a Machine IR pass that reassigns instruction chains from one domain to another,...

FunctionPass * createX86LoadValueInjectionRetHardeningPass()

FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()

FunctionPass * createX86PartialReductionLegacyPass()

FunctionPass * createCleanupLocalDynamicTLSPass()

This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...

FunctionPass * createX86FlagsCopyLoweringPass()

Return a pass that lowers EFLAGS copy pseudo instructions.

void initializeX86DynAllocaExpanderLegacyPass(PassRegistry &)

void initializeX86FastTileConfigPass(PassRegistry &)

FunctionPass * createCFGuardDispatchPass()

Insert Control FLow Guard dispatches on indirect function calls.

LLVM_ABI std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)

FunctionPass * createX86CompressEVEXPass()

This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...

void initializeX86ExpandPseudoPass(PassRegistry &)

FunctionPass * createX86ArgumentStackSlotPass()

void initializeX86PreTileConfigPass(PassRegistry &)

LLVM_ABI char & EarlyIfConverterLegacyID

EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.

FunctionPass * createX86CmovConverterPass()

This pass converts X86 cmov instructions into branch when profitable.

FunctionPass * createX86TileConfigPass()

Return a pass that config the tile registers.

FunctionPass * createX86PadShortFunctions()

Return a pass that pads short functions with NOOPs.

void initializeX86DomainReassignmentPass(PassRegistry &)

void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)

void initializeX86SuppressAPXForRelocationPassPass(PassRegistry &)

FunctionPass * createX86FastPreTileConfigPass()

Return a pass that preconfig the tile registers before fast reg allocation.

std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()

Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86TargetMachine::c...

void initializeX86AvoidSFBPassPass(PassRegistry &)

FunctionPass * createX86LowerTileCopyPass()

Return a pass that lower the tile copy instruction.

LLVM_ABI char & MachineCombinerID

This pass performs instruction combining using trace metrics to estimate critical-path and resource d...

void initializeX86FastPreTileConfigPass(PassRegistry &)

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

FunctionPass * createX86SpeculativeLoadHardeningPass()

FunctionPass * createX86FixupSetCC()

Return a pass that transforms setcc + movzx pairs into xor + setcc.

FunctionPass * createX86IndirectBranchTrackingPass()

This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...

void initializeX86AsmPrinterPass(PassRegistry &)

FunctionPass * createX86InsertX87waitPass()

This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...

ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)

Create a generic scheduler with no vreg liveness or DAG mutation passes.

void initializeX86FixupSetCCPassPass(PassRegistry &)

LLVM_ABI FunctionPass * createKCFIPass()

Lowers KCFI operand bundles for indirect calls.

LLVM_ABI char & LiveRangeShrinkID

LiveRangeShrink pass.

FunctionPass * createX86ExpandPseudoPass()

Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...

FunctionPass * createX86FixupInstTuning()

Return a pass that replaces equivalent slower instructions with faster ones.

void initializeX86AvoidTrailingCallLegacyPassPass(PassRegistry &)

void initializeX86WinEHUnwindV2Pass(PassRegistry &)

FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)

This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.

void initializeX86LowerTileCopyPass(PassRegistry &)

void initializeX86OptimizeLEAPassPass(PassRegistry &)

LLVM_ABI void initializePseudoProbeInserterPass(PassRegistry &)

CodeGenOptLevel

Code generation optimization level.

LLVM_ABI FunctionPass * createCFGuardLongjmpPass()

Creates CFGuard longjmp target identification pass.

LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key

FunctionPass * createX86FastTileConfigPass()

Return a pass that config the tile registers after fast reg allocation.

void initializeX86FPStackifierLegacyPass(PassRegistry &)

FunctionPass * createX86FixupLEAs()

Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...

LLVM_ABI FunctionPass * createInterleavedAccessPass()

InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...

LLVM_ABI void initializeGlobalISel(PassRegistry &)

Initialize all passes linked into the GlobalISel library.

LLVM_ABI void initializeKCFIPass(PassRegistry &)

void initializeX86FixupInstTuningPassPass(PassRegistry &)

void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)

void initializeX86CmovConverterPassPass(PassRegistry &)

LLVM_ABI FunctionPass * createBreakFalseDeps()

Creates Break False Dependencies pass.

FunctionPass * createX86CallFrameOptimization()

Return a pass that optimizes the code-size of x86 call sequences.

FunctionPass * createX86FPStackifierLegacyPass()

void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)

LLVM_ABI FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)

FunctionPass * createX86WinEHUnwindV2Pass()

// Analyzes and emits pseudos to support Win x64 Unwind V2.

FunctionPass * createX86LowerAMXTypeLegacyPass()

void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)

void initializeCompressEVEXPassPass(PassRegistry &)

FunctionPass * createCFGuardCheckPass()

Insert Control FLow Guard checks on indirect function calls.

LLVM_ABI FunctionPass * createEHContGuardTargetsPass()

Creates Windows EH Continuation Guard target identification pass.

FunctionPass * createX86OptimizeLEAs()

Return a pass that removes redundant LEA instructions and redundant address recalculations.

void initializeX86FixupVectorConstantsPassPass(PassRegistry &)

FunctionPass * createX86IndirectThunksPass()

This pass creates the thunks for the retpoline feature.

LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

Target & getTheX86_64Target()

FunctionPass * createX86FixupVectorConstants()

Return a pass that reduces the size of vector constant pool loads.

LLVM_ABI FunctionPass * createCFIInstrInserter()

Creates CFI Instruction Inserter pass.

void initializeX86ExecutionDomainFixPass(PassRegistry &)

FunctionPass * createX86PreTileConfigPass()

Return a pass that insert pseudo tile config instruction.

FunctionPass * createX86ReturnThunksPass()

This pass replaces ret instructions with jmp's to __x86_return thunk.

FunctionPass * createX86AvoidStoreForwardingBlocks()

Return a pass that avoids creating store forward block issues in the hardware.

void initializeX86ReturnThunksPass(PassRegistry &)

void initializeX86DAGToDAGISelLegacyPass(PassRegistry &)

void initializeFixupLEAPassPass(PassRegistry &)

FunctionPass * createX86AvoidTrailingCallLegacyPass()

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)

Factory function: default behavior is to call new using the supplied allocator.

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.

RegisterTargetMachine - Helper template for registering a target machine implementation,...

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.