XCoreISelLowering.cpp Source File (original) (raw)

32#include "llvm/IR/IntrinsicsXCore.h"

37#include

39using namespace llvm;

41#define DEBUG_TYPE "xcore-lower"

45{

47 {

66 }

67 return nullptr;

68}

102

103

108

110

111

113

116

117

119

120

125

128 }

129

130

133

134

139

140

144

145

148

150

151

154

155

157

161

162

165

168

169

171}

172

175 return false;

176

180 return false;

181

183 default: break;

184 case MVT::i8:

185 return true;

186 }

187

188 return false;

189}

190

193 switch (Op.getOpcode())

194 {

200 case ISD::LOAD: return LowerLOAD(Op, DAG);

206

208 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);

216 return LowerATOMIC_FENCE(Op, DAG);

217 default:

219 }

220}

221

222

223

227 switch (N->getOpcode()) {

228 default:

232 Results.push_back(ExpandADDSUB(N, DAG));

233 return;

234 }

235}

236

237

238

239

240

241SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,

244

246

249

250 const auto *GVar = dyn_cast(GV);

254

256}

257

260 return true;

261

264 return false;

265

267 unsigned ObjSize = DL.getTypeAllocSize(ObjType);

269}

270

271SDValue XCoreTargetLowering::

273{

279

280 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0);

282 GA = getGlobalAddressWrapper(GA, GV, DAG);

283

284 if (Offset != FoldedOffset) {

288 }

289 return GA;

290 } else {

291

299 }

300}

301

302SDValue XCoreTargetLowering::

304{

307 const BlockAddress *BA = cast(Op)->getBlockAddress();

309

311}

312

313SDValue XCoreTargetLowering::

315{

317

319 EVT PtrVT = Op.getValueType();

321 if (CP->isMachineConstantPoolEntry()) {

323 CP->getAlign(), CP->getOffset());

324 } else {

326 CP->getOffset());

327 }

329}

330

333}

334

335SDValue XCoreTargetLowering::

337{

338 SDValue Chain = Op.getOperand(0);

339 SDValue Table = Op.getOperand(1);

340 SDValue Index = Op.getOperand(2);

343 unsigned JTI = JT->getIndex();

347

348 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();

349 if (NumEntries <= 32) {

351 }

352 assert((NumEntries >> 31) == 0);

356 ScaledIndex);

357}

358

359SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset(

363 if ((Offset & 0x3) == 0) {

365 }

366

368 int32_t LowOffset = HighOffset - 4;

369 SDValue LowAddr, HighAddr;

371 dyn_cast(Base.getNode())) {

373 LowOffset);

375 HighOffset);

376 } else {

381 }

384

391 High.getValue(1));

394}

395

397{

400}

401

407 "Unexpected extension type");

408 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");

409

411 LD->getMemoryVT(), *LD->getMemOperand()))

413

417

418 if (->isVolatile()) {

424 Offset = cast(BasePtr->getOperand(1))->getSExtValue();

425 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,

427 }

431 BasePtr->getValueType(0));

432 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,

434 }

435 }

436

437 if (LD->getAlign() == Align(2)) {

439 LD->getPointerInfo(), MVT::i16, Align(2),

440 LD->getMemOperand()->getFlags());

445 LD->getPointerInfo().getWithOffset(2), MVT::i16,

446 Align(2), LD->getMemOperand()->getFlags());

451 High.getValue(1));

454 }

455

456

460

461 Entry.Ty = IntPtrTy;

463 Args.push_back(Entry);

464

466 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(

470 std::move(Args));

471

472 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);

473 SDValue Ops[] = { CallResult.first, CallResult.second };

475}

476

480 assert(->isTruncatingStore() && "Unexpected store type");

481 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");

482

484 ST->getMemoryVT(), *ST->getMemOperand()))

486

491

492 if (ST->getAlign() == Align(2)) {

498 MVT::i16, Align(2), ST->getMemOperand()->getFlags());

502 Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2),

503 MVT::i16, Align(2), ST->getMemOperand()->getFlags());

505 }

506

507

511

512 Entry.Ty = IntPtrTy;

514 Args.push_back(Entry);

515

517 Args.push_back(Entry);

518

520 CLI.setDebugLoc(dl).setChain(Chain).setCallee(

524 std::move(Args));

525

526 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);

527 return CallResult.second;

528}

529

530SDValue XCoreTargetLowering::

532{

534 "Unexpected operand to lower!");

540 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,

541 LHS, RHS);

545}

546

547SDValue XCoreTargetLowering::

549{

551 "Unexpected operand to lower!");

557 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,

558 Zero, Zero);

562}

563

564

565

566

567

568

569static bool

571 SDValue &Addend1, bool requireIntermediatesHaveOneUse)

572{

574 return false;

580 AddOp = N0;

581 OtherOp = N1;

583 AddOp = N1;

584 OtherOp = N0;

585 } else {

586 return false;

587 }

588 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())

589 return false;

591

592 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())

593 return false;

598 return true;

599 }

601

603 return false;

607 Addend1 = OtherOp;

608 return true;

609 }

611

613 return false;

617 Addend1 = OtherOp;

618 return true;

619 }

620 return false;

621}

622

623SDValue XCoreTargetLowering::

625{

628 if (N->getOperand(0).getOpcode() == ISD::MUL) {

629 Mul = N->getOperand(0);

630 Other = N->getOperand(1);

631 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {

632 Mul = N->getOperand(1);

633 Other = N->getOperand(0);

634 } else {

636 }

638 SDValue LL, RL, AddendL, AddendH;

640 Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));

642 Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));

652

654 DAG.getVTList(MVT::i32, MVT::i32), AddendH,

655 AddendL, LL, RL);

658 }

659 if (LHSSB > 32 && RHSSB > 32) {

660

662 DAG.getVTList(MVT::i32, MVT::i32), AddendH,

663 AddendL, LL, RL);

666 }

669 Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));

671 Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));

673 DAG.getVTList(MVT::i32, MVT::i32), AddendH,

674 AddendL, LL, RL);

681}

682

683SDValue XCoreTargetLowering::

685{

686 assert(N->getValueType(0) == MVT::i64 &&

688 "Unknown operand to lower!");

689

691 if (SDValue Result = TryExpandADDWithMul(N, DAG))

693

695

696

698 N->getOperand(0),

701 N->getOperand(0),

704 N->getOperand(1),

707 N->getOperand(1),

709

710

715 LHSL, RHSL, Zero);

717

719 LHSH, RHSH, Carry);

720 SDValue Ignored(Hi.getNode(), 1);

721

723}

724

725SDValue XCoreTargetLowering::

727{

728

729

731 EVT VT = Node->getValueType(0);

735 const Value *SV = cast(Node->getOperand(2))->getValue();

739

742 dl));

743

744 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,

746

748}

749

750SDValue XCoreTargetLowering::

752{

754

755

759 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),

761}

762

765

766

767

768

769

770 if (Op.getConstantOperandVal(0) > 0)

772

776 RegInfo->getFrameRegister(MF), MVT::i32);

777}

778

779SDValue XCoreTargetLowering::

781

782

783

784

785

786 if (Op.getConstantOperandVal(0) > 0)

788

796}

797

798SDValue XCoreTargetLowering::

800

801

802

803

805}

806

807SDValue XCoreTargetLowering::

809

810

811

812

814 SDValue Chain = Op.getOperand(0);

816 SDValue Handler = Op.getOperand(2);

818

819

822 RegInfo->getFrameRegister(MF), MVT::i32);

824 MVT::i32);

827

828

829

830 unsigned StackReg = XCore::R2;

831 unsigned HandlerReg = XCore::R3;

832

834 DAG.getCopyToReg(Chain, dl, StackReg, Stack),

835 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)

836 };

837

839

843

844}

845

846SDValue XCoreTargetLowering::

848 return Op.getOperand(0);

849}

850

851SDValue XCoreTargetLowering::

853 SDValue Chain = Op.getOperand(0);

854 SDValue Trmp = Op.getOperand(1);

855 SDValue FPtr = Op.getOperand(2);

856 SDValue Nest = Op.getOperand(3);

857

858 const Value *TrmpAddr = cast(Op.getOperand(4))->getValue();

859

860

861

862

863

864

865

866

867

868

869

870

872

874

876 OutChains[0] =

879

882 OutChains[1] =

885

888 OutChains[2] =

891

894 OutChains[3] =

896

899 OutChains[4] =

901

903}

904

905SDValue XCoreTargetLowering::

908 unsigned IntNo = Op.getConstantOperandVal(0);

909 switch (IntNo) {

910 case Intrinsic::xcore_crc8:

911 EVT VT = Op.getValueType();

914 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));

918 }

920}

921

922SDValue XCoreTargetLowering::

926}

927

928

929

930

931

932#include "XCoreGenCallingConv.inc"

933

934

935

936

937

938

951 bool isVarArg = CLI.IsVarArg;

952

953

954 isTailCall = false;

955

956

957 switch (CallConv)

958 {

959 default:

963 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,

964 Outs, OutVals, Ins, dl, DAG, InVals);

965 }

966}

967

968

969

975

977 if (VA.isRegLoc()) {

978 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),

982 } else {

983 assert(VA.isMemLoc());

984 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),

985 InVals.size()));

986

988 }

989 }

990

991

993 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {

994 int offset = ResultMemLocs[i].first;

995 unsigned index = ResultMemLocs[i].second;

997 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };

999 InVals[index] = load;

1001 }

1002

1003

1004

1005 if (!MemOpChains.empty())

1007

1008 return Chain;

1009}

1010

1011

1012

1013

1014

1015SDValue XCoreTargetLowering::LowerCCCCallTo(

1021

1022

1026

1027

1028

1029 CCInfo.AllocateStack(4, Align(4));

1030

1031 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);

1032

1034

1037 RetCCInfo.AllocateStack(CCInfo.getStackSize(), Align(4));

1038 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);

1039

1040

1041 unsigned NumBytes = RetCCInfo.getStackSize();

1042

1044

1047

1048

1049 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

1051 SDValue Arg = OutVals[i];

1052

1053

1059 break;

1062 break;

1065 break;

1066 }

1067

1068

1069

1072 } else {

1074

1076

1078 Chain, Arg,

1080 MVT::i32)));

1081 }

1082 }

1083

1084

1085

1086 if (!MemOpChains.empty())

1088

1089

1090

1091

1092

1094 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {

1095 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,

1096 RegsToPass[i].second, InGlue);

1098 }

1099

1100

1101

1102

1107

1108

1109

1110

1111

1116

1117

1118

1119 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)

1121 RegsToPass[i].second.getValueType()));

1122

1125

1128

1129

1130 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InGlue, dl);

1132

1133

1134

1135 return LowerCallResult(Chain, InGlue, RVLocs, dl, DAG, InVals);

1136}

1137

1138

1139

1140

1141

1142namespace {

1144}

1145

1146

1147SDValue XCoreTargetLowering::LowerFormalArguments(

1151 switch (CallConv)

1152 {

1153 default:

1157 return LowerCCCArguments(Chain, CallConv, isVarArg,

1158 Ins, dl, DAG, InVals);

1159 }

1160}

1161

1162

1163

1164

1165

1166SDValue XCoreTargetLowering::LowerCCCArguments(

1174

1175

1179

1180 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);

1181

1183

1184 unsigned LRSaveSize = StackSlotSize;

1185

1186 if (!isVarArg)

1188

1189

1190

1191

1192

1193

1194

1195

1199

1200

1201 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

1202

1205

1207

1210 default:

1211 {

1212#ifndef NDEBUG

1213 errs() << "LowerFormalArguments Unhandled argument type: "

1214 << RegVT << "\n";

1215#endif

1217 }

1218 case MVT::i32:

1219 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);

1223 }

1224 } else {

1225

1227

1229 if (ObjSize > StackSlotSize) {

1230 errs() << "LowerFormalArguments Unhandled argument type: "

1232 }

1233

1236 true);

1237

1238

1239

1243 }

1244 const ArgDataPair ADP = { ArgIn, Ins[i].Flags };

1246 }

1247

1248

1249 if (isVarArg) {

1250

1251 static const MCPhysReg ArgRegs[] = {

1252 XCore::R0, XCore::R1, XCore::R2, XCore::R3

1253 };

1255 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);

1256 if (FirstVAReg < std::size(ArgRegs)) {

1257 int offset = 0;

1258

1259

1260 for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {

1261

1263 if (i == (int)FirstVAReg) {

1265 }

1266 offset -= StackSlotSize;

1268

1269 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);

1270 RegInfo.addLiveIn(ArgRegs[i], VReg);

1273

1277 }

1278 } else {

1279

1281 MFI.CreateFixedObject(4, LRSaveSize + CCInfo.getStackSize(), true));

1282 }

1283 }

1284

1285

1286 if (!CFRegNode.empty())

1288

1289

1290

1291

1292

1293 for (const ArgDataPair &ArgDI : ArgData) {

1294 if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) {

1295 unsigned Size = ArgDI.Flags.getByValSize();

1296 Align Alignment =

1297 std::max(Align(StackSlotSize), ArgDI.Flags.getNonZeroByValAlign());

1298

1303 Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32),

1304 Alignment, false, false, nullptr, std::nullopt,

1306 } else {

1308 }

1309 }

1310

1311

1312 if (!MemOps.empty()) {

1315 }

1316

1317 return Chain;

1318}

1319

1320

1321

1322

1323

1324bool XCoreTargetLowering::

1326 bool isVarArg,

1330 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);

1331 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))

1332 return false;

1333 if (CCInfo.getStackSize() != 0 && isVarArg)

1334 return false;

1335 return true;

1336}

1337

1340 bool isVarArg,

1344

1348

1349

1350

1352

1353

1356

1357

1358 if (!isVarArg)

1360

1361 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);

1362

1365

1366

1367 RetOps.push_back(DAG.getConstant(0, dl, MVT::i32));

1368

1370

1371 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {

1374 continue;

1376 if (isVarArg) {

1377 report_fatal_error("Can't return value from vararg function in memory");

1378 }

1379

1382

1383 int FI = MFI.CreateFixedObject(ObjSize, Offset, false);

1384

1385

1386

1389 Chain, dl, OutVals[i], FIN,

1391 }

1392

1393

1394

1395 if (!MemOpChains.empty())

1397

1398

1399 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {

1402 continue;

1403

1405

1406

1407

1410 }

1411

1412 RetOps[0] = Chain;

1413

1414

1416 RetOps.push_back(Glue);

1417

1419}

1420

1421

1422

1423

1424

1430 assert((MI.getOpcode() == XCore::SELECT_CC) &&

1431 "Unexpected instr type to insert");

1432

1433

1434

1435

1436

1439

1440

1441

1442

1443

1444

1445

1450 F->insert(It, copy0MBB);

1451 F->insert(It, sinkMBB);

1452

1453

1457

1458

1461

1462 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))

1463 .addReg(MI.getOperand(1).getReg())

1465

1466

1467

1468

1469 BB = copy0MBB;

1470

1471

1473

1474

1475

1476

1477 BB = sinkMBB;

1478 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())

1479 .addReg(MI.getOperand(3).getReg())

1481 .addReg(MI.getOperand(2).getReg())

1483

1484 MI.eraseFromParent();

1485 return BB;

1486}

1487

1488

1489

1490

1491

1492SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,

1493 DAGCombinerInfo &DCI) const {

1496 switch (N->getOpcode()) {

1497 default: break;

1499 switch (N->getConstantOperandVal(1)) {

1500 case Intrinsic::xcore_outt:

1501 case Intrinsic::xcore_outct:

1502 case Intrinsic::xcore_chkct: {

1503 SDValue OutVal = N->getOperand(3);

1504

1510 !DCI.isBeforeLegalizeOps());

1514 DCI.CommitTargetLoweringOpt(TLO);

1515 }

1516 break;

1517 }

1518 case Intrinsic::xcore_setpt: {

1519 SDValue Time = N->getOperand(3);

1520

1526 !DCI.isBeforeLegalizeOps());

1530 DCI.CommitTargetLoweringOpt(TLO);

1531 }

1532 break;

1533 }

1534 }

1535 break;

1537 SDValue N0 = N->getOperand(0);

1538 SDValue N1 = N->getOperand(1);

1539 SDValue N2 = N->getOperand(2);

1543

1544

1545 if (N0C && !N1C)

1547

1548

1549 if (N0C && N0C->isZero() && N1C && N1C->isZero()) {

1555 }

1556

1557

1558

1559 if (N1C && N1C->isZero() && N->hasNUsesOfValue(0, 1)) {

1563 if ((Known.Zero & Mask) == Mask) {

1568 }

1569 }

1570 }

1571 break;

1573 SDValue N0 = N->getOperand(0);

1574 SDValue N1 = N->getOperand(1);

1575 SDValue N2 = N->getOperand(2);

1579

1580

1581 if (N0C && N0C->isZero() && N1C && N1C->isZero()) {

1585 if ((Known.Zero & Mask) == Mask) {

1591 }

1592 }

1593

1594

1595

1596 if (N1C && N1C->isZero() && N->hasNUsesOfValue(0, 1)) {

1600 if ((Known.Zero & Mask) == Mask) {

1605 }

1606 }

1607 }

1608 break;

1610 SDValue N0 = N->getOperand(0);

1611 SDValue N1 = N->getOperand(1);

1612 SDValue N2 = N->getOperand(2);

1613 SDValue N3 = N->getOperand(3);

1617

1618

1619 if ((N0C && !N1C) ||

1622 N1, N0, N2, N3);

1623

1624

1625 if (N1C && N1C->isZero()) {

1626

1627 if (N->hasNUsesOfValue(0, 0)) {

1631 }

1632

1638 }

1639 }

1640 break;

1642

1643

1644

1645

1646 SDValue Mul0, Mul1, Addend0, Addend1;

1647 if (N->getValueType(0) == MVT::i32 &&

1650 DAG.getVTList(MVT::i32, MVT::i32), Mul0,

1651 Mul1, Addend0, Addend1);

1654 }

1656

1657

1658

1659

1660 if (N->getValueType(0) == MVT::i64 &&

1667 Mul0, DAG.getConstant(0, dl, MVT::i32));

1669 Mul1, DAG.getConstant(0, dl, MVT::i32));

1671 Addend0, DAG.getConstant(0, dl, MVT::i32));

1673 Addend1, DAG.getConstant(0, dl, MVT::i32));

1675 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,

1676 Addend0L, Addend1L);

1679 }

1680 }

1681 break;

1683

1685 if (!DCI.isBeforeLegalize() ||

1687 ST->getMemoryVT(),

1688 *ST->getMemOperand()) ||

1689 ST->isVolatile() || ST->isIndexed()) {

1690 break;

1691 }

1693

1694 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();

1695 assert((StoreBits % 8) == 0 &&

1696 "Store size in bits must be a multiple of 8");

1697 Align Alignment = ST->getAlign();

1698

1699 if (LoadSDNode *LD = dyn_cast(ST->getValue())) {

1700 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&

1701 LD->getAlign() == Alignment &&

1702 ->isVolatile() && ->isIndexed() &&

1705 return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(),

1706 DAG.getConstant(StoreBits / 8, dl, MVT::i32),

1707 Alignment, false, nullptr, isTail,

1708 ST->getPointerInfo(), LD->getPointerInfo());

1709 }

1710 }

1711 break;

1712 }

1713 }

1715}

1716

1717void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,

1719 const APInt &DemandedElts,

1721 unsigned Depth) const {

1723 switch (Op.getOpcode()) {

1724 default: break;

1727 if (Op.getResNo() == 1) {

1728

1731 }

1732 break;

1734 {

1735 unsigned IntNo = Op.getConstantOperandVal(1);

1736 switch (IntNo) {

1737 case Intrinsic::xcore_getts:

1738

1739 Known.Zero =

1741 break;

1742 case Intrinsic::xcore_int:

1743 case Intrinsic::xcore_inct:

1744

1745 Known.Zero =

1747 break;

1748 case Intrinsic::xcore_testct:

1749

1750 Known.Zero =

1752 break;

1753 case Intrinsic::xcore_testwct:

1754

1755 Known.Zero =

1757 break;

1758 }

1759 }

1760 break;

1761 }

1762}

1763

1764

1765

1766

1767

1769{

1770 return (val >= 0 && val <= 11);

1771}

1772

1774{

1775 return (val%2 == 0 && isImmUs(val/2));

1776}

1777

1779{

1780 return (val%4 == 0 && isImmUs(val/4));

1781}

1782

1783

1784

1787 unsigned AS,

1791

1792 unsigned Size = DL.getTypeAllocSize(Ty);

1796 }

1797

1798 switch (Size) {

1799 case 1:

1800

1801 if (AM.Scale == 0) {

1803 }

1804

1806 case 2:

1807 case 3:

1808

1809 if (AM.Scale == 0) {

1811 }

1812

1814 default:

1815

1816 if (AM.Scale == 0) {

1818 }

1819

1821 }

1822}

1823

1824

1825

1826

1827

1828std::pair<unsigned, const TargetRegisterClass *>

1831 MVT VT) const {

1832 if (Constraint.size() == 1) {

1833 switch (Constraint[0]) {

1834 default : break;

1835 case 'r':

1836 return std::make_pair(0U, &XCore::GRRegsRegClass);

1837 }

1838 }

1839

1840

1842}

AMDGPU Mark last scratch load

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...

static bool isImmUs(int64_t val)

static bool isImmUs4(int64_t val)

static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL)

static bool isWordAligned(SDValue Value, SelectionDAG &DAG)

static bool isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, SDValue &Addend1, bool requireIntermediatesHaveOneUse)

isADDADDMUL - Return whether Op is in a form that is equivalent to add(add(mul(x,y),...

static bool isImmUs2(int64_t val)

Class for arbitrary precision integers.

static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)

Constructs an APInt value that has the bottom loBitsSet bits set.

static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)

Constructs an APInt value that has the top hiBitsSet bits set.

LLVM Basic Block Representation.

The address of a basic block.

CCState - This class holds information needed while lowering arguments and return values.

CCValAssign - Represent assignment of one arg/retval to a location.

LocInfo getLocInfo() const

int64_t getLocMemOffset() const

static Constant * getGetElementPtr(Type *Ty, Constant *C, ArrayRef< Constant * > IdxList, GEPNoWrapFlags NW=GEPNoWrapFlags::none(), std::optional< ConstantRange > InRange=std::nullopt, Type *OnlyIfReducedTy=nullptr)

Getelementptr form.

uint64_t getZExtValue() const

This is an important base class in LLVM.

This class represents an Operation in the Expression.

A parsed version of the target data layout string in and methods for querying it.

IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const

Returns an integer type with size at least as big as that of a pointer in the given address space.

int64_t getOffset() const

const GlobalValue * getGlobal() const

bool hasLocalLinkage() const

StringRef getSection() const

const DataLayout & getDataLayout() const

Get the data layout of the module this global belongs to.

Type * getValueType() const

This is an important class for using LLVM in a threaded context.

This class is used to represent ISD::LOAD nodes.

static auto integer_valuetypes()

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)

Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)

Create a new object at a fixed location on the stack.

int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)

Create a new statically sized stack object, returning a nonnegative identifier to represent it.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineJumpTableInfo * getJumpTableInfo() const

getJumpTableInfo - Return the jump table info object for the current function.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

@ EK_Inline

EK_Inline - Jump table entries are emitted inline at their point of use.

const std::vector< MachineJumpTableEntry > & getJumpTables() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

unsigned getNumValues() const

Return the number of values defined/returned by this operator.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

bool hasOneUse() const

Return true if there is exactly one node using value ResNo of Node.

bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const

Return true if this operand (which must be a chain) reaches the specified operand without crossing an...

SDValue getValue(unsigned R) const

EVT getValueType() const

Return the ValueType of the referenced return value.

TypeSize getValueSizeInBits() const

Returns the size of the value in bits.

const SDValue & getOperand(unsigned i) const

unsigned getOpcode() const

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)

SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)

SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)

Create a MERGE_VALUES node from the given operands.

SDVTList getVTList(EVT VT)

Return an SDVTList that represents the list of values specified.

SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)

SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)

SDValue getRegister(Register Reg, EVT VT)

SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

const TargetLowering & getTargetLoweringInfo() const

SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)

SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)

Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).

SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)

const DataLayout & getDataLayout() const

SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)

SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)

SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

Helper function to build ISD::STORE nodes.

SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)

Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...

SDValue getExternalSymbol(const char *Sym, EVT VT)

SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)

SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const

Return the number of times the sign bit of the register is replicated into the other bits.

SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)

bool isBaseWithConstantOffset(SDValue Op) const

Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...

MachineFunction & getMachineFunction() const

SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)

KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const

Determine which bits of Op are known to be either zero or one and return them in Known.

bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const

Return true if 'Op & Mask' is known to be zero.

LLVMContext * getContext() const

SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)

SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

This class is used to represent ISD::STORE nodes.

StringRef - Represent a constant reference to a string, i.e.

bool starts_with(StringRef Prefix) const

Check if this string starts with the given Prefix.

constexpr size_t size() const

size - Get the string size.

TargetInstrInfo - Interface to description of machine instruction set.

void setBooleanVectorContents(BooleanContent Ty)

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

unsigned MaxStoresPerMemcpyOptSize

Likewise for functions with the OptSize attribute.

const TargetMachine & getTargetMachine() const

void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)

Set the maximum atomic operation size supported by the backend.

void setMinFunctionAlignment(Align Alignment)

Set the target's minimum function alignment.

unsigned MaxStoresPerMemsetOptSize

Likewise for functions with the OptSize attribute.

void setBooleanContents(BooleanContent Ty)

Specify how the target extends the result of integer and floating point boolean values from i1 to a w...

unsigned MaxStoresPerMemmove

Specify maximum number of store instructions per memmove call.

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

unsigned MaxStoresPerMemmoveOptSize

Likewise for functions with the OptSize attribute.

void addRegisterClass(MVT VT, const TargetRegisterClass *RC)

Add the specified register class as an available regclass for the specified value type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

void setPrefFunctionAlignment(Align Alignment)

Set the target's preferred function alignment.

unsigned MaxStoresPerMemset

Specify maximum number of store instructions per memset call.

@ ZeroOrOneBooleanContent

void setStackPointerRegisterToSaveRestore(Register R)

If set to a physical register, this specifies the register that llvm.savestack/llvm....

void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)

Targets should invoke this method for each target independent node that they want to provide a custom...

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

std::vector< ArgListEntry > ArgListTy

bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

This function returns true if the memory access is aligned or if the target allows this specific unal...

unsigned MaxStoresPerMemcpy

Specify maximum number of store instructions per memcpy call.

void setSchedulingPreference(Sched::Preference Pref)

Specify the target scheduling preference.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const

Check to see if the specified operand of the specified instruction is a constant integer.

std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const

This function lowers an abstract call to a function into an actual call.

virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const

Given a physical register constraint (e.g.

bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const

Look at Op.

bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const

Check whether a given call node is in tail position within its function.

virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Primary interface to the complete machine description for the target machine.

CodeModel::Model getCodeModel() const

Returns the code model.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

@ VoidTyID

type with no size

static Type * getVoidTy(LLVMContext &C)

bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const

Return true if it makes sense to take the size of this type.

static IntegerType * getInt8Ty(LLVMContext &C)

bool isFunctionTy() const

True if this is an instance of FunctionType.

static IntegerType * getInt32Ty(LLVMContext &C)

TypeID getTypeID() const

Return the type id for the type.

LLVM Value Representation.

Align getPointerAlignment(const DataLayout &DL) const

Returns an alignment of the pointer value.

static int stackSlotSize()

Stack slot size (4 bytes)

XCoreFunctionInfo - This class is derived from MachineFunction private XCore target-specific informat...

void setVarArgsFrameIndex(int off)

void setReturnStackOffset(unsigned value)

int getVarArgsFrameIndex() const

int createLRSpillSlot(MachineFunction &MF)

unsigned getReturnStackOffset() const

const TargetRegisterInfo * getRegisterInfo() const override

const XCoreInstrInfo * getInstrInfo() const override

bool isZExtFree(SDValue Val, EVT VT2) const override

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...

unsigned getJumpTableEncoding() const override

Return the entry encoding for a jump table in the current function.

XCoreTargetLowering(const TargetMachine &TM, const XCoreSubtarget &Subtarget)

const char * getTargetNodeName(unsigned Opcode) const override

getTargetNodeName - This method returns the name of a target specific

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Args[]

Key for Kernel::Metadata::mArgs.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

@ STACKRESTORE

STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.

@ STACKSAVE

STACKSAVE - STACKSAVE has one operand, an input chain.

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ VAEND

VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.

@ FRAME_TO_ARGS_OFFSET

FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...

@ ADD

Simple integer binary arithmetic operators.

@ LOAD

LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ INTRINSIC_VOID

OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...

@ MEMBARRIER

MEMBARRIER - Compiler barrier only; generate a no-op.

@ ATOMIC_FENCE

OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.

@ BUILD_PAIR

BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.

@ INIT_TRAMPOLINE

INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.

@ EH_RETURN

OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...

@ SIGN_EXTEND

Conversion operators.

@ BR_CC

BR_CC - Conditional branch.

@ BR_JT

BR_JT - Jumptable branch.

@ EXTRACT_ELEMENT

EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...

@ VACOPY

VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ DYNAMIC_STACKALLOC

DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.

@ FRAMEADDR

FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ TRAP

TRAP - Trapping instruction.

@ INTRINSIC_WO_CHAIN

RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...

@ TokenFactor

TokenFactor - This node takes multiple tokens as input and produces a single token result.

@ VAARG

VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.

@ SHL_PARTS

SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.

@ ADJUST_TRAMPOLINE

ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.

@ INTRINSIC_W_CHAIN

RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...

This is an optimization pass for GlobalISel generic memory operations.

@ Low

Lower the current thread's priority such that it does not affect foreground tasks significantly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

static const unsigned CodeModelLargeSize

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

@ Mul

Product of integers.

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

constexpr unsigned BitWidth

This struct is a compact representation of a valid (non-zero power of two) alignment.

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

bool isInteger() const

Return true if this is an integer or a vector integer type.

unsigned countMinTrailingZeros() const

Returns the minimum number of trailing zero bits.

unsigned getBitWidth() const

Get the bit width of this value.

void resetAll()

Resets the known state of all bits.

This class contains a discriminated union of information about pointers in memory operands,...

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

This represents a list of ValueType's that has been intern'd by a SelectionDAG.

This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...

This structure contains all information that is necessary for lowering calls.

SmallVector< ISD::InputArg, 32 > Ins

SmallVector< ISD::OutputArg, 32 > Outs

SmallVector< SDValue, 32 > OutVals

A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...