XtensaDisassembler.cpp Source File (original) (raw)

27using namespace llvm;

30#define DEBUG_TYPE "Xtensa-disassembler"

34namespace {

37 bool IsLittleEndian;

39public:

43 bool hasDensity() const { return STI.hasFeature(Xtensa::FeatureDensity); }

48};

49}

54 return new XtensaDisassembler(STI, Ctx, true);

55}

63 Xtensa::A0, Xtensa::SP, Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5,

64 Xtensa::A6, Xtensa::A7, Xtensa::A8, Xtensa::A9, Xtensa::A10, Xtensa::A11,

65 Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15};

69 const void *Decoder) {

76}

80 const void *Decoder) {

81 if (RegNo > 3)

87}

91 const void *Decoder) {

92 if (RegNo > 1)

98}

102 const void *Decoder) {

103 if (RegNo > 1)

105

109}

110

113 const void *Decoder) {

114 if (RegNo > 15)

116

120}

121

125 if (RegNo > 255)

127

131

132 const XtensaDisassembler *Dis =

133 static_cast<const XtensaDisassembler *>(Decoder);

137 RAType))

139

142}

143

148

150 {Xtensa::LBEG, 0}, {Xtensa::LEND, 1},

151 {Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3},

152 {Xtensa::BREG, 4}, {Xtensa::LITBASE, 5},

153 {Xtensa::SCOMPARE1, 12}, {Xtensa::ACCLO, 16},

154 {Xtensa::ACCHI, 17}, {Xtensa::M0, 32},

155 {Xtensa::M1, 33}, {Xtensa::M2, 34},

156 {Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72},

157 {Xtensa::WINDOWSTART, 73}, {Xtensa::IBREAKENABLE, 96},

158 {Xtensa::MEMCTL, 97}, {Xtensa::ATOMCTL, 99},

159 {Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128},

160 {Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144},

161 {Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160},

162 {Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176},

163 {Xtensa::EPC1, 177}, {Xtensa::EPC2, 178},

164 {Xtensa::EPC3, 179}, {Xtensa::EPC4, 180},

165 {Xtensa::EPC5, 181}, {Xtensa::EPC6, 182},

166 {Xtensa::EPC7, 183}, {Xtensa::DEPC, 192},

167 {Xtensa::EPS2, 194}, {Xtensa::EPS3, 195},

168 {Xtensa::EPS4, 196}, {Xtensa::EPS5, 197},

169 {Xtensa::EPS6, 198}, {Xtensa::EPS7, 199},

170 {Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209},

171 {Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211},

172 {Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213},

173 {Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215},

174 {Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226},

175 {Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228},

176 {Xtensa::PS, 230}, {Xtensa::VECBASE, 231},

177 {Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233},

178 {Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235},

179 {Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237},

180 {Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240},

181 {Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242},

182 {Xtensa::MISC0, 244}, {Xtensa::MISC1, 245},

183 {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};

184

188 if (RegNo > 255)

190

196

197 for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {

200

201

202

204 Reg = Xtensa::INTSET;

205 }

206

210

213 }

214 }

215

217}

218

221 const void *Decoder) {

222 if (RegNo > 15)

224

228}

229

233 const void *Decoder) {

236 0, InstSize);

237}

238

240 int64_t Address, const void *Decoder) {

245}

246

248 int64_t Address, const void *Decoder) {

252}

253

255 int64_t Address, const void *Decoder) {

257 case Xtensa::BEQZ:

258 case Xtensa::BGEZ:

259 case Xtensa::BLTZ:

260 case Xtensa::BNEZ:

263 Address, 0, 3, Inst, Decoder))

265 break;

266 default:

269 Address, 0, 3, Inst, Decoder))

271 }

273}

274

276 int64_t Address, const void *Decoder) {

277

280 Decoder))

283}

284

286 int64_t Address, const void *Decoder) {

287

292}

293

295 int64_t Address, const void *Decoder) {

299}

300

302 int64_t Address,

303 const void *Decoder) {

307}

308

310 int64_t Address, const void *Decoder) {

314}

315

317 int64_t Address, const void *Decoder) {

321}

322

324 int64_t Address, const void *Decoder) {

328}

329

331 int64_t Address, const void *Decoder) {

335}

336

338 int64_t Address,

339 const void *Decoder) {

341 if (!Imm)

343 else

346}

347

349 int64_t Address,

350 const void *Decoder) {

352 if ((Imm & 0x60) == 0x60)

354 else

357}

358

360 int64_t Address, const void *Decoder) {

364}

365

367 int64_t Address,

368 const void *Decoder) {

369 assert(isUInt<6>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate");

372}

373

375 int64_t Address,

376 const void *Decoder) {

377 assert(isUInt<15>(Imm) && ((Imm & 0x7) == 0) && "Invalid immediate");

380}

381

383 int64_t Address,

384 const void *Decoder) {

388}

389

390static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7,

391 8, 10, 12, 16, 32, 64, 128, 256};

393 int64_t Address, const void *Decoder) {

395

398}

399

400static int64_t TableB4constu[16] = {32768, 65536, 2, 3, 4, 5, 6, 7,

401 8, 10, 12, 16, 32, 64, 128, 256};

403 int64_t Address,

404 const void *Decoder) {

406

409}

410

412 int64_t Address, const void *Decoder) {

416}

417

419 int64_t Address, const void *Decoder) {

424}

425

427 int64_t Address, const void *Decoder) {

432}

433

435 int64_t Address, const void *Decoder) {

440}

441

443 int64_t Address, const void *Decoder) {

448}

449

450

451

454 bool IsLittleEndian) {

455

456 if (Bytes.size() < 2) {

459 }

460

461 if (!IsLittleEndian) {

463 } else {

464 Insn = (Bytes[1] << 8) | Bytes[0];

465 }

466

468}

469

470

473 bool IsLittleEndian) {

474

475 if (Bytes.size() < 3) {

478 }

479

480 if (!IsLittleEndian) {

482 } else {

483 Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);

484 }

485

487}

488

489#include "XtensaGenDisassemblerTables.inc"

490

495 uint64_t Insn;

497

498

499 if (hasDensity()) {

503 LLVM_DEBUG(dbgs() << "Trying Xtensa 16-bit instruction table :\n");

504 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);

508 }

509 }

510

511

515 LLVM_DEBUG(dbgs() << "Trying Xtensa 24-bit instruction table :\n");

516 Result = decodeInstruction(DecoderTable24, MI, Insn, Address, this, STI);

520 }

522}

unsigned const MachineRegisterInfo * MRI

MCDisassembler::DecodeStatus DecodeStatus

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)

#define LLVM_EXTERNAL_VISIBILITY

static bool isBranch(unsigned Opcode)

static DecodeStatus decodeMem16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:426

static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:100

static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:78

static int64_t TableB4const[16]

Definition XtensaDisassembler.cpp:390

static DecodeStatus decodeImm1n_15Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:337

static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:111

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler()

Definition XtensaDisassembler.cpp:57

static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:89

static DecodeStatus readInstruction24(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian)

Read three bytes from the ArrayRef and return 24 bit data.

Definition XtensaDisassembler.cpp:471

static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:301

static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:294

static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:285

static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:374

static DecodeStatus decodeMem32nOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:442

static DecodeStatus decodeImm12Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:309

static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:67

static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t InstSize, MCInst &MI, const void *Decoder)

Definition XtensaDisassembler.cpp:230

const MCPhysReg ARDecoderTable[]

Definition XtensaDisassembler.cpp:62

static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:434

static DecodeStatus decodeUimm4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:316

static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition XtensaDisassembler.cpp:122

static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:366

static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:330

static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:418

static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:411

static DecodeStatus decodeUimm5Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:323

static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:348

static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian)

Read two bytes from the ArrayRef and return 16 bit data sorted according to the given endianness.

Definition XtensaDisassembler.cpp:452

static MCDisassembler * createXtensaDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition XtensaDisassembler.cpp:51

static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:239

static DecodeStatus decodeB4constuOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:402

static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:392

static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:359

static int64_t TableB4constu[16]

Definition XtensaDisassembler.cpp:400

static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition XtensaDisassembler.cpp:185

static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:219

static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:382

static DecodeStatus decodeLoopOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:275

static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:247

static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)

Definition XtensaDisassembler.cpp:254

const DecodeRegister SRDecoderTable[]

Definition XtensaDisassembler.cpp:149

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Context object for machine code objects.

Superclass for all disassemblers.

bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const

const MCSubtargetInfo & getSubtargetInfo() const

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

void addOperand(const MCOperand Op)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const FeatureBitset & getFeatureBits() const

Target - Wrapper for Target specific information.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

bool checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits, RegisterAccessType RA)

MCRegister getUserRegister(unsigned Code, const MCRegisterInfo &MRI)

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

Target & getTheXtensaTarget()

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

MCPhysReg Reg

Definition XtensaDisassembler.cpp:145

uint32_t RegNo

Definition XtensaDisassembler.cpp:146

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.