Enrico Monaco - Academia.edu (original) (raw)

Papers by Enrico Monaco

Electronics

In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the s... more In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and compensate for them by setting the optimal bias voltage. This can also be used to cancel the front-end nonlinear effects. The sampler was verified by implementing it in TSMC 5 nm FinFET, and a calibration system in a Pulse Amplitude Modulation transceiver, detecting and minimizing the nonlinearities, is presented. The optimum voltage biasing of the sampler was obtained by co-simulating the circuit with the linearity calibration loop implemented in Verilog-A. The histogram of the sampled signal at the slicer input is shown before and after the calibration to show the improvement in the sampled eye opening. Moreover, the resulting bias is equal to the one that maximizes the total harmonic dist...

Electronics

In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hol... more In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with t...

IEEE Transactions on Circuits and Systems II: Express Briefs, 2021

The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is inve... more The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021

In this paper we devised a simple analytical jitter model for the shunt capacitor delay line and ... more In this paper we devised a simple analytical jitter model for the shunt capacitor delay line and the current starved delay line. In the model we also considered the layout resistances and capacitances effects, the flicker noise, and the gate resistances noise which are not negligible in FinFET technology. Then, we verified the model validity through the design of prototypes in 5nm technology, obtaining a good match between the simulation and the model with a 15% maximum error. Lastly, we compared the efficiency of the circuits, and we analyze the effects of the capacitive load tuning range on the capacitive load delay line efficiency, showing how critical this is in the design and choice of the delay line topology.

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018

Transceivers for backplane serial links at 25Gb/s and beyond demand equalizers with high accuracy... more Transceivers for backplane serial links at 25Gb/s and beyond demand equalizers with high accuracy and flexibility in matching the channel response. To this purpose, a continuous-time linear equalizer (CTLE) with a transversal architecture is proposed. The equalizer features variable DC gain and two zeros that can be tuned independently. The transversal architecture makes it compatible with gradient descent algorithms, allowing optimal adaptation of the gain and zero frequency locations and improved equalization accuracy. The CTLE was realized in a 28nm CMOS technology and measurements are presented at data rate from 5Gb/s to 25Gb/s across 20dB-loss channels. Core power dissipation is 17mW from 1V supply and horizontal eye opening at BER=10−12 is larger than 50%, comparing favorably against previously reported equalizers targeting similar data-rate and channel loss.

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021

This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal i... more This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a 60 GS/s, 52.6 dB SFDR, 8 ways interleaved simulated prototype in TSMC 5 nm technology, consuming 2. 52 mW from a 0.9 V supply, is compared to the state-of- the-art sampling buffers, showing linearity improvement.

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018

PAM-4 modulation paired with forward error correction schemes has been introduced in recent wirel... more PAM-4 modulation paired with forward error correction schemes has been introduced in recent wireline communication standards operating up to 56Gb/s per-lane. PAM-4 enables a more efficient use of the available link bandwidth but, compared to NRZ, design of low-power transceivers entails new challenges. Transmitters must deliver high swing with wide bandwidth and high linearity [1-3]. The multilevel signal suffers from heightened sensitivity to channel loss and reflections, because transitions between adjacent levels are impaired from ISI generated by 3x larger pk-to-pk transitions [4]. As a result, enhanced equalization accuracy is mandatory before symbol detection.

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017

Electronics Letters, 2017

Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with h... more Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid meansquare-error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB-loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10 −12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data-rate and channel loss.

IEEE Journal of Solid-State Circuits, 2017

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expect... more Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of π/4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The standalone ILRO demonstrates 0.2-11.7 GHz frequency range with better than 1.5°quadrature phase error over ±20% supply and −40°C to +120°C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2-11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requirements of >25 Gb/s multi-standard I/O RXs.

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013

2009 IEEE Custom Integrated Circuits Conference, 2009

Frequency multipliers in CMOS are key blocks in new emerging applications at μ-waves and mmwaves.... more Frequency multipliers in CMOS are key blocks in new emerging applications at μ-waves and mmwaves. Classical solutions, in bipolar technology, exploit the steep non-linear I-V characteristic in order to generate output harmonics at multiples of the input signal frequency. This solution would lead to a very limited gain (or even loss) in CMOS. In this paper we propose a novel circuit topology where a differential pair, in push-push configuration, locks an LC oscillator over a wide frequency range. A behavioral model of the circuit is presented and simple design equations for locking range and output swing are derived. Prototypes, realized in a standard 0.13μm CMOS technology, show 30% locking range around 13GHz with 3dBm input power. Suppression of the unwanted input signal and its 3rd harmonic is better than 45dBc. Core power dissipation is 5.2mW only, less than half compared with state of the art.

2011 IEEE International Solid-State Circuits Conference, 2011

With a cutoff frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding... more With a cutoff frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms [1,2]. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers, working as dynamic CML latches, to realize high speed and low power mm-Wave dividers. The solution is very compact, which is particularly desirable at mm-Waves to ease chip layout and shorten IC interconnections, minimizing signal losses. A frequency divider-by-4 has been realized in a 65nm bulk CMOS technology and prototypes prove an operating frequency programmable from 20 to 70GHz. The frequency range in each sub-band spans from 10% to 17%, corresponding to a 2.5x to 4x improvement compared to injection-locked dividers-by-4. Maximum power dissipation is 6.5mW and occupied area is only 15μm x 30μm.

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010

A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of... more A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 2014

Transceivers for wireless communications at millimeter-waves are becoming pervasive in several co... more Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this article is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65 and 32 nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. fT and fMAX increase though slower than in the past, ron*Coff, a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32 nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108 GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes.

2012 IEEE Radio Frequency Integrated Circuits Symposium, 2012

2011 IEEE International Solid-State Circuits Conference, 2011

Electronics

In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the s... more In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and compensate for them by setting the optimal bias voltage. This can also be used to cancel the front-end nonlinear effects. The sampler was verified by implementing it in TSMC 5 nm FinFET, and a calibration system in a Pulse Amplitude Modulation transceiver, detecting and minimizing the nonlinearities, is presented. The optimum voltage biasing of the sampler was obtained by co-simulating the circuit with the linearity calibration loop implemented in Verilog-A. The histogram of the sampled signal at the slicer input is shown before and after the calibration to show the improvement in the sampled eye opening. Moreover, the resulting bias is equal to the one that maximizes the total harmonic dist...

Electronics

In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hol... more In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with t...

IEEE Transactions on Circuits and Systems II: Express Briefs, 2021

The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is inve... more The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2021

In this paper we devised a simple analytical jitter model for the shunt capacitor delay line and ... more In this paper we devised a simple analytical jitter model for the shunt capacitor delay line and the current starved delay line. In the model we also considered the layout resistances and capacitances effects, the flicker noise, and the gate resistances noise which are not negligible in FinFET technology. Then, we verified the model validity through the design of prototypes in 5nm technology, obtaining a good match between the simulation and the model with a 15% maximum error. Lastly, we compared the efficiency of the circuits, and we analyze the effects of the capacitive load tuning range on the capacitive load delay line efficiency, showing how critical this is in the design and choice of the delay line topology.

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018

Transceivers for backplane serial links at 25Gb/s and beyond demand equalizers with high accuracy... more Transceivers for backplane serial links at 25Gb/s and beyond demand equalizers with high accuracy and flexibility in matching the channel response. To this purpose, a continuous-time linear equalizer (CTLE) with a transversal architecture is proposed. The equalizer features variable DC gain and two zeros that can be tuned independently. The transversal architecture makes it compatible with gradient descent algorithms, allowing optimal adaptation of the gain and zero frequency locations and improved equalization accuracy. The CTLE was realized in a 28nm CMOS technology and measurements are presented at data rate from 5Gb/s to 25Gb/s across 20dB-loss channels. Core power dissipation is 17mW from 1V supply and horizontal eye opening at BER=10−12 is larger than 50%, comparing favorably against previously reported equalizers targeting similar data-rate and channel loss.

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021

This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal i... more This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a 60 GS/s, 52.6 dB SFDR, 8 ways interleaved simulated prototype in TSMC 5 nm technology, consuming 2. 52 mW from a 0.9 V supply, is compared to the state-of- the-art sampling buffers, showing linearity improvement.

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018

PAM-4 modulation paired with forward error correction schemes has been introduced in recent wirel... more PAM-4 modulation paired with forward error correction schemes has been introduced in recent wireline communication standards operating up to 56Gb/s per-lane. PAM-4 enables a more efficient use of the available link bandwidth but, compared to NRZ, design of low-power transceivers entails new challenges. Transmitters must deliver high swing with wide bandwidth and high linearity [1-3]. The multilevel signal suffers from heightened sensitivity to channel loss and reflections, because transitions between adjacent levels are impaired from ISI generated by 3x larger pk-to-pk transitions [4]. As a result, enhanced equalization accuracy is mandatory before symbol detection.

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017

Electronics Letters, 2017

Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with h... more Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid meansquare-error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB-loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10 −12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data-rate and channel loss.

IEEE Journal of Solid-State Circuits, 2017

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expect... more Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of π/4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The standalone ILRO demonstrates 0.2-11.7 GHz frequency range with better than 1.5°quadrature phase error over ±20% supply and −40°C to +120°C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2-11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requirements of >25 Gb/s multi-standard I/O RXs.

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013

2009 IEEE Custom Integrated Circuits Conference, 2009

Frequency multipliers in CMOS are key blocks in new emerging applications at μ-waves and mmwaves.... more Frequency multipliers in CMOS are key blocks in new emerging applications at μ-waves and mmwaves. Classical solutions, in bipolar technology, exploit the steep non-linear I-V characteristic in order to generate output harmonics at multiples of the input signal frequency. This solution would lead to a very limited gain (or even loss) in CMOS. In this paper we propose a novel circuit topology where a differential pair, in push-push configuration, locks an LC oscillator over a wide frequency range. A behavioral model of the circuit is presented and simple design equations for locking range and output swing are derived. Prototypes, realized in a standard 0.13μm CMOS technology, show 30% locking range around 13GHz with 3dBm input power. Suppression of the unwanted input signal and its 3rd harmonic is better than 45dBc. Core power dissipation is 5.2mW only, less than half compared with state of the art.

2011 IEEE International Solid-State Circuits Conference, 2011

With a cutoff frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding... more With a cutoff frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms [1,2]. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers, working as dynamic CML latches, to realize high speed and low power mm-Wave dividers. The solution is very compact, which is particularly desirable at mm-Waves to ease chip layout and shorten IC interconnections, minimizing signal losses. A frequency divider-by-4 has been realized in a 65nm bulk CMOS technology and prototypes prove an operating frequency programmable from 20 to 70GHz. The frequency range in each sub-band spans from 10% to 17%, corresponding to a 2.5x to 4x improvement compared to injection-locked dividers-by-4. Maximum power dissipation is 6.5mW and occupied area is only 15μm x 30μm.

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010

A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of... more A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 2014

Transceivers for wireless communications at millimeter-waves are becoming pervasive in several co... more Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this article is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65 and 32 nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. fT and fMAX increase though slower than in the past, ron*Coff, a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32 nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108 GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes.

2012 IEEE Radio Frequency Integrated Circuits Symposium, 2012

2011 IEEE International Solid-State Circuits Conference, 2011