Five to 25 Gb/s continuous time linear equaliser with transversal architecture (original) (raw)

A 38-Gb/s 2-tap transversal equalizer in 0.13-μm CMOS using a microstrip delay element

George Ng

2008 IEEE Radio Frequency Integrated Circuits Symposium, 2008

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A Low-Power 20-Gb/s Discrete-Time Analog Front-End for ADC-Based Serial Link Equalizers

Sameh Ibrahim

arXiv: Signal Processing, 2019

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A novel CMOS edge equalizer for 10GB/S highly lossy backplane

dianyong Chen

Biennial Symposium on Communications, 2008

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Low-Power CMOS Equalizer Design for 20-Gb/s Systems

Sameh Ibrahim

IEEE Journal of Solid-State Circuits, 2011

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A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization

Vishnu Balan

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

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A 40-Gb/s serial link transceiver in 28-nm CMOS technology

Bruce Su

2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014

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A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

Hirotaka Tamura

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

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Decision-Feedback-Equalizer for 10-Gb/s backplane transceivers for highly lossy 56-inch channels

dianyong Chen

2008 International Conference on Communications, Circuits and Systems, 2008

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A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-$\mu{\hbox {m}}$ CMOS

Namik Kocaman

IEEE Journal of Solid-State Circuits, 2000

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A 1.0625 sim\simsim 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

TAI YU JING

IEEE Journal of Solid-State Circuits, 2011

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A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control

Shahbaz Abbasi

International Journal of Circuit Theory and Applications, 2016

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A 5-Gbps USB3.0 transmitter and receiver linear equalizer

George Souliotis

International Journal of Circuit Theory and Applications, 2014

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0.18-/spl mu/m CMOS equalization techniques for 10-Gb/s fiber optical communication links

Youngsik Hur

IEEE Transactions on Microwave Theory and Techniques, 2000

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Continuous time linear equalization based gigabit receiver for parallel interface

Shiv Harit Mathur

2018

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Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

Jihong Ren

IEEE Transactions on Circuits and Systems I: Regular Papers, 2000

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A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

Monica Garcia

IEEE Journal of Solid-State Circuits, 2000

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A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

Sergey Rylov

IEEE Journal of Solid-State Circuits, 2000

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An improved equalization circuit for 10-Gb/s high-speed serial transmission over backplane channel

dianyong Chen

2009 International Conference on Communications, Circuits and Systems, 2009

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A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Junyoung Song

IEICE Electronics Express

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A compact low power mixed-signal equalizer for gigabit Ethernet applications

saeed saeedi

2006

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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

José Tierno

IEEE Journal of Solid-State Circuits, 2012

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A 2.44-pJ/b 1.62–10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

Jinhyung Lee

IEEE Transactions on Circuits and Systems II: Express Briefs, 2018

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Adaptive decision feedback equalization for multi-Gbps data links

Alaa Abdullah

2021

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A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 μm CMOS

fang lu

IEEE Journal of Solid-state Circuits, 1993

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A 20Gb/s 40mW equalizer in 90nm CMOS technology

Sameh Ibrahim

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

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Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

Seema Grover

2018 IEEE International Test Conference (ITC), 2018

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ISSCC 2007 / SESSION 24 / MULTI-GB/s TRANSCEIVERS / 24.1 24.1 A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

元莆 林

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A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

soorosh naseri

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Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS

RAKESH A

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A general-purpose high-speed equalizer

Patrice Senn

IEEE Journal of Solid-State Circuits, 1991

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Reliable CMOS adaptive equalizer for short-haul optical networks

Concepcion Aldea Aldea

Microelectronics Reliability, 2014

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Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s

Minkyu Je

IEEE Transactions on Circuits and Systems I-regular Papers, 2018

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A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE

M Ahmed Ragab

IEEE Journal of Solid-State Circuits, 2014

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A 6.25Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

Vikas Gupta

IEEE Journal of Solid-state Circuits, 2005

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A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

Seung-Jun Bae

IEEE Transactions on Circuits and Systems I-regular Papers, 2015

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