Henning Gundersen - Academia.edu (original) (raw)

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Papers by Henning Gundersen

Most of the electronic circuits designed today use binary logic. However, will binary logic be th... more Most of the electronic circuits designed today use binary logic. However, will binary logic be the leading technology in the future, why not uses balanced ternary logic, imple-mented using recharged semi-floating gate (RSFG) devices, instead? This paper gives some measurements and analyzes novel applications using CMOS RSFG technology.

This paper presents an approach to programming threshold voltages in floating-gate CMOS circuits.... more This paper presents an approach to programming threshold voltages in floating-gate CMOS circuits. The threshold voltage programming is exploited in ultra low-voltage ULV) amplifier design. A threshold voltage programming scheme is presented and several examples of analog ULV circuits are described. The ULV circuits are used in ULV amplifier design. Measured data are provided.

In this paper we present a novel voltage mode noninverting CMOS Semi Floating-Gate(SFG) Ternary S... more In this paper we present a novel voltage mode noninverting CMOS Semi Floating-Gate(SFG) Ternary Switching Element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35µmprocess parameters c35b4 is included.

2006 Ieee International Symposium on Circuits and Systems, May 21, 2006

This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Rechar... more This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged Semi-Floating Gate Transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadence R Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm General Purpose Bulk CMOS Process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is +/-0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates.

35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005

37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007

This paper presents ternary counters using balanced ternary notation. The balanced ternary counte... more This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.

Proceedings of The International Symposium on Multiple-Valued Logic

This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged... more This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi- Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

This paper presents a novel ternary more, less and equality (MLE) circuit implemented with rechar... more This paper presents a novel ternary more, less and equality (MLE) circuit implemented with recharged semi-floating gate transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadencereg Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm general purpose bulk CMOS process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is plusmn0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates

This paper will present work on a recharged com-parator using Semi Floating-Gate (SFG) MOS device... more This paper will present work on a recharged com-parator using Semi Floating-Gate (SFG) MOS devices. The out-put voltage of a basic SFG MOS Comparator circuit is normally interleaved with a recharge voltage. This prohibit control of pass-gates, which requires binary control signals. An output buffer is introduced to allow the control of pass-gates and multiplexers (MUXs) beyond a single recharge clock period. The recharged comparator is utilized as reset logic in a recharged multiple-valued (MV) n-ary frequency divider (FDIV). The MV FDIV reduces the number of transistors required for a configurable frequency division of modulus between two and eight. This makes it applicable as bit-counter and symbol clock generator in recharged configurable serial D/A converters. Simulation data is obtained using AMS 0.35µm process parameters c35b4.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

In this paper we present a new proposal for implementing a voltage-mode Multiple-Valued (MV) maxi... more In this paper we present a new proposal for implementing a voltage-mode Multiple-Valued (MV) maximum or minimum function. The circuit has been implemented using Recharged Semi Floating-Gate (SFG) transistors. The benefit with this design is, the proposed circuits can easily be fabricated using a conventional CMOS process. The circuit is suitable for a low power design, V dd < 2 volt. It has high noise margin and good linearity. The simulation results for the proposed circuit are evaluated using AMS 0.35µm CMOS device parameters.

37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007

In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The tern... more In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied. Simulated data for 130nm and 0.35µm CMOS processes are given.

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001

In this paper we present an ultra low-voltage (ULV) floating-gate (FG) transconductance amplifier... more In this paper we present an ultra low-voltage (ULV) floating-gate (FG) transconductance amplifier The amplifier is can operate at supply voltages down to 0.3V in a standard digital double poly CMOS process . The amplifier consists of three subcircuits, the single input analog FG inverter, the additive (double input) analog FG inverter with tunable gain and a FG digital inverter. Preliminary measurements of the transconductance amplifier are provided.

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001

In this paper we present a floating-Gate differential amplifier input stage with tunable gain. Th... more In this paper we present a floating-Gate differential amplifier input stage with tunable gain. The input stage can be used in a differential ultra lowvoltage (ULV) floating gate (FG) transconductance amplifier. Measured data for the subcircuits operating at 0.8V, 0.5V and 0.3V are provided.

2006 NORCHIP, 2006

This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can... more This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with Recharged Semi-Floating Gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers.

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001

Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we pr... more Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.