John Lau - Academia.edu (original) (raw)
Papers by John Lau
Journal of the Engineering Mechanics Division, 1981
Journal of the Engineering Mechanics Division, 1981
In this note, the simultaneous action of two kinds of loads on a cantilever is studied. It will b... more In this note, the simultaneous action of two kinds of loads on a cantilever is studied. It will be shown that the superposition of the results does not avail.
Journal of the Engineering Mechanics Division, 1982
Closed-form solutions are presented for the problem of large deflection of a cantilever beam with... more Closed-form solutions are presented for the problem of large deflection of a cantilever beam with a couple and a concentrated load acting simultaneously at the free end. Dimensionless charts are provided which relate the variables maximum vertical deflections, maximum horizontal deflections, couple and force.
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2018
The design, materials, process, fabrication, and reliability of a heterogeneous integration of fo... more The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips by a fanout panel-level packaging (FOPLP) method are investigated in this paper. Emphasis is placed on the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. The electroless Cu is used to make the seed layer, the laser direct imaging is used for opening the photoresist, and the printed circuit board Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the drop test and thermal cycling test are also performed.
Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology, 2004
The effects of temperature-cycling dwell-time on the thermal-fatigue life of lead-free solder joi... more The effects of temperature-cycling dwell-time on the thermal-fatigue life of lead-free solder joints are investigated in this study. Emphasis is placed on the determination of creep responses and the creep strain energy density per cycle of a PBGA (plastic ball grid array) package’s lead-free solder joints subjected to various dwell times (namely, 15, 60, and 480 minutes) at peak cycling temperatures (0°C and 100°C).
The lead-free solder-joint reliability of the high-density packages, 256-pin PBGA (plastic ball g... more The lead-free solder-joint reliability of the high-density packages, 256-pin PBGA (plastic ball grid array), 388-pin PBGA, and 1657-pin CCGA (ceramic column grid array), on PCB (printed circuit board) subjected to temperature cycling is investigated. Emphasis is placed on the determination of the creep responses (e.g., stress, strain, and strain energy density) of the lead-free solder joints of these packages. The
International Symposium on Microelectronics, 2012
The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart... more The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm × 28mm) with double sided wiring layers. This interposer is used to support a very large chip (22mm × 18mm) on its top-side and 2 smaller chips (10mm × 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm × 40mm) (with ordinary lead-free solder bumps). The lead-free micro solder bumps (Cu/Sn) on all the chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn.
Solder Joint Reliability, 1991
Surface mount technology (SMT) is currently one of the strongest trends in electronic packaging a... more Surface mount technology (SMT) is currently one of the strongest trends in electronic packaging and interconnect assembly. This technology offers oppor-tunities for significant cost reduction and for efficient production line automation.
2007 9th Electronics Packaging Technology Conference, 2007
... Joint Reliability of a New Lead-Free Solder: Sn3wt%Ag0.5wt%Cu0.019wt%Ce (SACC) John Lau1, San... more ... Joint Reliability of a New Lead-Free Solder: Sn3wt%Ag0.5wt%Cu0.019wt%Ce (SACC) John Lau1, Sang Liu2, Dongkai Shangguan3, Zhi Wei Song2, David ... Also, they are internally connected in such a way when they are soldered on the test board there will be a daisy chain for ...
The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in th... more The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in this paper. The demodulator is intended for use in direct-conversion high speed radio paging receivers. It is based on a zero-crossing counting and comparing scheme. To improve the bit error rate (BER) performance, a novel technique is utilized, which increases the decision accuracy by generating additional zero-crossings. Simple yet effective clock recovery circuits are included on-chip. The demodulator is fabricated in a 0.35 micron N-well CMOS process and occupies about 0.78 mm2 area. It consumes about 3 mW from a 3-V power supply. Good agreement between measurement and simulation is observed.
Journal of Electronic Packaging, 2014
3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC int... more 3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.
1997 Proceedings 47th Electronic Components and Technology Conference, 1997
This paper presents a new class of low cost, electrically and thermally optimized ball grid array... more This paper presents a new class of low cost, electrically and thermally optimized ball grid array packages, called NuBGA (new and useful ball grid array). The package is suitable for both low and high pin count applications. NuBGA is a cavity down package with a metal heatspreader covering the entire back surface of the package. Heat spreader is laminated with a single core double sided organic substrate. Optimized electrical performance is achieved using the design concepts of Split-Wrap-Around (SWA) and Split-Via-Connections (SVC). All traces on the core substrate can be designed into p-stripline and co-planar stripline structures. Further enhanced thermal and electrical performance NuBGA can be achieved by applying an additional metal stiffener and thinner core substrate. In this paper, the presentation is focus on (1) the unique design concept, (2) the electrical analysis, (3) the electrical measurement, and (4) the performance comparison with standard packages.
2008 58th Electronic Components and Technology Conference, 2008
An optical probe is developed for imaging in an optical coherence tomography (OCT) system. A 3D m... more An optical probe is developed for imaging in an optical coherence tomography (OCT) system. A 3D micro mirror is used for steering the beam from the source to the sample. A GRIN lens, fiber and micro mirror are assembled in a silicon optical bench. The assembled components are housed in the bio-compatible microinjection molded housing. The images obtained using this probe is studied with respect to probe assembly. Tolerance of GRIN lens placement, micro mirror placement on the substrate, deformation of the mirror, housing transparency and housing curvature are studied with respect to the final image from the probe. In this study it is found that a higher mirror curvature affects the depth of focus on the sample and mirror placement reduces the coupling efficiency during the optical assembly
Circuit World, 1995
Studies of solder‐bumped flip chips on organic substrates reported in the literature have so far ... more Studies of solder‐bumped flip chips on organic substrates reported in the literature have so far suggested the necessity of a polymeric underfill to compensate for the large thermal mismatch between the silicon and the substrate. In this company's target applications of this process, the underfill not only has to meet the much published mechanical and chemical requirements, but also has to flow through a vertical clearance of 0.020 to 0.0375 mm quickly as well as being cured in a relatively short time. The evaluation of the underfill materials starts with some basic understanding of how the different ingredients in the underfill formulation might affect its physical and chemical properties. The flow characteristics of the underfills were a first priority in the selection. A detailed thermal‐mechanical analysis then helped to determine the optimal cure schedule with the desired physical properties. A simple test die/test board system has been designed to evaluate how the underfil...
Materials Science Forum, 1985
Page 1. Materials Science Forum Vols. 5-6 (1985) pp 717-720 © (1985) Trans Tech Publications, Swi... more Page 1. Materials Science Forum Vols. 5-6 (1985) pp 717-720 © (1985) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.5-6.717 All rights reserved. No part of contents of this paper may be reproduced ...
Bio/Technology, 1989
I n an article by Pamela Knight entitled "Microcomputer Software Compares 2-D Gels," (Bio/Technol... more I n an article by Pamela Knight entitled "Microcomputer Software Compares 2-D Gels," (Bio/Technology 6:999, Sept. '88) Bio-Rad's 2-D Analyst II software for comparison of 2-D gels was not mentioned. We would like to point out that this system provides 2-D quantitative analyses, including automatic gel to gel comparisons and single spot analysis.
Guang pu xue yu guang pu fen xi = Guang pu, 2008
A method was studied for the analysis of Cr, As, Cd, Hg and Pb in acrylonitrile-butadiene-styrene... more A method was studied for the analysis of Cr, As, Cd, Hg and Pb in acrylonitrile-butadiene-styrene copolymer by using ICP-MS. The instrument parameters were optimized and the introduction system was developed systematically. The sample is decomposed by microwave digestion. The digestion condition was optimized concerning digestion system, proportion of acids and digestion procedure, which affords reference for the preparation of the same kinds of polymer samples. The detection limits of the method for all sample elements were 0.7-6.5 ng x g(-1), the recoveries were 89.8%-110.8%, and the RSDs were 2.8%-11.3%. The analytical method presented was characterized with good precision and accuracy, simplicity, rapidness, low limits of detection and no matrix matching requirements.
Surface mount technology (SMT) is a mature technology. SMT allows placement of more surface mount... more Surface mount technology (SMT) is a mature technology. SMT allows placement of more surface mount components (SMC) into smaller and tighter printed circuit board (PCB) areas. This increased density means increased performance and power in smaller packaging systems, and allows manufacturing of smaller and higher performance products at lower cost. The advance of integrated circuit (IC) technology and the requirements of high density for high-speed circuity is driving the design of SM C to higher pin count and smaller package size. In general, the higher pin count and smaller package size are accomplished by reducing the bond pad size and spacing (pitch) on the chip level and the lead/pin/solder dimensions and pitch on the chip carrier (module) level. The last few years have witnessed an explosive growth in the research and development efforts devoted to FPT as a direct result of the rapid growth of SMT and miniaturization. Some examples are: hand held lightweight video recorders that can take sharp pictures, hand held lightweight devices that can track the worldwide package movements, and portable computers with tiny yet powerful microprocessors and large memory capability that can fit into a briefcase or into the palm of your hand.
2007 International Conference on Electronic Materials and Packaging, 2007
... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Instit... more ... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Institute of Microelectronics, Singapore ... The dummy chip dimensions are 10x10mm, body dimensions are 12x12mm, and for other dimensions such as molding, substrate, and ...
2007 9th Electronics Packaging Technology Conference, 2007
... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Instit... more ... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Institute of Microelectronics, Singapore ... The dummy chip dimensions are 10x10mm, body dimensions are 12x12mm, and for other dimensions such as molding, substrate, and ...
Journal of the Engineering Mechanics Division, 1981
Journal of the Engineering Mechanics Division, 1981
In this note, the simultaneous action of two kinds of loads on a cantilever is studied. It will b... more In this note, the simultaneous action of two kinds of loads on a cantilever is studied. It will be shown that the superposition of the results does not avail.
Journal of the Engineering Mechanics Division, 1982
Closed-form solutions are presented for the problem of large deflection of a cantilever beam with... more Closed-form solutions are presented for the problem of large deflection of a cantilever beam with a couple and a concentrated load acting simultaneously at the free end. Dimensionless charts are provided which relate the variables maximum vertical deflections, maximum horizontal deflections, couple and force.
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2018
The design, materials, process, fabrication, and reliability of a heterogeneous integration of fo... more The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips by a fanout panel-level packaging (FOPLP) method are investigated in this paper. Emphasis is placed on the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. The electroless Cu is used to make the seed layer, the laser direct imaging is used for opening the photoresist, and the printed circuit board Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the drop test and thermal cycling test are also performed.
Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology, 2004
The effects of temperature-cycling dwell-time on the thermal-fatigue life of lead-free solder joi... more The effects of temperature-cycling dwell-time on the thermal-fatigue life of lead-free solder joints are investigated in this study. Emphasis is placed on the determination of creep responses and the creep strain energy density per cycle of a PBGA (plastic ball grid array) package’s lead-free solder joints subjected to various dwell times (namely, 15, 60, and 480 minutes) at peak cycling temperatures (0°C and 100°C).
The lead-free solder-joint reliability of the high-density packages, 256-pin PBGA (plastic ball g... more The lead-free solder-joint reliability of the high-density packages, 256-pin PBGA (plastic ball grid array), 388-pin PBGA, and 1657-pin CCGA (ceramic column grid array), on PCB (printed circuit board) subjected to temperature cycling is investigated. Emphasis is placed on the determination of the creep responses (e.g., stress, strain, and strain energy density) of the lead-free solder joints of these packages. The
International Symposium on Microelectronics, 2012
The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart... more The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm × 28mm) with double sided wiring layers. This interposer is used to support a very large chip (22mm × 18mm) on its top-side and 2 smaller chips (10mm × 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm × 40mm) (with ordinary lead-free solder bumps). The lead-free micro solder bumps (Cu/Sn) on all the chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn.
Solder Joint Reliability, 1991
Surface mount technology (SMT) is currently one of the strongest trends in electronic packaging a... more Surface mount technology (SMT) is currently one of the strongest trends in electronic packaging and interconnect assembly. This technology offers oppor-tunities for significant cost reduction and for efficient production line automation.
2007 9th Electronics Packaging Technology Conference, 2007
... Joint Reliability of a New Lead-Free Solder: Sn3wt%Ag0.5wt%Cu0.019wt%Ce (SACC) John Lau1, San... more ... Joint Reliability of a New Lead-Free Solder: Sn3wt%Ag0.5wt%Cu0.019wt%Ce (SACC) John Lau1, Sang Liu2, Dongkai Shangguan3, Zhi Wei Song2, David ... Also, they are internally connected in such a way when they are soldered on the test board there will be a daisy chain for ...
The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in th... more The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in this paper. The demodulator is intended for use in direct-conversion high speed radio paging receivers. It is based on a zero-crossing counting and comparing scheme. To improve the bit error rate (BER) performance, a novel technique is utilized, which increases the decision accuracy by generating additional zero-crossings. Simple yet effective clock recovery circuits are included on-chip. The demodulator is fabricated in a 0.35 micron N-well CMOS process and occupies about 0.78 mm2 area. It consumes about 3 mW from a 3-V power supply. Good agreement between measurement and simulation is observed.
Journal of Electronic Packaging, 2014
3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC int... more 3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.
1997 Proceedings 47th Electronic Components and Technology Conference, 1997
This paper presents a new class of low cost, electrically and thermally optimized ball grid array... more This paper presents a new class of low cost, electrically and thermally optimized ball grid array packages, called NuBGA (new and useful ball grid array). The package is suitable for both low and high pin count applications. NuBGA is a cavity down package with a metal heatspreader covering the entire back surface of the package. Heat spreader is laminated with a single core double sided organic substrate. Optimized electrical performance is achieved using the design concepts of Split-Wrap-Around (SWA) and Split-Via-Connections (SVC). All traces on the core substrate can be designed into p-stripline and co-planar stripline structures. Further enhanced thermal and electrical performance NuBGA can be achieved by applying an additional metal stiffener and thinner core substrate. In this paper, the presentation is focus on (1) the unique design concept, (2) the electrical analysis, (3) the electrical measurement, and (4) the performance comparison with standard packages.
2008 58th Electronic Components and Technology Conference, 2008
An optical probe is developed for imaging in an optical coherence tomography (OCT) system. A 3D m... more An optical probe is developed for imaging in an optical coherence tomography (OCT) system. A 3D micro mirror is used for steering the beam from the source to the sample. A GRIN lens, fiber and micro mirror are assembled in a silicon optical bench. The assembled components are housed in the bio-compatible microinjection molded housing. The images obtained using this probe is studied with respect to probe assembly. Tolerance of GRIN lens placement, micro mirror placement on the substrate, deformation of the mirror, housing transparency and housing curvature are studied with respect to the final image from the probe. In this study it is found that a higher mirror curvature affects the depth of focus on the sample and mirror placement reduces the coupling efficiency during the optical assembly
Circuit World, 1995
Studies of solder‐bumped flip chips on organic substrates reported in the literature have so far ... more Studies of solder‐bumped flip chips on organic substrates reported in the literature have so far suggested the necessity of a polymeric underfill to compensate for the large thermal mismatch between the silicon and the substrate. In this company's target applications of this process, the underfill not only has to meet the much published mechanical and chemical requirements, but also has to flow through a vertical clearance of 0.020 to 0.0375 mm quickly as well as being cured in a relatively short time. The evaluation of the underfill materials starts with some basic understanding of how the different ingredients in the underfill formulation might affect its physical and chemical properties. The flow characteristics of the underfills were a first priority in the selection. A detailed thermal‐mechanical analysis then helped to determine the optimal cure schedule with the desired physical properties. A simple test die/test board system has been designed to evaluate how the underfil...
Materials Science Forum, 1985
Page 1. Materials Science Forum Vols. 5-6 (1985) pp 717-720 © (1985) Trans Tech Publications, Swi... more Page 1. Materials Science Forum Vols. 5-6 (1985) pp 717-720 © (1985) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.5-6.717 All rights reserved. No part of contents of this paper may be reproduced ...
Bio/Technology, 1989
I n an article by Pamela Knight entitled "Microcomputer Software Compares 2-D Gels," (Bio/Technol... more I n an article by Pamela Knight entitled "Microcomputer Software Compares 2-D Gels," (Bio/Technology 6:999, Sept. '88) Bio-Rad's 2-D Analyst II software for comparison of 2-D gels was not mentioned. We would like to point out that this system provides 2-D quantitative analyses, including automatic gel to gel comparisons and single spot analysis.
Guang pu xue yu guang pu fen xi = Guang pu, 2008
A method was studied for the analysis of Cr, As, Cd, Hg and Pb in acrylonitrile-butadiene-styrene... more A method was studied for the analysis of Cr, As, Cd, Hg and Pb in acrylonitrile-butadiene-styrene copolymer by using ICP-MS. The instrument parameters were optimized and the introduction system was developed systematically. The sample is decomposed by microwave digestion. The digestion condition was optimized concerning digestion system, proportion of acids and digestion procedure, which affords reference for the preparation of the same kinds of polymer samples. The detection limits of the method for all sample elements were 0.7-6.5 ng x g(-1), the recoveries were 89.8%-110.8%, and the RSDs were 2.8%-11.3%. The analytical method presented was characterized with good precision and accuracy, simplicity, rapidness, low limits of detection and no matrix matching requirements.
Surface mount technology (SMT) is a mature technology. SMT allows placement of more surface mount... more Surface mount technology (SMT) is a mature technology. SMT allows placement of more surface mount components (SMC) into smaller and tighter printed circuit board (PCB) areas. This increased density means increased performance and power in smaller packaging systems, and allows manufacturing of smaller and higher performance products at lower cost. The advance of integrated circuit (IC) technology and the requirements of high density for high-speed circuity is driving the design of SM C to higher pin count and smaller package size. In general, the higher pin count and smaller package size are accomplished by reducing the bond pad size and spacing (pitch) on the chip level and the lead/pin/solder dimensions and pitch on the chip carrier (module) level. The last few years have witnessed an explosive growth in the research and development efforts devoted to FPT as a direct result of the rapid growth of SMT and miniaturization. Some examples are: hand held lightweight video recorders that can take sharp pictures, hand held lightweight devices that can track the worldwide package movements, and portable computers with tiny yet powerful microprocessors and large memory capability that can fit into a briefcase or into the palm of your hand.
2007 International Conference on Electronic Materials and Packaging, 2007
... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Instit... more ... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Institute of Microelectronics, Singapore ... The dummy chip dimensions are 10x10mm, body dimensions are 12x12mm, and for other dimensions such as molding, substrate, and ...
2007 9th Electronics Packaging Technology Conference, 2007
... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Instit... more ... John Lau1, Jeffery Lo2, Jimmy Lam2, Eng-Leong Soon3, Woai-Sheng Chow3, and Ricky Lee2 1Institute of Microelectronics, Singapore ... The dummy chip dimensions are 10x10mm, body dimensions are 12x12mm, and for other dimensions such as molding, substrate, and ...