Michael Dimopoulos - Academia.edu (original) (raw)

Papers by Michael Dimopoulos

Research paper thumbnail of Advanced double-sampling architectures

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2016

Research paper thumbnail of Speeding Up GA-Based ATPG for Sequential Circuits through Knowledge Extraction and Exploitation

This paper presents a genetic algorithm based approach to cope with the problem of sequential cir... more This paper presents a genetic algorithm based approach to cope with the problem of sequential circuit test generation. Population sequences having low fitness values but detect extra faults, which sequences otherwise would be discarded, survive and evolve in subsequent generations thus maintaining population diversity. For the purpose of further increasing the fault coverage and keeping the test sequence length small

Research paper thumbnail of A GA-based method for efficient interconnect capacitance computation in mixed-signal integrated circuits using sets of linear charges

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

ABSTRACT The problem of interconnect capacitance computation in mixed-signal integrated circuits ... more ABSTRACT The problem of interconnect capacitance computation in mixed-signal integrated circuits is studied in this work. The proposed method is based on the method of images utilizing sets of linear charges and a Genetic Algorithm (GA). The proposed method is general and applicable to an arbitrary geometry configuration of interconnection lines. Comparative simulation results are presented for several practical case studies with a commercial tool employing the Finite Element Method (FEM). The results show that the computed capacitance value by our proposed method is in close agreement to the value obtained by the commercial tool with the average difference ranging between 2%-5%.

Research paper thumbnail of Prospects of 3D inductors on through silicon vias processes for 3D ICs

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come.... more Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-siliconvias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

Research paper thumbnail of Wavelet analysis of measurements for on-line testing analog & mixed-signal circuits

2010 IEEE 16th International On-Line Testing Symposium, 2010

In this paper a test method based on the wavelet transformation of the measured signal, be it sup... more In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform, is presented. In the wavelet analysis, a test metric named discrimination factor is introduced utilizing information from initial two decomposition levels of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Experimental comparative results between the proposed method, a test method based on the RMS value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum and a method based on the wavelet transformation of the measured signal are presented showing the effectiveness of the proposed testing scheme.

Research paper thumbnail of Efficient inductance calculation for long and medium length rectangular interconnects in VLSI circuits

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

ABSTRACT A method for computing mutual inductance between interconnects of rectangular geometry i... more ABSTRACT A method for computing mutual inductance between interconnects of rectangular geometry in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is general and does not rely on any fitting techniques. It is shown to be computational efficient and numerical stable even for very long interconnects. Simulation results with other methods from literature are presented. The mutual inductance value computed by the proposed method is shown to be in close agreement to the value obtained by the industry standard tool-FastHenry with the average error falling below 5%. In this work, a new method for computing the mutual inductance of rectangular conductors is presented. It is based on partitioning each conductor into segments and placing a current filament in it. Then, the mutual inductance between the conductors is computed as a weighted sum of the mutual inductances between each pair of filaments. The weights, the currents of the filaments, are calculated by utilizing fast matrix solving techniques. The method is general and may be applied to any multiconductor system of arbitrary placement.

Research paper thumbnail of A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) ... more A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

Research paper thumbnail of Musical composition based on genetic algorithms and fuzzy transformations of traditional Greek music patterns

Progress in Computer Research, 2001

... Downloads (12 Months), 8. View colleagues of Panagiotis Linardis. Michael Dimopoulos homepage... more ... Downloads (12 Months), 8. View colleagues of Panagiotis Linardis. Michael Dimopoulos homepage mdimop ieee.org. ... 2. {2} Spyridis, H., Politis, D., "Information Theory Applied to the Structural Study of Byzantine Ecclesiastical Hymns", ACUSTICA, Vol. 71, No. 1, May 1990, pp. ...

Research paper thumbnail of Closed-form expressions for the coupling capacitance computation between through silicon vias and interconnects for 3D ICs

Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems Mixdes 2011, 2011

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to ... more Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-silicon- vias (TSV) processes offer a step towards 3D integration. In this work, the capacitive coupling between TSVs and (horizontal) interconnects is studied. A closed-form formula is derived by studying the physics of the problem. In the analysis, no fitting techniques are utilized. As results show, the range of validity of the proposed formula covers the current and future TSV geometries with the average error falling within 4-6%.

Research paper thumbnail of Analog and mixed-signal testing by wavelet transformations of power supply current measurements

2009 Mixdes 16th International Conference Mixed Design of Integrated Circuits Systems, Jun 25, 2009

ABSTRACT In this paper a test method based on wavelet transformation of the measured supply curre... more ABSTRACT In this paper a test method based on wavelet transformation of the measured supply current (IPS) waveforms is presented. The method is simple, offers a single-point test measurement solution and may easily be adapted to test various analog and mixed-signal systems. Experimental comparative results between the proposed method, a test method based on the RMS value of IPS, and a test method utilizing the harmonic magnitude components of the IPS spectrum are presented showing the effectiveness of the proposed testing scheme.

Research paper thumbnail of Automated substrate resistance extraction in nanoscale VLSI by exploiting a geometry-based analytical model

Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems Mixdes 2011, 2011

In this work, a new automated method for determining the substrate resistance is presented. It ex... more In this work, a new automated method for determining the substrate resistance is presented. It exploits a geometric formulation of the current streamlines between coupled structures and builds an analytical model for the substrate resistance. Both simulation and measurement data are utilized in order to show the validity of the proposed scheme. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance while the average error falls within 5%. Index Terms—Substrate noise; Integrated circuits; geometric modeling; Resistance extraction; Resistance Modeling; Parasitics.

Research paper thumbnail of Improved Selection of Test SubSequences in Sequential Circuits for Reduced Power Consumption

A method for the reduction of power dissipation during testing of sequential circuits is presente... more A method for the reduction of power dissipation during testing of sequential circuits is presented. In this algorithm from an initial set of test sequences a set of subsequences is properly selected with the purpose of reducing the power consumption without reducing the initial fault coverage. The selection process is accelerated by exploiting the presence of essential sequences and enhanced by introducing to the original test set new GA-engineered test sequences in order to further reduce power consumption. The algorithm as a secondary objective tries to compact the resulting subsequences. Experimental results support the usefulness of the proposed method.

Research paper thumbnail of Efficient testing of an optical feedback pixel driver using wavelet analysis

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

ABSTRACT A method for testing an optical feedback pixel driver (OFPD) is presented. It is based o... more ABSTRACT A method for testing an optical feedback pixel driver (OFPD) is presented. It is based on the wavelet transformation of the measured output pixel current (IPIXEL) waveform. In the wavelet analysis, a test metric is introduced which relies on the wavelet energy computation from the trend and detail coefficients of the IPIXEL waveform. The proposed test method is general and may be applied also for testing other analog and mixed-signal circuits. Comparative simulation results are presented between the proposed method and a method utilizing the calculation of the integral of the IPIXEL. The results show a +13.33% improvement in fault coverage by using the proposed testing scheme.

Research paper thumbnail of Efficient static compaction of test sequence sets through the application of set covering techniques

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004

The test sequence compaction problem is modeled here, first, as a set covering problem. This form... more The test sequence compaction problem is modeled here, first, as a set covering problem. This formulation enables the straightforward application of set covering methods for compaction. Because of the complexity inherent in the first model, a second more efficient, formulation is proposed where the test sequences are modeled as matrix columns with variable costs (number of vectors). Further, matrix reduction rules appropriate to the new formulation, which do not affect the optimality of the solution, are introduced. Finally, the reduced problem is minimized with a Branch & Bound algorithm. Experiments on a large number of test sets show significant reductions to the original problem by simply using the presented reduction rules. Experimental results comparing our method with others from the literature and also with the absolute minima of the examples, computed separately with the MINCOV algorithm, support the potential of the proposed approach.

Research paper thumbnail of Wavelet energy-based Mahalanobis distance metric for testing analog and mixed-signal circuits

In this paper a test method based on the wavelet transformation of the measured signal, be it sup... more In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform, is presented. In the wavelet analysis, a Mahalanobis distance test metric is introduced utilizing information from the wavelet energies of the first decomposition level of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Simulation comparative results on a benchmark circuit for testing both hard faults and parametric faults are presented showing the effectiveness of the proposed testing scheme.

Research paper thumbnail of Design and development of a versatile testing system for analog and mixed-signal circuits

2007 18th European Conference on Circuit Theory and Design, 2007

... various complex electronic products which among others include fire alarm systems, burglary p... more ... various complex electronic products which among others include fire alarm systems, burglary protection ... other specialized testing methods like [9-11] which are based on supply ... REFERENCES [1] E. Makrigiannis, AA Hatzopoulos, “Microcontroller based on-line testing of analog ...

Research paper thumbnail of Using Non-uniform Crossover in Genetic Algorithm Methods to Speed up the Generation of Test Patterns for Sequential Circuits

Lecture Notes in Computer Science, 2002

... and CD Spyropoulos (Eds.): SETN 2002, LNAI 2308, pp. 485–493, 2002. © Springer-Verlag Berlin ... more ... and CD Spyropoulos (Eds.): SETN 2002, LNAI 2308, pp. 485–493, 2002. © Springer-Verlag Berlin Heidelberg 2002 Using Non-uniform Crossover in Genetic Algorithm Methods to Speed up the Generation of Test Patterns for Sequential Circuits Michael Dimopoulos and ...

Research paper thumbnail of Multiple Parametric Circuit Analysis Tool for Detectability Estimation

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007

In this paper a software tool is presented which is capable of producing testability metrics for ... more In this paper a software tool is presented which is capable of producing testability metrics for analog and mixed-signal circuits. These metrics are obtained by performing probabilistic analysis techniques. The presented tool acts as a shell utilizing the power of state of the art external schematic and simulation programs and offers to the user a graphical interface for circuit design

Research paper thumbnail of Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008

In this paper a model for emergency luminaire circuits is utilized for building a fault dictionar... more In this paper a model for emergency luminaire circuits is utilized for building a fault dictionary so as to be used for circuit fault diagnosis. Simulation and measurements used for testing an emergency luminaire were performed in order to verify the emergency luminaire circuits behavior. Simulation results were compared to the experimental data acquired with the help of an oscilloscope and a measuring system, which offers real-time storage of current and voltage waveform measurements. Simulations of the fault-free circuit and faulty circuit instances proved to be in good accordance to the measured data. A fault dictionary is built and is successfully used to diagnose the most commonly encountered faults in the circuit.

Research paper thumbnail of Simulation and measurements for testing an emergency luminaire circuit

MELECON 2008 - The 14th IEEE Mediterranean Electrotechnical Conference, 2008

ABSTRACT In this paper simulation and measurements used for testing an emergency luminaire are pr... more ABSTRACT In this paper simulation and measurements used for testing an emergency luminaire are presented. Model validation is accomplished by comparing the PSpice data with the experimental data acquired with the help of an oscilloscope and a measuring system which offers real-time storage of current and voltage waveform measurements. Simulations of the fault-free circuit and faulty circuit instances proved to be in good accordance to the measured data. From the simulated fault-free and several commonly encountered faulty circuit cases, a fault dictionary can be built in order to be used in a fault circuit diagnosis method for emergency luminaire circuits.

Research paper thumbnail of Advanced double-sampling architectures

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2016

Research paper thumbnail of Speeding Up GA-Based ATPG for Sequential Circuits through Knowledge Extraction and Exploitation

This paper presents a genetic algorithm based approach to cope with the problem of sequential cir... more This paper presents a genetic algorithm based approach to cope with the problem of sequential circuit test generation. Population sequences having low fitness values but detect extra faults, which sequences otherwise would be discarded, survive and evolve in subsequent generations thus maintaining population diversity. For the purpose of further increasing the fault coverage and keeping the test sequence length small

Research paper thumbnail of A GA-based method for efficient interconnect capacitance computation in mixed-signal integrated circuits using sets of linear charges

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

ABSTRACT The problem of interconnect capacitance computation in mixed-signal integrated circuits ... more ABSTRACT The problem of interconnect capacitance computation in mixed-signal integrated circuits is studied in this work. The proposed method is based on the method of images utilizing sets of linear charges and a Genetic Algorithm (GA). The proposed method is general and applicable to an arbitrary geometry configuration of interconnection lines. Comparative simulation results are presented for several practical case studies with a commercial tool employing the Finite Element Method (FEM). The results show that the computed capacitance value by our proposed method is in close agreement to the value obtained by the commercial tool with the average difference ranging between 2%-5%.

Research paper thumbnail of Prospects of 3D inductors on through silicon vias processes for 3D ICs

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come.... more Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-siliconvias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

Research paper thumbnail of Wavelet analysis of measurements for on-line testing analog & mixed-signal circuits

2010 IEEE 16th International On-Line Testing Symposium, 2010

In this paper a test method based on the wavelet transformation of the measured signal, be it sup... more In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform, is presented. In the wavelet analysis, a test metric named discrimination factor is introduced utilizing information from initial two decomposition levels of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Experimental comparative results between the proposed method, a test method based on the RMS value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum and a method based on the wavelet transformation of the measured signal are presented showing the effectiveness of the proposed testing scheme.

Research paper thumbnail of Efficient inductance calculation for long and medium length rectangular interconnects in VLSI circuits

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

ABSTRACT A method for computing mutual inductance between interconnects of rectangular geometry i... more ABSTRACT A method for computing mutual inductance between interconnects of rectangular geometry in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is general and does not rely on any fitting techniques. It is shown to be computational efficient and numerical stable even for very long interconnects. Simulation results with other methods from literature are presented. The mutual inductance value computed by the proposed method is shown to be in close agreement to the value obtained by the industry standard tool-FastHenry with the average error falling below 5%. In this work, a new method for computing the mutual inductance of rectangular conductors is presented. It is based on partitioning each conductor into segments and placing a current filament in it. Then, the mutual inductance between the conductors is computed as a weighted sum of the mutual inductances between each pair of filaments. The weights, the currents of the filaments, are calculated by utilizing fast matrix solving techniques. The method is general and may be applied to any multiconductor system of arbitrary placement.

Research paper thumbnail of A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) ... more A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

Research paper thumbnail of Musical composition based on genetic algorithms and fuzzy transformations of traditional Greek music patterns

Progress in Computer Research, 2001

... Downloads (12 Months), 8. View colleagues of Panagiotis Linardis. Michael Dimopoulos homepage... more ... Downloads (12 Months), 8. View colleagues of Panagiotis Linardis. Michael Dimopoulos homepage mdimop ieee.org. ... 2. {2} Spyridis, H., Politis, D., "Information Theory Applied to the Structural Study of Byzantine Ecclesiastical Hymns", ACUSTICA, Vol. 71, No. 1, May 1990, pp. ...

Research paper thumbnail of Closed-form expressions for the coupling capacitance computation between through silicon vias and interconnects for 3D ICs

Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems Mixdes 2011, 2011

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to ... more Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-silicon- vias (TSV) processes offer a step towards 3D integration. In this work, the capacitive coupling between TSVs and (horizontal) interconnects is studied. A closed-form formula is derived by studying the physics of the problem. In the analysis, no fitting techniques are utilized. As results show, the range of validity of the proposed formula covers the current and future TSV geometries with the average error falling within 4-6%.

Research paper thumbnail of Analog and mixed-signal testing by wavelet transformations of power supply current measurements

2009 Mixdes 16th International Conference Mixed Design of Integrated Circuits Systems, Jun 25, 2009

ABSTRACT In this paper a test method based on wavelet transformation of the measured supply curre... more ABSTRACT In this paper a test method based on wavelet transformation of the measured supply current (IPS) waveforms is presented. The method is simple, offers a single-point test measurement solution and may easily be adapted to test various analog and mixed-signal systems. Experimental comparative results between the proposed method, a test method based on the RMS value of IPS, and a test method utilizing the harmonic magnitude components of the IPS spectrum are presented showing the effectiveness of the proposed testing scheme.

Research paper thumbnail of Automated substrate resistance extraction in nanoscale VLSI by exploiting a geometry-based analytical model

Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems Mixdes 2011, 2011

In this work, a new automated method for determining the substrate resistance is presented. It ex... more In this work, a new automated method for determining the substrate resistance is presented. It exploits a geometric formulation of the current streamlines between coupled structures and builds an analytical model for the substrate resistance. Both simulation and measurement data are utilized in order to show the validity of the proposed scheme. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance while the average error falls within 5%. Index Terms—Substrate noise; Integrated circuits; geometric modeling; Resistance extraction; Resistance Modeling; Parasitics.

Research paper thumbnail of Improved Selection of Test SubSequences in Sequential Circuits for Reduced Power Consumption

A method for the reduction of power dissipation during testing of sequential circuits is presente... more A method for the reduction of power dissipation during testing of sequential circuits is presented. In this algorithm from an initial set of test sequences a set of subsequences is properly selected with the purpose of reducing the power consumption without reducing the initial fault coverage. The selection process is accelerated by exploiting the presence of essential sequences and enhanced by introducing to the original test set new GA-engineered test sequences in order to further reduce power consumption. The algorithm as a secondary objective tries to compact the resulting subsequences. Experimental results support the usefulness of the proposed method.

Research paper thumbnail of Efficient testing of an optical feedback pixel driver using wavelet analysis

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010

ABSTRACT A method for testing an optical feedback pixel driver (OFPD) is presented. It is based o... more ABSTRACT A method for testing an optical feedback pixel driver (OFPD) is presented. It is based on the wavelet transformation of the measured output pixel current (IPIXEL) waveform. In the wavelet analysis, a test metric is introduced which relies on the wavelet energy computation from the trend and detail coefficients of the IPIXEL waveform. The proposed test method is general and may be applied also for testing other analog and mixed-signal circuits. Comparative simulation results are presented between the proposed method and a method utilizing the calculation of the integral of the IPIXEL. The results show a +13.33% improvement in fault coverage by using the proposed testing scheme.

Research paper thumbnail of Efficient static compaction of test sequence sets through the application of set covering techniques

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004

The test sequence compaction problem is modeled here, first, as a set covering problem. This form... more The test sequence compaction problem is modeled here, first, as a set covering problem. This formulation enables the straightforward application of set covering methods for compaction. Because of the complexity inherent in the first model, a second more efficient, formulation is proposed where the test sequences are modeled as matrix columns with variable costs (number of vectors). Further, matrix reduction rules appropriate to the new formulation, which do not affect the optimality of the solution, are introduced. Finally, the reduced problem is minimized with a Branch & Bound algorithm. Experiments on a large number of test sets show significant reductions to the original problem by simply using the presented reduction rules. Experimental results comparing our method with others from the literature and also with the absolute minima of the examples, computed separately with the MINCOV algorithm, support the potential of the proposed approach.

Research paper thumbnail of Wavelet energy-based Mahalanobis distance metric for testing analog and mixed-signal circuits

In this paper a test method based on the wavelet transformation of the measured signal, be it sup... more In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform, is presented. In the wavelet analysis, a Mahalanobis distance test metric is introduced utilizing information from the wavelet energies of the first decomposition level of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Simulation comparative results on a benchmark circuit for testing both hard faults and parametric faults are presented showing the effectiveness of the proposed testing scheme.

Research paper thumbnail of Design and development of a versatile testing system for analog and mixed-signal circuits

2007 18th European Conference on Circuit Theory and Design, 2007

... various complex electronic products which among others include fire alarm systems, burglary p... more ... various complex electronic products which among others include fire alarm systems, burglary protection ... other specialized testing methods like [9-11] which are based on supply ... REFERENCES [1] E. Makrigiannis, AA Hatzopoulos, “Microcontroller based on-line testing of analog ...

Research paper thumbnail of Using Non-uniform Crossover in Genetic Algorithm Methods to Speed up the Generation of Test Patterns for Sequential Circuits

Lecture Notes in Computer Science, 2002

... and CD Spyropoulos (Eds.): SETN 2002, LNAI 2308, pp. 485–493, 2002. © Springer-Verlag Berlin ... more ... and CD Spyropoulos (Eds.): SETN 2002, LNAI 2308, pp. 485–493, 2002. © Springer-Verlag Berlin Heidelberg 2002 Using Non-uniform Crossover in Genetic Algorithm Methods to Speed up the Generation of Test Patterns for Sequential Circuits Michael Dimopoulos and ...

Research paper thumbnail of Multiple Parametric Circuit Analysis Tool for Detectability Estimation

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007

In this paper a software tool is presented which is capable of producing testability metrics for ... more In this paper a software tool is presented which is capable of producing testability metrics for analog and mixed-signal circuits. These metrics are obtained by performing probabilistic analysis techniques. The presented tool acts as a shell utilizing the power of state of the art external schematic and simulation programs and offers to the user a graphical interface for circuit design

Research paper thumbnail of Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008

In this paper a model for emergency luminaire circuits is utilized for building a fault dictionar... more In this paper a model for emergency luminaire circuits is utilized for building a fault dictionary so as to be used for circuit fault diagnosis. Simulation and measurements used for testing an emergency luminaire were performed in order to verify the emergency luminaire circuits behavior. Simulation results were compared to the experimental data acquired with the help of an oscilloscope and a measuring system, which offers real-time storage of current and voltage waveform measurements. Simulations of the fault-free circuit and faulty circuit instances proved to be in good accordance to the measured data. A fault dictionary is built and is successfully used to diagnose the most commonly encountered faults in the circuit.

Research paper thumbnail of Simulation and measurements for testing an emergency luminaire circuit

MELECON 2008 - The 14th IEEE Mediterranean Electrotechnical Conference, 2008

ABSTRACT In this paper simulation and measurements used for testing an emergency luminaire are pr... more ABSTRACT In this paper simulation and measurements used for testing an emergency luminaire are presented. Model validation is accomplished by comparing the PSpice data with the experimental data acquired with the help of an oscilloscope and a measuring system which offers real-time storage of current and voltage waveform measurements. Simulations of the fault-free circuit and faulty circuit instances proved to be in good accordance to the measured data. From the simulated fault-free and several commonly encountered faulty circuit cases, a fault dictionary can be built in order to be used in a fault circuit diagnosis method for emergency luminaire circuits.