F. Verdier - Academia.edu (original) (raw)

Papers by F. Verdier

EURASIP Journal on Embedded Systems, 2008

We are interested in the design of a system-on-chip implementing the vision system of a mobile ro... more We are interested in the design of a system-on-chip implementing the vision system of a mobile robot. Following a biologically inspired approach, this vision architecture belongs to a larger sensorimotor loop. This regulation loop both creates and exploits dynamics properties to achieve a wide variety of target tracking and navigation objectives. Such a system is representative of numerous flexible and dynamic applications which are more and more encountered in embedded systems. In order to deal with all of the dynamic aspects of these applications, it appears necessary to embed a dedicated real-time operating system on the chip. The presence of this on-chip custom executive layer constitutes a major scientific obstacle in the traditional hardware and software design flows. Classical exploration and simulation tools are particularly inappropriate in this case. We detail in this paper the specific mechanisms necessary to build a high-level model of an embedded custom operating system able to manage such a real-time but flexible application. We also describe our executable RTOS model written in SystemC allowing an early simulation of our application on top of its specific scheduling layer. Based on this model, a methodology is discussed and results are given on the exploration and validation of a distributed platform adapted to this vision system.

2015 Euromicro Conference on Digital System Design, 2015

The paper focuses on techniques for the verification of software implementing communication funct... more The paper focuses on techniques for the verification of software implementing communication functionality in networked embedded systems. We discuss the merits and limitations of tools for the simulation of a networked embedded system executing the binary code of the network protocol stack. In particular, we compare different solutions to extend a virtual platform to simulate the node of interest in a realistic communication scenario involving different network nodes. We then explain how this solution has the potentiality to perform verification of the protocol stack, which would be a great asset for industry and academia to validate the communication software under development or use.

2008 International Conference on Reconfigurable Computing and FPGAs, 2008

This paper presents the OveRSoC project. The objective is to develop an exploration and validatio... more This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded real time operating systems for reconfigurable System-On-Chip based platforms. Here, we describe the overall methodology and the corresponding design environment. The method is based on abstract and modular SystemC models that allow to explore, simulate, and validate the distribution of OS services

In this paper, we study the impact of the finite precision coding of the messages used for LDPC B... more In this paper, we study the impact of the finite precision coding of the messages used for LDPC Belief Propagation decoding. The finite precision deteriorates the code performance, and we explain theoretically this performance loss with a quantized version of Density Evolution. Then, we point out the weaknesses of the quantized Belief Propagation decoder and propose a modification of the algorithm that reduces the gap between finite precision decoding and infinite precision decoding.

… Symposium on Turbo-Codes & Related …, 2003

We explore in this paper some issues concerning the parallel hardware implementation of LDPC code... more We explore in this paper some issues concerning the parallel hardware implementation of LDPC codes. We propose a LDPC matrix construction that is well suited to parallel decoding, that we called Hardware-Constrained LDPC codes (HC-LDPC). Although this construction is highly constrained, we show by simulations that there is no loss of performance compared to a pseudo-random parity matrix.

IEEE Transactions on Communications, 2010

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007

In the scope of the US Department of Defense (DoD) Joint Tactical Radio System (JTRS) program, th... more In the scope of the US Department of Defense (DoD) Joint Tactical Radio System (JTRS) program, the portability and reconfigurability needs of Software Defined Radios (SDR) required by the Software Communications Architecture (SCA) [1] can be resolved thanks to Model Driven Architecture (MDA) and component/container paradigm to address a heterogeneous hardware and software architecture. In this paper, we propose SystemC Transaction Level Modelling (TLM) to simulate Platform Independent Model (PIM) and Platform Specific Model (PSM) of SDRs, while keeping the component/container approach for applications portability. We show that SystemC 2.1 enables natively to simulate the waveform PIM specified in UML to obtain an executable specification, which can be reused to validate the SystemC TLM model of PSM. This latter allows radio platform virtualisation and true reuse of IPs models to validate earlier SDR waveforms and platforms. 1.2. Military overview The Joint Tactical Radio System (JTRS) is a US Department of Defense program aimed to create a global communication network of scalable and interoperable SDRs for US and allied terrestrial, maritime and airborne joint forces. The JTRS is built upon the Software Communications Architecture (SCA).

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, 2008

This paper presents an efficient run-time hardware/software scheduling approach. This scheduling ... more This paper presents an efficient run-time hardware/software scheduling approach. This scheduling heuristic consists in mapping on-line the different tasks of a highly dynamic application in such a way that the total execution time is minimized.Our approach takes advantage of the reconfiguration property of the considered architecture to adapt processing to the system dynamics. We compare our heuristic with another similar

2006 International Symposium on Intelligent Signal Processing and Communications, 2006

... Arthur Segard*, Frangois Verdier*, David Declercq* and Pascal Urardt *ETIS laboratory Univers... more ... Arthur Segard*, Frangois Verdier*, David Declercq* and Pascal Urardt *ETIS laboratory University of Cergy-Pontoise 6, avenue du Ponceau ... massively parallel hardware architecture of DVB-S2 compliant Some architectures were described to work with those specific LDPC ...

After a very successful start with many sources detected, the second phase of the H.E.S.S. experi... more After a very successful start with many sources detected, the second phase of the H.E.S.S. experiment is being implemented. The objective is to build a very large telescope in the center of the array of the 4 existing ones. Operating the very large telescope in coincidence (stereoscopy) with the four H.E.S.S. I telescopes allows to reduce the energy threshold from 100 GeV to 50 GeV. In order to make optimum use of this additional very large telescope and to lower the energy threshold further, one has to consider the single telescope events of this telescope as well. The data acquisition of these events requires a second level trigger for the reduction of the data flow. The concepts for the realization and properties for a second level trigger are presented.

2009 International Conference on Reconfigurable Computing and FPGAs, 2009

... Each processor system owns a PLB (Processor Local Bus), a D/ILMB (Data/In-struction Local Mem... more ... Each processor system owns a PLB (Processor Local Bus), a D/ILMB (Data/In-struction Local Memory Bus), a BRAM, an interruption controller, a Timer and an UART or a GPIO module. The ... [4] A. Aguiar, SJ Filho, TG dos Santos, C. Marcon, and F. Hessel, Architectural Support ...

2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneou... more Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip. Namely, several processors, hardware accelerators as well as communication networks between all these components. In order to leverage the programming complexity of this kind of platform, applications are described with software threads, running on processors, and hardware threads, running on FPGA partitions. Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration file. Such a feature permits to save critical memory resources. In this article, we propose to tackle the issue of designing fully independent partitions, and especially to avoid the routing conflicts which can occur when using the standard Xilinx FPGA design flow. To achieve the relocation process successfully, we propose a new design flow dedicated to the module relocation, using the standard tools and based on the Isolation Design Flow (IDF), a special flow provided by Xilinx for secure FPGA applications.

2008 Second International Conference on Electrical Engineering, 2008

In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary ... more In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC (NB- LDPC) codes, presented in [4]. To the knowledge of the authors this is the first implementation of an GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem

2007 IEEE International Conference on Communications, 2007

In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes prese... more In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in (D. Declencq and M. Fossorier, 2007). A particularity of the new algorithm is that it takes into accounts the memory problem of the non binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our

IEEE Transactions on Communications, 2000

We present in this paper an architectural model for implementing parallel and scalable low-densit... more We present in this paper an architectural model for implementing parallel and scalable low-density parity-check (LDPC) decoders. This model has been developed for targeting field-programmable gate array devices and system-on-chip (SoC) platforms. We present first the motivations of investigating a new hardware model for regular and irregular LDPC decoders. The code flexibility, the memory usage optimization, and an easy hardware integration have been taken into account. The construction of a specific class of codes (hardware-constrained LDPC codes) is then presented. Parallelization and pseudorandomness constraints of codes are particularly detailed. A complete description of our parallel and scalable hardware model suitable for reprogrammable architectures is then given. Simulation results are presented showing the efficiency of this model with both (3,6) regular and irregular codes.

The integration of dynamically reconfigurable modules into systems-on-chip ensures a certain degr... more The integration of dynamically reconfigurable modules into systems-on-chip ensures a certain degree of flexibility. In fact, it allows systems-on-chip to adapt to variable computation loads, due to the beginning of new tasks or to data dependent processings, for example. In order to get the most advantages of these reconfigurable modules, the operating system must provide the different tasks placement on available targets. This operation has to be performed on-line and must take into account the heterogeneousness of these different targets (software and hardware). In addition, a validation phase is necessary due to the complexity of these applications and systems. This validation can be done on a prototyping platform taking into account the entire system component set. To do so, a general simulation model must be available to evaluate performance application on the chip.