C. Claeys | KU Leuven (original) (raw)
Papers by C. Claeys
A study is made of the impact of embedded epitaxial Si:C source/drain regions on the DC and low-f... more A study is made of the impact of embedded epitaxial Si:C source/drain regions on the DC and low-frequency (LF) noise characteristics of nMOSFETs with 1.4 nitrided oxide gate dielectric. It is shown that a ~10% improvement in ION is achieved for a C concentration of 1%, with ...
Applied Surface Science, 2008
IEEE Transactions on Device and Materials Reliability, 2000
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implem... more In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
![Research paper thumbnail of On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN∕TaN∕HfO[sub 2]∕SiO[sub 2] gate stack](https://attachments.academia-assets.com/47500842/thumbnails/1.jpg)
](Applied Physics Letters, 2008
In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channe... more In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide field effect transistors ͑pMOSFETs͒ with a Si passivated surface. The gate stack consists of HfO 2 / SiO 2 dielectric with TiN / TaN metal gate. The observed temperature dependence of the gate current indicates that the dominant charge transport mechanism through the gate dielectric consists of Poole-Frenkel conduction. Gate current 1 / f noise is more than two orders higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion into the gate oxide is the suspected cause for the enhanced Poole-Frenkel conduction and the high gate current 1 / f noise in Ge pMOSFETs.
IEEE Transactions on Device and Materials Reliability, 2000
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implem... more In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
Materials Science in Semiconductor Processing, 2008
The purpose of this paper is to evaluate the impact of the geometry of embedded Si 1Àx Ge x sourc... more The purpose of this paper is to evaluate the impact of the geometry of embedded Si 1Àx Ge x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si 1Àx Ge x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.
28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
ABSTRACT This paper is conceptual and introduces for the first time a new concept of structural d... more ABSTRACT This paper is conceptual and introduces for the first time a new concept of structural design for FinFETs, the OCTO FinFET, which consists of an evolution of the Diamond layout style. Three-dimensional numerical simulations were performed in order to compare the performance between this new architecture and the conventional counterpart. It is shown that this layout style can significantly improve important parameters such as drain current, transconductance and on-state resistance.
Solid-State Electronics, 2005
This work studies the effect of halo implantation on the electrical characteristics of deep-submi... more This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K-300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.
Solid-State Electronics, 2007
This work studies the impact of uniaxial, biaxial and combined uniaxial–biaxial strain on the lin... more This work studies the impact of uniaxial, biaxial and combined uniaxial–biaxial strain on the linearity of nMOSFETs from a 65nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order harmonic distortion (HD3) will be used as figures of merit. ...
Solid-State Electronics, 2008
This work shows a comparison between the analog performance of standard and strained Si n-type tr... more This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained ...
Microelectronics Reliability, 2012
Triple-gate devices are considered a promising solution for sub-20nm era. Strain engineering has ... more Triple-gate devices are considered a promising solution for sub-20nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time
This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, Ti... more This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
Solid-State Electronics, 2007
This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, Ti... more This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
IEEE Transactions on Electron Devices, 1989
Abstruct-In this paper, detailed substrate current characteristics of nMOST&#x27;s at 4.2... more Abstruct-In this paper, detailed substrate current characteristics of nMOST&#x27;s at 4.2 K are presented and discussed in view of the well-known transient (hysteresis) and kink behavior observed below carrier freeze-out. A great similarity with room-temperature behavior is found, indicating ...
In this paper we describe an analytical model for the gate current 1/f noise in a MOS device. The... more In this paper we describe an analytical model for the gate current 1/f noise in a MOS device. The model is based on a simple idea: one electron trapped in the dielectric switches-off tunneling through the oxide over an equivalent blocking area. The effective trap density inside the dielectric can be extracted as a function of energy from gate current noise measurements. The Gate Noise Parameter (GNP) is introduced as a new figure of merit for the quality of the gate stack. The GNP can be related to physical quantities of the MOS structure on the basis of the proposed model.
IEEE Electron Device Letters, 2006
The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavio... more The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n-and p-channel MOSFETs with high-κ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices.
Microelectronic Engineering, 2007
This work presents the impact of low temperature operation on the characteristics of uniaxially s... more This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The maximum transconductance in linear region was used to evaluate the mobility enhancement. Besides the increased mobility provided by the strain in comparison to its unstrained SOI counterpart, higher mobility degradation for high values of applied gate voltage was observed. The subthreshold slope and the Drain Induced Barrier Lowering (DIBL) of short-channel devices have been also analyzed, showing that strained devices are more susceptible to the occurrence of short-channel effects.
Silicides used commonly for Schottky barrier infrared (IR) imaging arrays, are those of platinum ... more Silicides used commonly for Schottky barrier infrared (IR) imaging arrays, are those of platinum and palladium. Recently good results have also been reported for IR sensitive composed Pt-Ir silicides. The uniformity of the response over large detector arrays and the VLSI fabrication compatibility are their main advantages, as compared to non Schottky type detectors. This paper presents theoretical as well as experimental data on the cobalt silicide as used in Schottky detectors for the short wavelength IR (SWIR) band. The big advantage of a CoSi2 detector, over the conventionally used silicides, is its higher operating temperature allowing passive cooling in space remote sensing applications.
Journal of The Electrochemical Society, 2011
The mechanisms of oxygen precipitation in the SiO 2 phase during rapid thermal annealing of solar... more The mechanisms of oxygen precipitation in the SiO 2 phase during rapid thermal annealing of solar-grade Cz-Si wafers at moderate temperature (850 C) are analysed. A theoretical model is derived to study the kinetics of oxygen precipitate growth that takes into account a significant increase in the non-equilibrium solubility of oxygen and the increased effective diffusivity of oxygen atoms. A mechanism for the mentioned abnormal modifications of the characteristics of oxygen diffusivity and solubility is suggested based on the dominating influence of excess point defects appearing in the Si wafers during the rapid thermal anneals.
A study is made of the impact of embedded epitaxial Si:C source/drain regions on the DC and low-f... more A study is made of the impact of embedded epitaxial Si:C source/drain regions on the DC and low-frequency (LF) noise characteristics of nMOSFETs with 1.4 nitrided oxide gate dielectric. It is shown that a ~10% improvement in ION is achieved for a C concentration of 1%, with ...
Applied Surface Science, 2008
IEEE Transactions on Device and Materials Reliability, 2000
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implem... more In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
Applied Physics Letters, 2008
In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channe... more In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide field effect transistors ͑pMOSFETs͒ with a Si passivated surface. The gate stack consists of HfO 2 / SiO 2 dielectric with TiN / TaN metal gate. The observed temperature dependence of the gate current indicates that the dominant charge transport mechanism through the gate dielectric consists of Poole-Frenkel conduction. Gate current 1 / f noise is more than two orders higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion into the gate oxide is the suspected cause for the enhanced Poole-Frenkel conduction and the high gate current 1 / f noise in Ge pMOSFETs.
IEEE Transactions on Device and Materials Reliability, 2000
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implem... more In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
Materials Science in Semiconductor Processing, 2008
The purpose of this paper is to evaluate the impact of the geometry of embedded Si 1Àx Ge x sourc... more The purpose of this paper is to evaluate the impact of the geometry of embedded Si 1Àx Ge x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si 1Àx Ge x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.
28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
ABSTRACT This paper is conceptual and introduces for the first time a new concept of structural d... more ABSTRACT This paper is conceptual and introduces for the first time a new concept of structural design for FinFETs, the OCTO FinFET, which consists of an evolution of the Diamond layout style. Three-dimensional numerical simulations were performed in order to compare the performance between this new architecture and the conventional counterpart. It is shown that this layout style can significantly improve important parameters such as drain current, transconductance and on-state resistance.
Solid-State Electronics, 2005
This work studies the effect of halo implantation on the electrical characteristics of deep-submi... more This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K-300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.
Solid-State Electronics, 2007
This work studies the impact of uniaxial, biaxial and combined uniaxial–biaxial strain on the lin... more This work studies the impact of uniaxial, biaxial and combined uniaxial–biaxial strain on the linearity of nMOSFETs from a 65nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order harmonic distortion (HD3) will be used as figures of merit. ...
Solid-State Electronics, 2008
This work shows a comparison between the analog performance of standard and strained Si n-type tr... more This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained ...
Microelectronics Reliability, 2012
Triple-gate devices are considered a promising solution for sub-20nm era. Strain engineering has ... more Triple-gate devices are considered a promising solution for sub-20nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time
This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, Ti... more This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
Solid-State Electronics, 2007
This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, Ti... more This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
IEEE Transactions on Electron Devices, 1989
Abstruct-In this paper, detailed substrate current characteristics of nMOST&#x27;s at 4.2... more Abstruct-In this paper, detailed substrate current characteristics of nMOST&#x27;s at 4.2 K are presented and discussed in view of the well-known transient (hysteresis) and kink behavior observed below carrier freeze-out. A great similarity with room-temperature behavior is found, indicating ...
In this paper we describe an analytical model for the gate current 1/f noise in a MOS device. The... more In this paper we describe an analytical model for the gate current 1/f noise in a MOS device. The model is based on a simple idea: one electron trapped in the dielectric switches-off tunneling through the oxide over an equivalent blocking area. The effective trap density inside the dielectric can be extracted as a function of energy from gate current noise measurements. The Gate Noise Parameter (GNP) is introduced as a new figure of merit for the quality of the gate stack. The GNP can be related to physical quantities of the MOS structure on the basis of the proposed model.
IEEE Electron Device Letters, 2006
The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavio... more The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n-and p-channel MOSFETs with high-κ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices.
Microelectronic Engineering, 2007
This work presents the impact of low temperature operation on the characteristics of uniaxially s... more This work presents the impact of low temperature operation on the characteristics of uniaxially strained fully-depleted SOI nMOSFETs. Devices with channel lengths down to 160 nm were explored in the range 100-380 K. The maximum transconductance in linear region was used to evaluate the mobility enhancement. Besides the increased mobility provided by the strain in comparison to its unstrained SOI counterpart, higher mobility degradation for high values of applied gate voltage was observed. The subthreshold slope and the Drain Induced Barrier Lowering (DIBL) of short-channel devices have been also analyzed, showing that strained devices are more susceptible to the occurrence of short-channel effects.
Silicides used commonly for Schottky barrier infrared (IR) imaging arrays, are those of platinum ... more Silicides used commonly for Schottky barrier infrared (IR) imaging arrays, are those of platinum and palladium. Recently good results have also been reported for IR sensitive composed Pt-Ir silicides. The uniformity of the response over large detector arrays and the VLSI fabrication compatibility are their main advantages, as compared to non Schottky type detectors. This paper presents theoretical as well as experimental data on the cobalt silicide as used in Schottky detectors for the short wavelength IR (SWIR) band. The big advantage of a CoSi2 detector, over the conventionally used silicides, is its higher operating temperature allowing passive cooling in space remote sensing applications.
Journal of The Electrochemical Society, 2011
The mechanisms of oxygen precipitation in the SiO 2 phase during rapid thermal annealing of solar... more The mechanisms of oxygen precipitation in the SiO 2 phase during rapid thermal annealing of solar-grade Cz-Si wafers at moderate temperature (850 C) are analysed. A theoretical model is derived to study the kinetics of oxygen precipitate growth that takes into account a significant increase in the non-equilibrium solubility of oxygen and the increased effective diffusivity of oxygen atoms. A mechanism for the mentioned abnormal modifications of the characteristics of oxygen diffusivity and solubility is suggested based on the dominating influence of excess point defects appearing in the Si wafers during the rapid thermal anneals.