Claudius Dan | Universitatea Politehnica din Bucuresti (original) (raw)

Papers by Claudius Dan

Applications of wavelet analysis are widespread and cover many fields of scientific research incl... more Applications of wavelet analysis are widespread and cover many fields of scientific research including image processing, classification and recognition. The artificial vision systems was developed having as model the human system, and therefore the objects recognition task is reduced to a classification: the recognition of an initial unknown object through detection of the similarities to another object, previously learned. Our purpose is to study the obstacle recognition in the ruttier scene using wavelet transform. We compared different recognition rates obtained by the use of different mother wavelet functions (as Daubechies, Coiflet, Biorthogonal and the recent discovered ones, named fractional B-splines).

IEEE Power Engineering Review, 1983

2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003

This paper evaluates the design trade-offs for a high frequency RF front-end. The main three fact... more This paper evaluates the design trade-offs for a high frequency RF front-end. The main three factors - gain, linearity, noise - influence is analyzed, in order to get an optimum performance for the receiver. The analysis is focused on the weight of the main blocks (the low noise amplifier - LNA and the mixer) parameters oil the RF frontend operation.

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997

Compared with more advanced wireless telecommunication systems such as GSM, the pager offers the ... more Compared with more advanced wireless telecommunication systems such as GSM, the pager offers the advantages of a lower cost, a smaller size and a longer battery autonomy. Furthermore, the RDS pager system allows reuse of the existing network of FM radio broadcasting stations, reducing the cost of introduction of the pager network and allowingimmediately a large geographical coverage. The realization of the RDS baseband decoder described below is a first step of an attempt to increase the pager battery autonomy from a few weeks to more than a half year. Modern FM transmitters transmit a radio signal in the frequency range between 84MHz and 108MHz. The modulating MPX signal

Abstract: In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0... more Abstract: In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm integrated technology, to be used in a UMTS transceiver having the following specifications: f=1.95 GHz, VDC=1 V, Pout=0.5 W. The designed class-E network accommodates the simultaneous presence of a parasitic ground in-ductance and losses in the switch and shunt-capacitor. The transistor is dimensioned for an optimum PAE (power added efficiency). Finally, we simulate the power con-trol capabilities and highlight linearization methods.

Lucrarea analizează compromisul dintre zgomotul de fază, aria şi consumul de putere ce defineşte ... more Lucrarea analizează compromisul dintre zgomotul de fază, aria şi consumul de putere ce defineşte proiectarea sintetizoarelor de frecvenţă utilizate în transiverele reconfigurabile de bandă largă, urmărind identificarea unei arhitecturi optime pentru sintetizatorul de frecvenţă, ţinând cont de particularităţile proiectării de radiofrecvenţă. Lucrarea descrie şi analizează principalele surse de zgomot din circuit şi construieşte un model în baza căruia performanţele de zgomot ale sintetizorului pot fi simulate cunoscându-se contribuţiile individuale ale sub-blocurilor componente. În urma acestei analize, este dezvoltată o nouă arhitectură a sintetizorului de frecvenţă ce implementează două filtre trece jos, unul extern, ce optimizează zgomotul de fază, şi unul intern, de dimensiuni reduse, ce optimizează aria şi consumul de putere. This paper presents the phase noise and area-power consumption trade-off defining the frequency synthesizers used in Software Defined Radio Transceivers (S...

2018 International Semiconductor Conference (CAS), 2018

This paper presents a 5V LDO architecture with a buffered error amplifier. This is achieved by us... more This paper presents a 5V LDO architecture with a buffered error amplifier. This is achieved by using a functional block called a dual complementary buffer which consists of two buffers, one using a NMOS output transistor, the other a PMOS output transistor. The main advantage of this architecture is the rail-to-rail output voltage swing of the buffer, improving performance in both the tracking and the regulating operating regions of the voltage regulator. Simulation results show load regulation of 4.47uV/mA and line regulation of 3.92uV/v. The maximum input voltage is 40V and the maximum load current is 200mA. The LDO was simulated using a 0.8um BiCMOS process.

In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35μm inte... more In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35μm integrated technology, to be used in a UMTS transceiver having the following specifications: f=1.95 GHz, VDC=1 V, Pout=0.5 W. The designed class-E network accommodates the simultaneous presence of a parasitic ground inductance and losses in the switch and shunt-capacitor. The transistor is dimensioned for an optimum PAE (power added efficiency). Finally, we simulate the power control capabilities and highlight linearization methods.

This paper presents a translinear topology suitable for static and dynamic analog signal processi... more This paper presents a translinear topology suitable for static and dynamic analog signal processing at very low supply voltage. The one variable objective functions, are piecewise linear approximated and finally implemented using CMOS translinear networks. The use of these functions offers both the advantage of small computational time and of implementations with controllable errors and good stability. This topology is used in a structural synthesis program for automated synthesis of translinear circuits.

2001 International Semiconductor Conference. CAS 2001 Proceedings (Cat. No.01TH8547)

This paper presents a new low-power threshold logic family with self lock-out property. The simul... more This paper presents a new low-power threshold logic family with self lock-out property. The simulated results have shown that, the proposed threshold logic dissipates between 10% and 79% less power and between 57% and 71% less energy, at VDD=5 V, when compared with previous similar threshold logic families. Moreover, at VDD =3.3 V, it has between 12% and 48% less

9th International Conference on Electronics, Circuits and Systems

This paper presents a new low-power Threshold Logic family featuring self lock-out and run-time r... more This paper presents a new low-power Threshold Logic family featuring self lock-out and run-time reprogrammability. The simulated results have shown that, the proposed Threshold Logic dissipates between

Proceedings. International Semiconductor Conference

In this paper we propose a new compact static delay model for latch-based CMOS Threshold logic ga... more In this paper we propose a new compact static delay model for latch-based CMOS Threshold logic gates. The particular effects captured by the model are: the dependency of the delay on threshold (data) values and the dependency of the delay vs. capacitive loading. The model parameters were extracted from several Threshold logic gate setups and the delay predicted by the model for a computer arithmetic basic circuit fully agree with circuit simulations.

CAS '99 Proceedings. 1999 International Semiconductor Conference (Cat. No.99TH8389)

... Iuliu Maniu 1-3, 77202, Bucharest, ROMANIA Phone: +0040;1-3 12 2452; e-mail:marius@mESsnet.pu... more ... Iuliu Maniu 1-3, 77202, Bucharest, ROMANIA Phone: +0040;1-3 12 2452; e-mail:marius@mESsnet.pub.ro Delft University of Technology, Mekelweg 4,2628, CD ... smaller perturbation in the common node because the worst-case row perturbation is inversely ...

Proceedings of the Fifth …, 2008

TLSS A POWERFUL SOFTWARE TOOL FOR STRUCTURAL SYNTHESIS OF TRANSLINIAR INTEGRATED CIRCUITS Elena... more TLSS A POWERFUL SOFTWARE TOOL FOR STRUCTURAL SYNTHESIS OF TRANSLINIAR INTEGRATED CIRCUITS Elena Doicaru1 , Ileana Nicolae1 , Claudius Dan2 , Dan - Ovidiu Andrei1 1 University of Craiova, Faculty of Automation, Computer Science and Electronics ...

SpringerBriefs in Electrical and Computer Engineering, 2016

ABSTRACT This paper analyzes the gain – noise – linearity partitioning in multi-standard radio re... more ABSTRACT This paper analyzes the gain – noise – linearity partitioning in multi-standard radio receivers embedding baseband analog signal conditioning. The presented novel gain partitioning strategy tailored towards multi-standard radio receivers optimally mitigates the extreme reception conditions specific to the wireless environment. Based on a first order system level analysis, the paper develops a standard independent methodology that drives the gain partitioning strategy and enables the designer to handle efficiently the large amount of information from the envisaged wireless standards. The receiver gain is split between an RF front-end embedding programmable gain and a high-dynamic range Variable Gain Amplifier (VGA). As the receiver NF and IIP3 change with the RF front-end gain, we proposed a generic algorithm to find the optimal gain partitioning between the receiver's two variable gain blocks.

ABSTRACT This paper analyzes the noise–linearity breakdown in direct conversion multi-standard ra... more ABSTRACT This paper analyzes the noise–linearity breakdown in direct conversion multi-standard radio receivers embedding analog signal conditioning. The paper’s main goal is to develop a systematic noise–linearity partitioning methodology to be used in splitting the multi-standard receiver noise and linearity budget between its high frequency (HF) part and its low frequency (LF) baseband part. To this aim, a new and efficient design methodology tailored towards multi-standard receivers, and based on manual analysis, is developed. By using the developed methodology, power saving is enabled in the HF part through changing the multi-standard receiver HF part noise and linearity performance with its RF front-end gain. While for the LF part, the analysis revealed the performance can be kept the same to allow power optimization through dedicated circuit design.

ABSTRACT This paper analyses the key trade-off that shapes the design of direct conversion radio ... more ABSTRACT This paper analyses the key trade-off that shapes the design of direct conversion radio receivers embedding analog signal conditioning: the trade-off between the receiver area, determined by its anti-alias Low Pass Filter (LPF) order, and its power consumption, constrained by the ADC specifications of resolution and speed. The paper's main goal is to determine the receiver's LPF order that enables the complete analog channel selection in the context of a multi-standard receiver implementation. Based on the multi-standard receiver generic blocker diagram analysis, a first order, system level analysis is used to determine the LPF order. The analysis is constructed from the circuit / transistor level designer perspective and is also used for estimating the impact of the complete analog channel selection on the receiver RF front-end power consumption and area. Thus, by using this analysis methodology the designer is enabled to handle efficiently the large amount of information required for designing multi-standard radio systems.

In this paper are presented two current mode techniques for low-voltage, continuous-time, analogu... more In this paper are presented two current mode techniques for low-voltage, continuous-time, analogue filter implementation. The first presented technique is adequate for very low power application and is based on a translinear approach. The second presented technique is adequate for high frequency application. In the paper, firstly, the state-space description and the used synthesis techniques of current-mode filters are presented. Then the two different current-mode integrators are presented and analyzed. Finally, as a test vehicle for the proposed techniques, two low voltage, third order, continuous-time filters, for low power applications structure implementation are described and analyzed.