An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA (original) (raw)
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Jitter tolerance calibration for high-speed serial interfaces
Integration, 2017
A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI standard specification. As an example, the proposed solution is applied for the jitter tolerance simulation and characterization of the most updated M-PHY ver.3 HSSI standard for mobile applications. A comprehensive method for the calculation of the jitter noise frequency ingredients and the calibration of jitter noise sources is also proposed resulting a jitter tolerance mask compliant with the M-PHY ver.3 specifications. Using the proposed implementation the transistor level and behavioral modules co-simulation time could be significantly minimized.
Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems
2007 IEEE Electrical Performance of Electronic Packaging, 2007
Although it is well understood that a band-limited passive system can be a source of deterministic jitter, it is less obvious that the deterministic and random jitters generated by the clock or data source can be enhanced significantly by the passive channel. In this paper, modeling and simulation techniques to predict jitter enhancement across interconnect systems are presented. The conventional method of using SPICE to calculate output jitter is computationally expensive. Instead, the effect of channel on input jitter can be represented by jitter impulse response or jitter transfer function in time or frequency domains, respectively. These jitter characteristic functions can then be used to efficiently determine the increase in jitter as signal propagates across an interconnect system. The probability mass function of jitter impulse response can also be constructed to statistically predict the jitter enhancement at lower bit-error rate. Finally, the results form SPICE-based simulation and those obtained using the jitter characteristic functions are compared.
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
IEEE Journal of Solid-State Circuits, 2018
We present a technique to measure random jitter in a phase interpolator (PI)-based clock and data recovery (CDR) circuit by injecting a controlled amount of square-wave jitter into its edge clock and monitoring its effect on the autocorrelation function of the CDR's bang-bang phase detector output. Jitter is injected by adjusting the code of the edge PI while the autocorrelation function is measured by on-chip counters. Since the injected jitter only affects the edge clock, the CDR remains operational during jitter injection. Using this technique, the rms relative jitter between the clock and data at the CDR input can be estimated with sub-picosecond accuracy as demonstrated in measurements of a 28 Gb/s half-rate digital CDR fabricated in 28 nm CMOS.
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance
IEEE Journal of Solid-State Circuits, 2007
This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs
IEEE Journal of Solid-State Circuits, 2015
On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, the jitter of random data is measured on-chip by correlating the phase detector outputs from two adjacent CDR lanes. This allows the jitter's autocorrelation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. The RMS value of random jitter ranging from 0.85 ps to 1.89 ps, and sinusoidal jitter from 0.89 ps to 5.1 ps is measured in PRBS31 data with less than 0.6 ps of error compared to measurements by an 80 GS/s real-time oscilloscope. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the recovered clock jitter. Sinusoidal jitter from 1.8 ps to 5.3 ps is measured in the recovered clock with an error of less than 1 ps. Index Terms-Clock and data recovery, CDR, jitter, jitter measurement, on-chip measurement.
Built-in jitter test schemes for mixed-signal integrated circuits
1996
In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of fJLclf'i rxc*-*' ^
2004
As data rates move towards the Gbps regime, effects that may have been ignored at lower data rates are becoming significant. Such signal integrity issues decrease the timing budget of I/O interconnects exponentially and hence, place a stringent requirement on the total jitter budget. The issues that affect signal integrity also affect jitter as both share many common root causes. Jitter can be divided into different subcomponents each with different root causes and properties. Crosstalk Jitter, or commonly referred in the industry as Bounded Uncorrelated Jitter (BUJ), is a jitter subcomponent that is mostly caused by crosstalk coupling from the adjacent interconnects on printed-circuit boards (PCB). However, the characteristics of BUJ are still ill understood. In addition, a mathematical model of jitter and an algorithm to generate a histogram for BUJ have not been developed to this date. The crosstalk-induced pulse characteristic from an aggressor signal is studied here. Based on t...
This paper presents an advanced methodology for extrapolating the Bit Error Rate (BER) up to BER E-15 during receiver jitter tolerance testing. The methodology incorporates the utilization of jmp tool software for data post-processing, facilitating the determination of the required slope to achieve the target BER. The study specifically concentrates on the data rates ranging from 16 Gbps to 32 Gbps, adopting the Non Return Zero (NRZ) mode, and conducting evaluations on the margins of UX IP at the 12.65 process node. The research outcomes not only demonstrate the margin of UX IP but also provide comprehensive insights into its performance, offering an effective statistical extrapolation approach through the utilization of jmp tools. The overall efficiency gain achieved amounts to 50%, demonstrating significant improvements in BER extrapolation techniques for engineers.