Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems (original) (raw)
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Single ended 6T SRAM with isolated read-port for low-power embedded systems
Proceedings of the …, 2009
This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-V dd and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65nm CMOS technology node to evaluate and compare different ...
A single ended 6T SRAM cell design for ultra-low-voltage applications
IEICE Electronics Express, 2008
In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic 'one' is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.
Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement
Electronics, 2021
To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology.
Ultra low voltage and low power Static Random Access Memory design using average 6 . 5 T technique
2015
Power Stringent Static Random Access Memory (SRAM) design is very much essential in embedded systems such as biomedical implants, automotive electronics and energy harvesting devices in which battery life, input power and execution delay are of main concern. With reduced supply voltage, SRAM cell design will go through severe stability issues. In this paper, we present a highly stable average nT SRAM cell for ultra-low power in 125nm technology. The distinct difference between the proposed technique and other conventional methods is about the data independent leakage in the read bit line which is achieved by newly introduced block mask transistors. An average 6.5T SRAM and average 8T SRAM are designed and compared with 6T SRAM, 8T SRAM, 9T SRAM, 10T SRAM and 14T SRAM cells. The result indicates that there is an appreciable decrease in power consumption and delay.
Low power single bitline 6T SRAM cell with high read stability
2011
This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-alone SRAM applications. The data is retained by the cell with the help of leakage current and positive feedback, and does not use any refresh cycle. The size of the new cell is comparable to the conventional six-transistor cell of same technology and design rules. Also, the proposed cells uses a single bit-line for both read and write purposes. The cell proposed in this paper consumes less dynamic power and has higher read stability than the standard one. In conventional six-transistor (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. In existing SRAM topologies of 8T, 9T and higher transistor count, the read static noise margin (SNM) is increased but size of the cell and power consumption increases relatively. In the proposed technique, the SRAM cell operates by charging/discharging of a single bit-line (BL) during read and write operation, resulting in reduction of dynamic power consumption to only 40% to 60% (best case/worst case) of that of a conventional 6T SRAM cell. The power consumption is further decreased if the switching operational voltage of the bit-line lies between 0.25VDD to 0.5VDD. All simulations are done using 0.18um Technology.
Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell
International journal of physical sciences
In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and analyzed a 32 kb 1-port SRAM using 45 nm CMOS technology. The six-transistor SRAM cell size is 1.25 µm 2 . Evaluation shows that the standby current of 32 kb SRAM is 1.2 µA at 1.2 V and room temperature. It was reduced to 7.5% of the conventional SRAM.
This paper presents analysis of the Static Noise Margin (SNM), power dissipation, access time and dynamic noise margin of a novel low power proposed 8T Static Random Access Memory (SRAM) cell for read operations. In the proposed structure, two voltage sources are used, one is connected with the bit line and the other is connected with the bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. Simulation results for the read static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other SRAM cells, reported in di erent literatures. It is shown that the proposed SRAM cell has better static noise margin and dissipates less power in comparison to other SRAM cells. Analog and schematic simulations have been done in a 45 nm environment with the help of Microwind 3.1, using the BSimM4 model.
SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems. This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) Cell and Dynamic Random Access Memory (DRAM) Cell to perform high speed to develop low power consumption. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 6-transistor SRAM cell built from a simple static latch and tri state inverter and 3-transistor DRAM cell. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines. Results show good performance.
Design and comparison of Single Bit SRAM Cell Under different Configurations
Memory is widely used in all electrical systems mainframes microcomputers and cellular phones etc. From the last more than five decades we are scaling down the size of the CMOS devices to make the devices portable and compact in size and to get better performance in terms of access time, power dissipation, delay etc. More memory means more information therefore more size and so more power consumption. Thus the demand for low size and low power memory has been raised. Working of low supply voltage and leakage energy has become main concern as the power consumption can be reduced significantly. We, in our work have designed the low power SRAM memory cells, which are used to store single bit information, under different configurations (6T, 8T, 9T) and compared various parameters of these cells. We have carried out the simulation work using Tanner SPICE. However, there is no universal way to avoid trade-offs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product needs.
Design and Analysis of 1-Bit SRAM
International Journal of Engineering Research and, 2020
SRAM (Static Random-Access Memory) is a memory component and is used in various VLSI chips due to its unique capability to retain data. This memory cell has become a subject of research to meet the demands for future digital electronics and communication systems. SRAM is a major data storage device due to its large storage density, less time to access and consumes less power. It does not require refreshing periodically which makes it the most popular memory cell among VLSI designers. Hence continuous work is going on for the better performance of SRAM cells. In this paper 6T SRAM cell circuit is designed for 1-Bit storage. The design is synthesized using the LTspice software tool and the analysis of important memory parameters like read access time, write access time, power and number of transistors is performed.