Design and Implementation of Sub Micron Level 10T Full Adder in ALU Using Cell Based and SOC Technology (original) (raw)

Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso Platform

International Journal of VLSI Design & Communication Systems, 2013

Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nano meter technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. This proposed work illustrates the design of the low-power less transistor full adder designs using cadence tool and virtuoso platform, the entire simulations have been done on 180nm single n-well CMOS bulk technology, in virtuoso platform of cadence tool with the supply voltage 1.8V and frequency of 100MHz. These circuits consume less power with maximum (6T design)of 93.1% power saving compare to conventional 28T design and 80.2% power saving compare to SERF design without much delay degradation. The proposed circuit exploits the advantage of GDI technique and pass transistor logic.

Design and Simulation of Low Power 10T Full Adder using Cadence 16nM Technology

IJRASET, 2019

This paper presents the design of low voltage low power 10T full adder with minimum leakage power, and its transient analysis with cadence tools. Adder is the basic building block of Arithmetic in digital circuits, the area and power consumption of adder plays a vital role in portable devices. The low voltage low power full adder circuits are widely used in portable applications as it improves the battery lifetime. In this paper we have presented the design, simulation and comparative analysis of 27T and 10T full adder topologies with various supply voltages and lower technology node at Cadence Virtuoso TSMC 16nM technology.

DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY

With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure.

Design And Analysis Of Low Power High Performance Single Bit Full Adder

Adder is the significant circuit in arithmetic operations. Adder cells are designed for power and delay reduction. Now ground bounce noise is also necessary for good performance. In this paper the full adder is designed using only 8 Transistors using Pass Transistor Logic (PTL). The power gating technique is one such a best technique which reduces leakage power through the ground. This technique is implemented using sleep transistor added between ground rail and actual ground. Here a single bit 8 Transistor full adder is proposed. We will perform analysis and simulation of various parameters like power, delay and ground bounce noise using tanner EDA tool 180nm CMOS Technology.

Low Power and High Performance Full Adder in Deep Submicron Technology

2014

The leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. Increasing leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This work presents the performance of different full adders in deep-submicron using 45nnm, 65nm and 90nm technology. Finally, the paper explores different circuit techniques to estimate the leakage power consumption has been presented. An illustrative example has been provided to demonstrate the design and simulation of CMOS with various technologies using DSCH and MICROWIND program.

High Performance ALU Using Carry Look-ahead Adder

CVR Journal of Science & Technology, 2018

A Low Power 8-bit Arithmetic Logic unit (ALU) using a Carry look-ahead adder (CLA) and placing Low Vt (LVt) cells in Critical path is anticipated. The ALU is designed in 90nm CMOS technology. ALU is the most essential circuit in any processor. It consists of AE, LE, CLA and CE. This ALU is designed to calculate Arithmetic and Logical operations. Power and Delay values of different 8-bit adders like CLA, Sparse and Ripple Carry Adder (RCA) are designed and compared. The simulation results show that the design of ALU using CLA and incorporating High Vt and Low Vt cells in the CLA gives more power and delay efficient than with only Standard threshold voltage cells.

Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications

For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. As technology scales into the nano meter regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this project, low leakage 1-bit full adder cells are proposed for mobile applications. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. Since, Adders are heart of computational circuits and many complex arithmetic circuits are based on the addition. The vast use of this operation in arithmetic functions attracts a lot of researcher's attention to adder for mobile applications. In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells. Therefore a new transistor resizing approach for 1-bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power has been proposed. The simulation results depicts that the proposed design also leads to efficient 1-bit full adder cells in terms of standby leakage power. In order to verify the leakage power, various designs of full adder circuits are simulated using DSCH, Micro wind and Virtuoso (Cadence).

IJERT-Low Power CMOS Full Adder Design with Sleep Transistor for Submicron VLSI Technologies

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/low-power-cmos-full-adder-design-with-sleep-transistor-for-submicron-vlsi-technologies https://www.ijert.org/research/low-power-cmos-full-adder-design-with-sleep-transistor-for-submicron-vlsi-technologies-IJERTV2IS110197.pdf Any computational circuit is incomplete without the use of an adder. Addition is one of the primary operations in arithmetic circuits. These adder cells commonly aimed to reduce power consumption and delay. These studies have also investigated different approaches realizing adders using CMOS technology. The designer's concern for the level of leakage current is mainly aimed at minimizing power dissipation. For portable electronic devices this equates to maximizing battery life. When a mobile phone is in standby mode, certain portions of the circuitry are shut down. Even though de-activated, these circuits have some leakage current flowing through them. Even if the leakage current is much smaller than the normal operating current of the circuit, it depletes the battery charge over the relatively long standby time, whereas the operating current during talk time only depletes the battery charge over the relatively short talk time. As a result, the leakage current has a disproportional effect on total battery life. In this project leakage power and the ground bounce noise is considerably reduced by the use of sleep transistor in full adder design. Size of the sleep transistor is determined by transistor resizing approach. 4 bit adder is implemented using 1 bit adder as reference. The simulation shows that, the 1 bit and 4 bit adders are efficient in terms of standby leakage power, active power and ground bounce noise. Simulations have been performed by using 130 nm CMOS. Electric Tool is used to design the schematic and layout level diagrams of our project. The LT-SPICE Tool will be used for simulation of the Spice code which tests the functionality of our generated layout and schematic blocks.

Design and Analysis of Different Type Single Bit Adder for ALU Application

In these dissertation four types of 1-bit adder has been designed and simulated using 180nm CMOS technology in tanner tool at a various supply voltage from1.0V to 1.8 V & compare their results with respect to various parameters like delay, area & power consumption. The adder is the most commonly used arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its performance and power optimization is of utmost importance. With the technology scaling to deep sub-micron, the speed of the circuit increases rapidly. Due to continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. At the same time, the power consumption per chip also increases significantly due to the increasing density of the chip. Therefore comparison has been carried out by assuming the circuits with minimum size transistors, to minimize the power consumption. Power consumption is a function of load capacitance, frequency of operation, and supply voltage. A reduction of any one of these parameter is beneficial. A reduction in power consumption provides several benefits. Less heat is generated, which reduces problems associated with high temperature, such as the need for heat sinks. This provides the consumer with a product that costs less.

Design and analysis of low run-time leakage in a 10 Transistors full adder in 45nm technology

2016 IEEE Region 10 Conference (TENCON), 2016

In this paper a new full adder is proposed. The number of Transistors used in the proposed full adder is 13.Average leakage is 62% of conventional 28 transistor CMOS full adder. The leakage power reduction results in overall power reduction. The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools.