High performance 0.1µm CMOS device with suppressed parasitic junction capacitance and junction leakage current (original) (raw)
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Solid-State Device Research European Conference, 2002
High performance 0.1µm MOSFETs with a 70nm physical gate length and 1.7nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current (Ileak,j), high speed/low power transistors are fabricated with a superior driving current. Careful optimization in channel, pocket and source/drain (S/D) doping profile results in a reduction of N+/PW area junction capacitance (Cja) to 0.8fF/µm 2 and P+/NW Cja to 0.7fF/µm 2 . In addition, area diode leakage current (Ileak,a) <50nA/cm2 and periphery diode leakage current (Ileak,p) <0.1fA/µm are achieved. In this work, NMOS drive current and PMOS drive current are 840µA/µm and 380µA/µm respectively, at 1.2V with an off-state current (Ioff) 15nA/µm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator has 10.5ps/stage at 1.2V operation.
A high-performance 0.25- mu m CMOS technology. II. Technology
IEEE Transactions on Electron Devices, 1992
In this paper, the key technology elements and their integration into a high-performance, selectively scaled, 0.25-pm CMOS technology are presented. Dual poly gates (n' for nFET and p+ for pFET) are fabricated using a process, where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate, such as work Function and boron penetration through thin gate oxide (7 nm) are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi2) process. The TiSi, thickness is reduced, as compared with the 0.5-pm CMOS process, to maintain the low leakage and low contact resistance for the shallow S / D junctions. To achieve low silicide sheet resistance, RTA processing is used, replacing the furnace anneals. The gate level with 0.4-pm physical length is defined using optical lithography with contrast enhanced layer (CEL) resist system. The CEL offers improved resolution and process control by producing vertical resist profiles down to the minimum dimensions. It also significantly reduces the interference effects and therefore the linewidth sensitivity to the resist thickness variations over topography *
Performance Analysis of NMOS for Higher Speed and Low Power Applications
… (FutureTech), 2010 5th …, 2010
Integrated circuits based on low supply voltage and subthreshold operations of NMOS devices are very attractive for low power applications. An effective way to reduce supply voltage and resulting in power consumption without losing the circuit performance of NMOS is to increase the drive current of NMOS. This paper reports the scaling analysis of NMOS from deep-submicron to nanometer technologies,
A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications
2000
A modular 0.13 /spl mu/m CMOS platform has been developed to support a wide range of applications, including embedded non-volatile memory (NVM). The high performance core device with a 18 /spl Aring/ gate oxide supports the high end needs of the technology. In addition, medium performance and low leakage 25 /spl Aring/ devices are provided in the technology platform to service the low power applications, with low off-state leakage. The peripheral I/O devices support both 2.5 V (50 /spl Aring/) and 3.3 V (70 /spl Aring/) interfaces. Gate lengths range from 110 to 80 nm. Optical enhancement techniques allow use of 248 nm KrF lithography to meet the patterning needs. The interconnect technology allows for two low-k dielectric options with K-values in the range from 2.9 to 3.6. Aggressive design rules, fully compatible with 248 nm KrF systems allow for high logic densities and a 2.48 um/sup 2/ 6T embedded SRAM cell. The technology has been exercised using a 4MB SRAM test vehicle with good yields.
Device design, fabrication and characterization of 0.8 μm CMOS technology
1998
An intensive study has been conducted for the development of the MIMOS 0.8 μm CMOS technology. Issues such as device design and characterization have been given much consideration. NMOS and PMOS transistors have been designed from basic concepts and using simulation tools such as TSUPREM-4 and MEDICI. Device design constraints such as threshold voltage variation, off-state leakage current and drain-induced barrier lowering (DIBL) effects have been seriously examined to improve device performance. Furthermore, performance criteria such as drive current capability have also been examined. Extraction of device characteristics from silicon has been performed on a test chip. Based on experimental results, numerous I-V plots are presented and the data are discussed in terms of output and transfer characteristics and surface DIBL leakage current
Very Low-Voltage Operation Capability of Cmos Ring Oscillators and Logic Gates
2004
Operation of complementary metal-oxide-semiconductor ͑CMOS͒ logic gates at low supply voltages down to 100 mV and ring oscillators down to 67 mV is experimentally investigated. The measured voltage transfer characteristics of CMOS inverters and logic gates are explained using the subthreshold operation of MOS transistors. Robust control of ring oscillators allows for a tuning range of six decades in frequency with excellent sensitivity as low as 75 mV per frequency decade at low voltages in the range from 0.2 to 0.5 V, when body biasing of the metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ is also used. For the present state-of-the-art CMOS, the simple digital CMOS cells can operate properly at supply voltages down to 0.2 V, but to achieve operation at lower voltages, additional circuitry is needed to maintain the matching between p-and n-MOSFETs, and the circuit complexity increases. Nevertheless, the experiments with ring oscillators demonstrated good performance of CMOS circuits down to the physical limit of two to three times the thermal voltage, while logic gates with stacked transistors need a supply of approximately four to six times the thermal voltage.
Low power high speed CMOS circuit design
2011 International Conference on Emerging Trends in Networks and Computer Communications (ETNCC), 2011
A novel low-power and high-speed master-salve Latches is proposed in this paper, thus the improvement of flipflops and latches is one of the most critical tasks to enhance the system performance. The circuits are simulated on Tanner EDA tool with BSIM3V3 45nm CMOS technology for the calculation and comparison power delay product and both PDP and delay are better then other circuits. They are not only responsible for correct timing, functionality, and performance of the chips, but also their clocked devices consume a significant portion of the total active power. With increasing requirement for high-speed and low power, flip-flops with fewer transistors are preferred for their low power consumption and small area occupation.
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 2006
The operation of a CMOS ring oscillator with supply voltage values as low as ~80 mV are experimentally investigated. The low-voltage operation of the ring oscillator based on a single inverter, is analyzed. The use of body voltage of MOS transistors as a means for controlling the frequency of oscillation of CMOS ring oscillators are demonstrated. The feasibility of very low-voltage operation of logic CMOS gates such as NAND gate is confirmed with simulation.
INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY, 2016
The invention of the metal oxide semiconductor (MOS) transistor has aided the semiconductor industry to distinguished itself by the rapid pace of improvement in its products. This has resulted from the ability of the industry to double the number of transistors per chip approximately every twenty four months in the last 50 years thereby decreasing the unit cost while improving functionality. Power dissipation and removal in devices became a major problem due to high transistor number and high frequency of operation. Complementary MOS process was introduced to mitigate the power loss. Power Loss in a typical CMOS circuit is classified basically as dynamic or static loss. In both cases the loss arises from the transfer of charge from the supply voltage to the ground. The power loss in sub-nanometer level transistors has made it impossible to meet ITRS road map in the last decade leading to the search fornew devices and ideas that will realize some " beyond CMOS " capabilities.This work discusses the limitations of CMOS, trends in improving the process and the possible direction in the fight to reduce the leakage power and continue with the growth in the semiconductor industry.
CMOS scaling into the 21st century: 0.1 µm and beyond
IBM Journal of Research and Development, 2000
This paper describes the design, fabrication, and characterization of 0.1 -pm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2x performance gain over 2.54, 0.25-pm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20x reduction in active power per circuit is obtained at a supply voltage e1 V with the same delay as the 0.25-pm CMOS. These results demonstrate the feasibility of highperformance and low-power room-temperature 0.1-pm CMOS technology. Beyond 0.1 pm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed.