Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks (original) (raw)
Related papers
Standby Leakage Power Reduction Techniques in Deep Sub-Micron CMOS VLSI Circuits
Ijca Proceedings on International Conference on Communication Technology, 2013
Standby Leakage Power Reduction in Digital Circuits
2015
Review of Leakage Power Reduction in CMOS Circuits Cite This Article
Review of Leakage Power Reduction in CMOS Circuits
American Journal of Electrical and Electronic Engineering, 2014
LEAKAGE POWER REDUCTION TECHNIQUE IN CMOS CIRCUIT: A STATE-OF-THE-ART REVIEW
Estimation of leakage power and delay in CMOS circuits using parametric variation
Perspectives in Science, 2016
International Journal of Computer Applications, 2013
Microelectronics Journal, 2010
IJERT-Comparison of Various Leakage Power Reduction Techniques for CMOS Circuit Design
International Journal of Engineering Research and Technology (IJERT), 2013
Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits
2010
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS
Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs
International Journal of Computer Applications, 2014
bindu madhavi, Mamidala Pallavi
Standby Mode Subthreshold Leakage Power Analysis in Digital Circuits with Variations in Temperature
Journal of Computer Science IJCSIS
TRANSISTOR GATING: A Technique for Leakage Power Reduction in CMOS Circuits
2012
Leakage Power and Area Optimization in Cmos Logic Design in Sub Micron Technology
2017
International Journal of Computer Applications, 2013
Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits
SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology, 2022
Leakage Current Reduction Techniques for CMOS Circuits.
International Journal of Engineering Sciences & Research Technology, 2014
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment
2002
Leakage current in low standby power and high performance devices
Proceedings of the 2002 international symposium on Physical design - ISPD '02, 2002
Reduction Of Leakage Current And Power In CMOS Circuits Using Stack Technique
Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies
IEEE Transactions on Circuits and Systems II: Express Briefs, 2000
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Proceedings of The IEEE, 2003
A New Technique for Leakage Power Reduction in CMOS circuit by using DSM
International Journal of Computer Applications
FACTA UNIVERSITATIS Series: Electronics and Energetics, 2021