Kaushik Roy - Academia.edu (original) (raw)

Papers by Kaushik Roy

Dual threshold technique has been proposed to reduce leak-age power in low voltage and low power ... more Dual threshold technique has been proposed to reduce leak-age power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path s to maintain the performance. Mixed-Vth MVT ...

Reduction in leakage power has become an important concern in low v oltage, low p o w er and high... more Reduction in leakage power has become an important concern in low v oltage, low p o w er and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using lowthreshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been veri ed by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50.

... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borka... more ... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles Hawkins', Kaushik Roy* and Vivek De MicroComputer Research Labs, 'The University of New Mexico, and 'Purdue University Intel Corporation, Hillsboro, OR 97124, USA ...

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1999

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contribu... more Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I D DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

Abstract| Low supply voltage requires the device threshold to be reduced in order to maintain per... more Abstract| Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been veri ed by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuit... more The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low leakage state and insert leakage control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone.

ACM Transactions on Design Automation of Electronic Systems, 1997

IEEE Transactions on Very Large Scale Integration Systems, 1999

Page 1. 16 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 1, MARCH... more Page 1. 16 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 1, MARCH 1999 Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications Liqiong ...

Set-associative caches achieve low miss rates for typical applications but result in significant ... more Set-associative caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-associative caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent accessing the other ways is wasted. Eliminating the wasted energy by performing the data lookup sequentially following the tag lookup substantially increases cache access time, and is unacceptable for high-performance L1 caches. In this paper, we apply two previously-proposed techniques, way-prediction and selective direct-mapping, to reducing L1 cache dynamic energy while maintaining high performance. The techniques predict the matching way and probe only the predicted way and not all the ways, achieving energy savings. While these techniques were originally proposed to improve set-associative cache access times, this is the first paper to apply them to reducing cache energy.

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2005

In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/writ... more In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.

In this paper we propose a novel integrated circuit and architectural level technique to reduce l... more In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (transistor threshold voltage) process. We utilize the concept of Gated-Ground [5] (NMOS transistor inserted between Ground line and SRAM cell) to achieve reduction in leakage energy without significantly affecting performance. Experimental results on gated-Ground caches show that data is retained (DRG-Cache) even if the memory are put in the stand-by mode of operation. Data is restored when the gated-Ground transistor is turned on. Turning off the gated-Ground transistor in turn gives large reduction in leakage power. This technique requires no extra circuitry; row decoder itself can be used to control the gated-Ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25µ technology to show the data retention capability and the cell stability of DRG-cache. Our simulation results on 100nm and 70nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache with less than 5% impact on execution time and within 4% increase in area overhead.

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT)... more Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2-D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a Sum of Current Sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.

IEEE Transactions on Very Large Scale Integration Systems, 2003

Abstract In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices... more Abstract In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L eff) of 25nm (oxide thickness= 1.1 nm), 50 nm (oxide thickness= 1.5 nm) and 90 nm (oxide thickness= 2.5 nm) is studied using device ...

In this paper we have developed analytical models to estimate the mean and the standard deviation... more In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.

Proceedings of The IEEE, 2003

coming a significant contributor to power dissipation of CMOS circuits as threshold voltage, chan... more coming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Dual threshold technique has been proposed to reduce leak-age power in low voltage and low power ... more Dual threshold technique has been proposed to reduce leak-age power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path s to maintain the performance. Mixed-Vth MVT ...

Reduction in leakage power has become an important concern in low v oltage, low p o w er and high... more Reduction in leakage power has become an important concern in low v oltage, low p o w er and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using lowthreshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been veri ed by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50.

... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borka... more ... Standby Leakage Power Reduction in CMOS K's Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles Hawkins', Kaushik Roy* and Vivek De MicroComputer Research Labs, 'The University of New Mexico, and 'Purdue University Intel Corporation, Hillsboro, OR 97124, USA ...

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1999

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contribu... more Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I D DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

Abstract| Low supply voltage requires the device threshold to be reduced in order to maintain per... more Abstract| Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been veri ed by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuit... more The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low leakage state and insert leakage control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone.

ACM Transactions on Design Automation of Electronic Systems, 1997

IEEE Transactions on Very Large Scale Integration Systems, 1999

Page 1. 16 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 1, MARCH... more Page 1. 16 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 1, MARCH 1999 Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications Liqiong ...

Set-associative caches achieve low miss rates for typical applications but result in significant ... more Set-associative caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-associative caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the matching way is used. The energy spent accessing the other ways is wasted. Eliminating the wasted energy by performing the data lookup sequentially following the tag lookup substantially increases cache access time, and is unacceptable for high-performance L1 caches. In this paper, we apply two previously-proposed techniques, way-prediction and selective direct-mapping, to reducing L1 cache dynamic energy while maintaining high performance. The techniques predict the matching way and probe only the predicted way and not all the ways, achieving energy savings. While these techniques were originally proposed to improve set-associative cache access times, this is the first paper to apply them to reducing cache energy.

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2005

In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/writ... more In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.

In this paper we propose a novel integrated circuit and architectural level technique to reduce l... more In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (transistor threshold voltage) process. We utilize the concept of Gated-Ground [5] (NMOS transistor inserted between Ground line and SRAM cell) to achieve reduction in leakage energy without significantly affecting performance. Experimental results on gated-Ground caches show that data is retained (DRG-Cache) even if the memory are put in the stand-by mode of operation. Data is restored when the gated-Ground transistor is turned on. Turning off the gated-Ground transistor in turn gives large reduction in leakage power. This technique requires no extra circuitry; row decoder itself can be used to control the gated-Ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25µ technology to show the data retention capability and the cell stability of DRG-cache. Our simulation results on 100nm and 70nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache with less than 5% impact on execution time and within 4% increase in area overhead.

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT)... more Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2-D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a Sum of Current Sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.

IEEE Transactions on Very Large Scale Integration Systems, 2003

Abstract In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices... more Abstract In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L eff) of 25nm (oxide thickness= 1.1 nm), 50 nm (oxide thickness= 1.5 nm) and 90 nm (oxide thickness= 2.5 nm) is studied using device ...

In this paper we have developed analytical models to estimate the mean and the standard deviation... more In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.

Proceedings of The IEEE, 2003

coming a significant contributor to power dissipation of CMOS circuits as threshold voltage, chan... more coming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.