Improved Power Reduction and Aging Mitigation Using Gate Replacement and Voltage Scaling Techniques (original) (raw)
Related papers
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
Applicability of power-gating strategies for aging mitigation of CMOS logic paths
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
International Journal of Computer Applications, 2013
Standby Leakage Power Reduction in Digital Circuits
2015
NBTI-aware power gating design
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011
Influence of the Nmos and Pmos Transistor Threshold Voltages on Cmos Circuits Power Dissipation
An Efficient Approach to Low-Leakage Power VLSI Design using Variable Body Biasing
Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, 2012
Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
IJERT-Comparison of Various Leakage Power Reduction Techniques for CMOS Circuit Design
International Journal of Engineering Research and Technology (IJERT), 2013
Analysis of Power Dissipation & Low Power VLSI Chip Design
IJERT-NBTI Aware Power Gating Design Technique: An Overview
International Journal of Engineering Research and Technology (IJERT), 2014
TRANSISTOR GATING: A Technique for Leakage Power Reduction in CMOS Circuits
2012
Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits
SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology, 2022
INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY, 2016
Efficient reduction of leakage power in low power VLSI circuits using Sleepy Keeper Approach
2015
Review of Leakage Power Reduction in CMOS Circuits Cite This Article
Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power
International Journal of Electrical and Computer Engineering (IJECE)
International Journal of Electrical and Computer Engineering (IJECE), 2017
Design and Realization of CMOS Circuits Using Dual Integrated Technique to Reduce Power Dissipation
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09, 2009
Review of Leakage Power Reduction in CMOS Circuits
American Journal of Electrical and Electronic Engineering, 2014
Microelectronics Journal, 2017
Reduction of Power Dissipation in Logic Circuits
International Journal of Computer Applications, 2011
Standby Leakage Power Reduction Techniques in Deep Sub-Micron CMOS VLSI Circuits
Ijca Proceedings on International Conference on Communication Technology, 2013
WARSE The World Academy of Research in Science and Engineering
Leakage Power Reduction for Logic CircuitsUsing Variable Body Biasing Technique
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy, 2013
AVTS Approach To Digital CMOS Circuits For Diminishing Complete Power Expenditure
An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing
waset.org, 2012