Computer Algorithms Research Papers - Academia.edu (original) (raw)
Genetic algorithms have been extensively used and studied in computer science, yet there is no generally accepted methodology for exploring which parameters significantly affect performance, whether there is any interaction between... more
Genetic algorithms have been extensively used and studied in computer science, yet there is no generally accepted methodology for exploring which parameters significantly affect performance, whether there is any interaction between parameters, and how performance varies with respect to changes in parameters. This paper presents a rigorous yet practical statistical methodology for the exploratory study of genetic and other adaptive algorithms. This methodology addresses the issues of experimental design, blocking, power calculations, and response curve analysis. It details how statistical analysis may assist the investigator along the exploratory pathway. As a demonstration of our methodology, we describe case studies using four well-known test functions. We find that the effect upon performance of crossover is predominantly linear, while the effect of mutation is predominantly quadratic. Higher order effects are noted but contribute less to overall behavior. In the case of crossover, both positive and negative gradients are found suggesting the use of a maximum crossover rate for some problems and its exclusion for others. For mutation, optimal rates appear higher compared with earlier recommendations in the literature, while supporting more recent work. The significance of interaction and the best values for crossover and mutation are problem specific.
Materialized views (MVs) and indexes both significantly speed query processing in database systems, but consume disk space and need to be maintained when updates occur. Choosing the best set of MVs and indexes to create depends upon the... more
Materialized views (MVs) and indexes both significantly speed query processing in database systems, but consume disk space and need to be maintained when updates occur. Choosing the best set of MVs and indexes to create depends upon the workload, the database, and many other factors, which makes the decision intractable for humans and computationally challenging for computer algorithms. Even heuristic-based algorithms can be impractical in real systems. In this paper, we present an advanced tool that uses the query optimizer itself to both suggest and evaluate candidate MVs and indexes, and a simple, practical, and effective algorithm for rapidly finding good solutions even for large workloads. The algorithm trades off the cost for updates and storing each MV or index against its benefit to queries in the workload. The tool autonomically captures the workload, database, and system information, optionally permits sampling of candidate MVs to better estimate their size, and exploits multi-query optimization to construct candidate MVs that will benefit many queries, over which their maintenance cost can then be amortized cost-effectively. We describe the design of the system and present initial experiments that confirm the quality of its results on a database and workload drawn from a real customer database.
Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern... more
Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.
- by Mariusz Rawski and +2
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- Field-Programmable Gate Arrays, Computer Software, Rom, FPGAs
Algorithm visualization software graphically illustrates how computer algorithms work. Past experiments designed to substantiate the software's pedagogical value have yielded mixed results. A review of these studies suggests that the more... more
Algorithm visualization software graphically illustrates how computer algorithms work. Past experiments designed to substantiate the software's pedagogical value have yielded mixed results. A review of these studies suggests that the more actively involved learners are in the visualization process, the better they perform. Given this trend, and inspired by ethnographic fieldwork we conducted in an undergraduate algorithms course, we hypothesize that students who use simple art supplies to construct their own visualizations will learn an algorithm better than students who interact with computer-based visualizations constructed by an expert. We conducted an experiment to test this hypothesis, and found no significant differences between the two pedagogical approaches. Thus, students who use "low tech" materials to construct their own visualizations may learn algorithms just as well as students who study conventional "high tech" visualizations constructed by an expert. This result motivates a markedly different kind of algorithm visualization software: one that enables learners to construct their own "low tech" visualizations.
Periocular biometrics is the recognition of individuals based on the appearance of the region around the eye. Periocular recognition may be useful in applications where it is difficult to obtain a clear picture of an iris for iris... more
Periocular biometrics is the recognition of individuals based on the appearance of the region around the eye. Periocular recognition may be useful in applications where it is difficult to obtain a clear picture of an iris for iris biometrics, or a complete picture of a face for face biometrics. Previous periocular research has used either visible-light (VL) or near-infrared (NIR) light images, but no prior research has directly compared the two illuminations using images with similar resolution. We conducted an experiment in which volunteers were asked to compare pairs of periocular images. Some pairs showed images taken in VL, and some showed images taken in NIR light. Participants labeled each pair as belonging to the same person or to different people. Untrained participants with limited viewing times correctly classified VL image pairs with 88% accuracy, and NIR image pairs with 79% accuracy. For comparison, we presented pairs of iris images from the same subjects. In addition, we investigated differences between performance on light and dark eyes and relative helpfulness of various features in the periocular region under different illuminations. We calculated performance of three computer algorithms on the periocular images. Performance for humans and computers was similar.
This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize the power consumption with resources operating at multiple voltages. The input to both schemes is an unscheduled data flow graph (DFG), and... more
This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize the power consumption with resources operating at multiple voltages. The input to both schemes is an unscheduled data flow graph (DFG), and the timing or the resource constraints. In the paper, partitioning is considered with scheduling in the proposed algorithms as multiple voltage design can lead to an increase in interconnection complexity at layout level. That is, in the proposed algorithms power consumption is first reduced by the scheduling step, and then the partitioning step takes over to decrease the interconnection complexity. Both time-constrained and resource-constrained algorithms have time complexity of O(n 2 ), where n is the number of nodes in the DFG. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve the power reduction under timing constraints and resource constraints by an average of 46.5 and 20%, respectively.
| Let G(k) and H(n) be respectively a kdimensional and an n-dimensional graph. Packing is a technique by which p k many copies of each G(k), k min k k max , are embedded into H(n). Packings can use H(n) eciently by assigning independent... more
| Let G(k) and H(n) be respectively a kdimensional and an n-dimensional graph. Packing is a technique by which p k many copies of each G(k), k min k k max , are embedded into H(n). Packings can use H(n) eciently by assigning independent tasks to the embedded copies of G(k), and are a useful foundation from which node allocation and task migration strategies can be built. Copies of G(k), packed into H(n) with dilation d base , can be combined to produce a variable-dilation embedding of G(k +`) into H(n). Such an embedding has dilation d i along dimension i of G(k +`), where d i = d base for i k, and d i > d base for k < i k +`. The average dilation of the embedding is d avr = 1 k+`P k+ì =1 d i , and can often be made close to d base .
A fast and accurate algorithm for determining inductionmotor transient behavior is presented. The fast components of the stator transients are decoupled from the machine flux linkage equations by a linear transformation. The resulting... more
A fast and accurate algorithm for determining inductionmotor transient behavior is presented. The fast components of the stator transients are decoupled from the machine flux linkage equations by a linear transformation. The resulting differential equations are then solved by using recursive algebraic equations, which require remarkably less computational efforts than existing methods. An example shows that the proposed method is very accurate and yet uses less than 40 percent of the CPU time required by the exact model. The method may be useful in studies that involve simultaneous responses of many machines, such as power system stability studies, where optimal computational efficiency is desirable.
The design description for an integrated circuit may be described in terms of three domains, namely: (1) behavioral domain, (2) structural domain and (3) physical domain. These domains may be hierarchically divided into several levels of... more
The design description for an integrated circuit may be described in terms of three domains, namely: (1) behavioral domain, (2) structural domain and (3) physical domain. These domains may be hierarchically divided into several levels of abstraction. Classically, these level of abstraction are (1) Architectural or Functional level, (2) Register-transfer level, (3) Logic level and (4) Circuit level. Some of the design problems associated with VLSI circuit design are area, speed, reliability and power consumption. With the development of portable devices, power consumption has become a dominant design consideration in the modern VLSI design area. In each of these domains there are a number of design challenges to reduce power. For instance, at the behavioral level, the freedom to choose multiple voltages and frequencies to minimize power to meet the given hard time constraints is considered as an active field of research to minimize power. Various past researches have showed that higher the level of abstraction, better the ability to address the problems associated with the design. Therefore this work proposes an algorithm that allocates both voltage and frequency simultaneously to the operations of the directed flow graph to optimize power given the time constraints. The resources required for multiple voltage-frequency scheduling is derived using the classical force directed scheduling algorithm. This algorithm has been implemented and tested on High-Level synthesis benchmarks for both non-pipelined and pipeline instances.
| The star-connected cycles (SCC) graph was recently proposed as an alternative to the cubeconnected cycles (CCC) graph, using a star graph to connect cycles of nodes rather than a hypercube. This paper presents an analysis of... more
| The star-connected cycles (SCC) graph was recently proposed as an alternative to the cubeconnected cycles (CCC) graph, using a star graph to connect cycles of nodes rather than a hypercube. This paper presents an analysis of broadcasting algorithms for SIMD and MIMD SCCs, covering both one-port and multiple-port versions. We show that O(n log n) one-port broadcasting algorithms that have been proposed for the n-star cannot be e ciently extended to the case of the n-SCC graph. However, a simple but rather ine cient algorithm requiring O(n 2 ) steps in the n-star graph can run in O(n) time in the n-SCC if a proper combination of parallelism and transmission rates in the links connecting the nodes is selected. The result is that broadcasting in the n-SCC can be accomplished e ciently, requiring a running time better than or equal to that of an n-star containing (n ? 1) times fewer nodes.
We have developed a transfer matrix algorithm for the enumeration of compact self-avoiding walks on rectangular strips of the square lattice. The algorithm is easily adapted to other shapes or generalized to problems such as interacting... more
We have developed a transfer matrix algorithm for the enumeration of compact self-avoiding walks on rectangular strips of the square lattice. The algorithm is easily adapted to other shapes or generalized to problems such as interacting walks. These models are relevant in the study of globular proteins.
Title: Jitter and Wander Reduction for a SONETIDS3 Desynchronizer using Predictive Fuzzy Control Excessive high-frequency jitter or low-frequency wander can create problems within synchronous transmission systems and must be kept within... more
Title: Jitter and Wander Reduction for a SONETIDS3 Desynchronizer using Predictive Fuzzy Control Excessive high-frequency jitter or low-frequency wander can create problems within synchronous transmission systems and must be kept within limits to ensure reliable network operation. The emerging Synchronous Optical NETwork (SONET) introduces additional challenges for jitter and wander attenuation equipment (called desynchronizers) when used to carry payloads from the existing Plesiochronous Digital Hierarchy (PDH), such as the DS3. The difficulty is primarily due to the large phase transients resulting from the pointer-based justification technique employed by SONET (called Pointer Justification Events or PJEs). While some previous desynchronization techniques consider the buffer level in their control actions, none has explicitly considered wander generation. Instead, compliance with jitter, wander, and buffer-size constraints have typically been met implicitly-through testing and tuning of the Phase Locked Loop (PLL) controller. We investigated a fuzzy/rule-based solution to this desynchronization/constraintsatisfaction problem. But rather than mapping the input state to an action, as is done in standard fuzzy logic, our controller maps a state and a candidate action to a desired result. In other words, this control paradigm employs prediction to evaluate which of a set of candidate actions would result in the "best" predicted performance. Before the faithful friend. She has never doubted that I could finish whatever I put my mind to. I would also like to thank my mother and father for being a persistent source of encouragement and support. I could not have asked for a better family. A big thanks to my advisor Dr. Y.c. Jenq who was excellent to work with. He made sure that I always had the tools necessary to complete each task and it is doubtful that 1 would have finished when I did were it not for the guidance and insights he provided each week. I'd like to acknowledge NEC America for funding this research. Specifically, Mr. Brian Reilly and Mr. Steven Gorshe contributed by discussing ideas, offering assistance with T 1 standards and documents, and providing their industrial experience. It is doubtful that these results would have been achieved without the freedom they gave me to explore and create. The other members of my committee deserve acknowledgement as well: Dr. Driscoll for his logical/sequential analysis of my research and for telling me early on that to earn a Ph.D. I would "have to really, really want it" (I decided that I did); Dr. Hall for sharing his many practical experiences and insights, time spent on numerous occasions to train me as a teacher, and his convincing arguments for completing my education sooner rather than later; Dr. Lendaris for his thorough and frank evaluation of my ideas and writings, and for a genuinely friendly, personal interest in me and my family; Dr. Turcic for his encouragement and flexibility, and for bringing up the question of simulation validity early on so that I had time to consider this critical component. I would like to acknowledge the EE staff and several of my many supportive friends: Tim