Implementation of Full Adder using NAND Gates (original) (raw)

Last Updated : 20 Jan, 2026

In Digital Logic Circuit, Full Adder is a Digital Logic Circuit that can add three inputs and give two outputs. The three inputs such as A, B, and input carry as Cin. The output carry is represented as Cout and the normal output is represented as S, Sum. The Cout is also known as the majority 1’s detector, whose output goes high when more than one input is high.

In Digital Logic Circuits, Full Adders are implemented using digital logic gates such as OR gate, AND gate, NOT gate, NAND gates, NOR gates, etc. In this article, we will explore Full Adders, and NAND Gates and execute the ImplementationofFull Adder using NAND Gates.

**What is a Full Adder?

Full Adder is a Digital Logic Circuits that can add three inputs and give two outputs i.e. three inputs such as A, B, and input carry as Cin and gives a sum output and carry output i.e. two outputs. A Full Adder Circuit performs as the brain of the most of Digital Logic Circuits that execute addition or subtraction.

A Full Adder require the use of nine NAND gates. The Arithmetic Logic Unit, ALU uses Full Adders. In a computer, Full Adders are utilized by the ALU to produce memory addresses and relocate the Program Counter to the next instruction.

Now, Here we will understand Full Adder by Block Diagram of Full Adder where we will discuss and explain it by using :

Block Diagram of Full Adder

The Block Diagram of Full Adder is shown below

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**Logical Expression of a Full Adder

Given below is the Expression for Full Adder which includes Sum and Carry

Sum=A ⊕ B ⊕ Cin

Cout= AB + ACin + BCin

Where, A, B, Cin are the Inputs of the Full Adder

**Applications of Full Adder

What is a NAND Gate?

A NAND gate is one of the type of Universal Gates in which the two basic logic gates are combined as the NAND gate can implement any Boolean function without the use of basic gates and also find the results of logical inputs without the use of any other logic gates.

The NAND gate or “Not AND” gate is the combination of two basic logic gates are connected in series i.e. the AND gate and the NOT gate. NAND gate output is high when one of the two inputs is high or if both inputs are low. It means the output is always high and when both the inputs are high then the output is low.

Symbol of a NAND Gate

Given Below is the Symbol For NAND Gate

**Logical expression of a NAND Gate

In the expression, Two inputs are represented as A and B and the Output is X, then the expression is –

X = (A.B)’

2 Input NAND Gate

NAND Gate

**Applications of NAND Gate

Implementation of Full Adder using NAND Gates

Implementation of Full Adder using NAND Gates is realization of Full Adder by using minimum nine NAND Gates during which we will have 2 outputs at the end namely Cout and Sum.

Given Below is the Circuit For Implementation of Full Adder using NAND Gates :

Full Adder Using NAND Gate

Full Adder Using NAND Gates

**Logical Expression for Full Adder using NAND Gate

Using Half Adder Equation of Sum, we get

Sum=A\overline{B}+\overline{A}B

=AA\overline{B}+\overline{A}B+A\overline{A}+B\overline{B} Because A\overline{A}=0

=A\overline{B}+A\overline{A}+\overline{A}B+B\overline{B} Because B\overline{B}=0

=A(\overline{B}+\overline{A})+B(\overline{A}+\overline{B})

=A(\overline{AB})+B(\overline{AB}) By De-Morgan's Theorem

=\overline{\overline{A(\overline{AB})+B(\overline{AB})}} Because \overline{\overline{A}}=A

Sum=\overline{\overline{A(\overline{AB})}.\overline{B(\overline{AB})}} By De-Morgan's Theorem

Using Half Adder Equation of Carry, we get

Carry=A.B

=\overline{\overline{A.B}} Because \overline{\overline{A}}=A

Sum=A\overline{B}+\overline{A}B

=\overline{\overline{A(\overline{AB})}.\overline{B(\overline{AB})}} Equation-1

For Full Adder Equation of Sum, we realize

Sum=A⊕B⊕Cin Put A⊕B=x

=x⊕Cin

=\overline{\overline{x(\overline{xCin})}.\overline{Cin(\overline{xCin})}} Comparing x⊕Cin with A⊕B, Using Equation 1, we get

Sum={(\overline{A\overline{B}+\overline{A}B).(\overline{(A\overline{B}+\overline{A}B).Cin)}.\overline{Cin(\overline{(A\overline{B}+\overline{A}B).Cin)}}}

Carry=AB+(A\overline{B}+\overline{A}B).Cin

=\overline{\overline{AB+(A\overline{B}+\overline{A}B).Cin}}

=\overline{\overline{AB}.\overline{((A\overline{B}+\overline{A}B).Cin)}}

Steps To Implement the Full Adder using NAND Gate

Applications of Implementation of a Full Adder using NAND Gates

Given Below are the Applications of Implementation of a Full Adder using NAND Gates