AArch64CollectLOH.cpp File Reference (original) (raw)

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Functions
	STATISTIC (NumADRPSimpleCandidate, "Number of simplifiable ADRP dominate by another")
	STATISTIC (NumADDToSTR, "Number of simplifiable STR reachable by ADD")
	STATISTIC (NumLDRToSTR, "Number of simplifiable STR reachable by LDR")
	STATISTIC (NumADDToLDR, "Number of simplifiable LDR reachable by ADD")
	STATISTIC (NumLDRToLDR, "Number of simplifiable LDR reachable by LDR")
	STATISTIC (NumADRPToLDR, "Number of simplifiable LDR reachable by ADRP")
	STATISTIC (NumADRSimpleCandidate, "Number of simplifiable ADRP + ADD")
	INITIALIZE_PASS (AArch64CollectLOH, "aarch64-collect-loh", AARCH64_COLLECT_LOH_NAME, false, false) static bool canAddBePartOfLOH(const MachineInstr &MI)
static bool	canDefBePartOfLOH (const MachineInstr &MI)
	Answer the following question: Can Def be one of the definition involved in a part of a LOH?
static bool	isCandidateStore (const MachineInstr &MI, const MachineOperand &MO)
	Check whether the given instruction can the end of a LOH chain involving a store.
static bool	isCandidateLoad (const MachineInstr &MI)
	Check whether the given instruction can be the end of a LOH chain involving a load.
static bool	supportLoadFromLiteral (const MachineInstr &MI)
	Check whether the given instruction can load a literal.
static bool	areInstructionsConsecutive (const MachineInstr First, const MachineInstr Second)
	Returns true if there are no non-debug instructions between First and Second.
static int	mapRegToGPRIndex (MCRegister Reg)
	Map register number to index from 0-30.
static void	handleUse (const MachineInstr &MI, const MachineOperand &MO, LOHInfo &Info)
	Update state Info given MI uses the tracked register.
static void	handleClobber (LOHInfo &Info)
	Update state Info given the tracked register is clobbered.
static bool	handleMiddleInst (const MachineInstr &MI, LOHInfo &DefInfo, LOHInfo &OpInfo)
	Update state Info given that MI is possibly the middle instruction of an LOH involving 3 instructions.
static void	handleADRP (const MachineInstr &MI, AArch64FunctionInfo &AFI, LOHInfo &Info, LOHInfo *LOHInfos)
	Update state when seeing and ADRP instruction.
static void	handleRegMaskClobber (const uint32_t RegMask, MCPhysReg Reg, LOHInfo LOHInfos)
static void	handleNormalInst (const MachineInstr &MI, LOHInfo *LOHInfos)

◆ AARCH64_COLLECT_LOH_NAME

◆ DEBUG_TYPE

#define DEBUG_TYPE "aarch64-collect-loh"

◆ areInstructionsConsecutive()

◆ canDefBePartOfLOH()

◆ handleADRP()

Update state when seeing and ADRP instruction.

Definition at line 391 of file AArch64CollectLOH.cpp.

References llvm::AArch64FunctionInfo::addLOHDirective(), areInstructionsConsecutive(), llvm::dbgs(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), handleClobber(), Info, LLVM_DEBUG, llvm_unreachable, mapRegToGPRIndex(), llvm::MCLOH_AdrpAdd, llvm::MCLOH_AdrpAddLdr, llvm::MCLOH_AdrpAddStr, llvm::MCLOH_AdrpAdrp, llvm::MCLOH_AdrpLdr, llvm::MCLOH_AdrpLdrGot, llvm::MCLOH_AdrpLdrGotLdr, llvm::MCLOH_AdrpLdrGotStr, MI, LOHInfo::MultiUsers, LOHInfo::OneUser, OpIdx, and supportLoadFromLiteral().

◆ handleClobber()

void handleClobber ( LOHInfo & Info)	static

◆ handleMiddleInst()

Update state Info given that MI is possibly the middle instruction of an LOH involving 3 instructions.

Definition at line 343 of file AArch64CollectLOH.cpp.

References assert(), handleClobber(), LOHInfo::IsCandidate, LOHInfo::LastADRP, llvm::MCLOH_AdrpAddLdr, llvm::MCLOH_AdrpAddStr, llvm::MCLOH_AdrpLdr, llvm::MCLOH_AdrpLdrGotLdr, llvm::MCLOH_AdrpLdrGotStr, MI, llvm::AArch64II::MO_GOT, and LOHInfo::OneUser.

◆ handleNormalInst()

◆ handleRegMaskClobber()

◆ handleUse()

Update state Info given MI uses the tracked register.

Definition at line 298 of file AArch64CollectLOH.cpp.

References const, handleUse(), if(), Info, isCandidateLoad(), isCandidateStore(), llvm::MCLOH_AdrpAddStr, llvm::MCLOH_AdrpLdr, MI, and llvm::AArch64II::MO_GOT.

Referenced by handleNormalInst(), and handleUse().

◆ INITIALIZE_PASS()

INITIALIZE_PASS	(	AArch64CollectLOH	,
"aarch64-collect-loh"	,
AARCH64_COLLECT_LOH_NAME	,
false	,
false	) const &

◆ isCandidateLoad()

◆ isCandidateStore()

◆ mapRegToGPRIndex()

◆ STATISTIC() [1/7]

STATISTIC	(	NumADDToLDR	,
"Number of simplifiable LDR reachable by ADD"	)

◆ STATISTIC() [2/7]

STATISTIC	(	NumADDToSTR	,
"Number of simplifiable STR reachable by ADD"	)

◆ STATISTIC() [3/7]

STATISTIC	(	NumADRPSimpleCandidate	,
"Number of simplifiable ADRP dominate by another"	)

◆ STATISTIC() [4/7]

STATISTIC	(	NumADRPToLDR	,
"Number of simplifiable LDR reachable by ADRP"	)

◆ STATISTIC() [5/7]

STATISTIC	(	NumADRSimpleCandidate	,
"Number of simplifiable ADRP + ADD"	)

◆ STATISTIC() [6/7]

STATISTIC	(	NumLDRToLDR	,
"Number of simplifiable LDR reachable by LDR"	)

◆ STATISTIC() [7/7]

STATISTIC	(	NumLDRToSTR	,
"Number of simplifiable STR reachable by LDR"	)