AMDGPUAsmBackend.cpp Source File (original) (raw)

26using namespace llvm;

29namespace {

32public:

33 AMDGPUAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::little) {}

35 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,

36 uint8_t *Data, uint64_t Value, bool IsResolved) override;

37 bool fixupNeedsRelaxation(const MCFixup &Fixup,

38 uint64_t Value) const override;

40 void relaxInstruction(MCInst &Inst,

41 const MCSubtargetInfo &STI) const override;

44 const MCSubtargetInfo &STI) const override;

46 unsigned getMinimumNopSize() const override;

47 bool writeNopData(raw_ostream &OS, uint64_t Count,

48 const MCSubtargetInfo *STI) const override;

50 std::optional getFixupKind(StringRef Name) const override;

51 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override;

52};

54}

56void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,

58 MCInst Res;

62 Inst = std::move(Res);

63}

65bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,

66 uint64_t Value) const {

70 return (((int64_t(Value)/4)-1) == 0x3f);

71}

73bool AMDGPUAsmBackend::mayNeedRelaxation(unsigned Opcode,

75 const MCSubtargetInfo &STI) const {

76 if (!STI.hasFeature(AMDGPU::FeatureOffset3fBug))

77 return false;

80 return true;

82 return false;

83}

86 switch (Kind) {

88 return 2;

91 return 1;

94 return 2;

97 return 4;

100 return 8;

101 default:

103 }

104}

105

108 int64_t SignedValue = static_cast<int64_t>(Value);

109

110 switch (Fixup.getKind()) {

112 int64_t BrImm = (SignedValue - 4) / 4;

113

115 Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");

116

117 return BrImm;

118 }

125 default:

127 }

128}

129

130void AMDGPUAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,

131 const MCValue &Target, uint8_t *Data,

132 uint64_t Value, bool IsResolved) {

133 if (Target.getSpecifier())

134 IsResolved = false;

135 maybeAddReloc(F, Fixup, Target, Value, IsResolved);

137 return;

138

141 return;

142

143 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());

144

145

147

149 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&

150 "Invalid fixup offset!");

151

152

153

154 for (unsigned i = 0; i != NumBytes; ++i)

155 Data[i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);

156}

157

158std::optional

159AMDGPUAsmBackend::getFixupKind(StringRef Name) const {

160 auto Type = StringSwitch(Name)

161#define ELF_RELOC(Name, Value) .Case(#Name, Value)

162#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"

163#undef ELF_RELOC

164 .Case("BFD_RELOC_NONE", ELF::R_AMDGPU_NONE)

165 .Case("BFD_RELOC_32", ELF::R_AMDGPU_ABS32)

166 .Case("BFD_RELOC_64", ELF::R_AMDGPU_ABS64)

167 .Default(-1u);

168 if (Type != -1u)

170 return std::nullopt;

171}

172

173MCFixupKindInfo AMDGPUAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {

175

176 {"fixup_si_sopp_br", 0, 16, 0},

177 };

178

180 return {};

181

184

186 "Invalid kind!");

188}

189

190unsigned AMDGPUAsmBackend::getMinimumNopSize() const {

191 return 4;

192}

193

194bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,

195 const MCSubtargetInfo *STI) const {

196

197

198

199

200 unsigned MinInstAlignment = getContext().getAsmInfo()->getMinInstAlignment();

202

203

204 Count /= MinInstAlignment;

205

206

207

208 const uint32_t Encoded_S_NOP_0 = 0xbf800000;

209

210 assert(MinInstAlignment == sizeof(Encoded_S_NOP_0));

211 for (uint64_t I = 0; I != Count; ++I)

213

214 return true;

215}

216

217

218

219

220

221namespace {

222

223class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {

224 bool Is64Bit;

225 bool HasRelocationAddend;

227

228public:

229 ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)

230 : AMDGPUAsmBackend(T), Is64Bit(TT.isAMDGCN()),

231 HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {

232 switch (TT.getOS()) {

233 case Triple::AMDHSA:

234 OSABI = ELF::ELFOSABI_AMDGPU_HSA;

235 break;

236 case Triple::AMDPAL:

237 OSABI = ELF::ELFOSABI_AMDGPU_PAL;

238 break;

239 case Triple::Mesa3D:

240 OSABI = ELF::ELFOSABI_AMDGPU_MESA3D;

241 break;

242 default:

243 break;

244 }

245 }

246

247 std::unique_ptr

248 createObjectTargetWriter() const override {

250 }

251};

252

253}

254

unsigned const MachineRegisterInfo * MRI

static unsigned getFixupKindNumBytes(unsigned Kind)

The number of bytes the fixup may change.

static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Provides AMDGPU specific target descriptions.

Analysis containing CSE Info

PowerPC TLS Dynamic Call Fixup

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

Generic interface to target specific assembler backends.

virtual MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const

Get information on a fixup kind.

Context object for machine code objects.

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

Target - Wrapper for Target specific information.

LLVM Value Representation.

raw_ostream & write_zeros(unsigned NumZeros)

write_zeros - Insert 'NumZeros' nulls.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ fixup_si_sopp_br

16-bit PC relative fixup for SOPP branch instructions.

LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)

VE::Fixups getFixupKind(uint8_t S)

Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)

Apply fixup expression for edge to block content.

bool isRelocation(MCFixupKind FixupKind)

Context & getContext() const

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Definition AMDGPUAsmBackend.cpp:255

std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

FunctionAddr VTableAddr Count

@ FK_SecRel_2

A two-byte section relative fixup.

@ FirstLiteralRelocationKind

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_SecRel_8

A eight-byte section relative fixup.

@ FK_SecRel_4

A four-byte section relative fixup.

@ FK_SecRel_1

A one-byte section relative fixup.

@ FK_Data_2

A two-byte fixup.

FunctionAddr VTableAddr uintptr_t uintptr_t Data

ArrayRef(const T &OneElt) -> ArrayRef< T >