LLVM: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Source File (original) (raw)
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21#include "llvm/IR/IntrinsicsAMDGPU.h"
22#include "llvm/IR/IntrinsicsR600.h"
29#include
30
31#define GET_INSTRINFO_NAMED_OPS
32#define GET_INSTRMAP_INFO
33#include "AMDGPUGenInstrInfo.inc"
34
38 llvm:🆑:desc("Set default AMDHSA Code Object Version (module flag "
39 "or asm directive still take priority if present)"));
40
41namespace {
42
43
44unsigned getBitMask(unsigned Shift, unsigned Width) {
45 return ((1 << Width) - 1) << Shift;
46}
47
48
49
50
51unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
52 unsigned Mask = getBitMask(Shift, Width);
53 return ((Src << Shift) & Mask) | (Dst & ~Mask);
54}
55
56
57
58
59unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
60 return (Src & getBitMask(Shift, Width)) >> Shift;
61}
62
63
64unsigned getVmcntBitShiftLo(unsigned VersionMajor) {
66}
67
68
69unsigned getVmcntBitWidthLo(unsigned VersionMajor) {
71}
72
73
74unsigned getExpcntBitShift(unsigned VersionMajor) {
76}
77
78
79unsigned getExpcntBitWidth(unsigned VersionMajor) { return 3; }
80
81
82unsigned getLgkmcntBitShift(unsigned VersionMajor) {
84}
85
86
87unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
89}
90
91
92unsigned getVmcntBitShiftHi(unsigned VersionMajor) { return 14; }
93
94
95unsigned getVmcntBitWidthHi(unsigned VersionMajor) {
96 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
97}
98
99
100unsigned getLoadcntBitWidth(unsigned VersionMajor) {
102}
103
104
105unsigned getSamplecntBitWidth(unsigned VersionMajor) {
107}
108
109
110unsigned getBvhcntBitWidth(unsigned VersionMajor) {
112}
113
114
115unsigned getDscntBitWidth(unsigned VersionMajor) {
117}
118
119
120unsigned getDscntBitShift(unsigned VersionMajor) { return 0; }
121
122
123unsigned getStorecntBitWidth(unsigned VersionMajor) {
125}
126
127
128unsigned getKmcntBitWidth(unsigned VersionMajor) {
130}
131
132
133unsigned getLoadcntStorecntBitShift(unsigned VersionMajor) {
135}
136
137
138inline unsigned getVmVsrcBitWidth() { return 3; }
139
140
141inline unsigned getVmVsrcBitShift() { return 2; }
142
143
144inline unsigned getVaVdstBitWidth() { return 4; }
145
146
147inline unsigned getVaVdstBitShift() { return 12; }
148
149
150inline unsigned getSaSdstBitWidth() { return 1; }
151
152
153inline unsigned getSaSdstBitShift() { return 0; }
154
155}
156
157namespace llvm {
158
159namespace AMDGPU {
160
161
162
165}
166
167
170}
171
173 if (auto *Ver = mdconst::extract_or_null(
174 M.getModuleFlag("amdhsa_code_object_version"))) {
175 return (unsigned)Ver->getZExtValue() / 100;
176 }
177
179}
180
183}
184
186 switch (ABIVersion) {
188 return 4;
190 return 5;
192 return 6;
193 default:
195 }
196}
197
200 return 0;
201
202 switch (CodeObjectVersion) {
203 case 4:
205 case 5:
207 case 6:
209 default:
211 Twine(CodeObjectVersion));
212 }
213}
214
216 switch (CodeObjectVersion) {
218 return 48;
221 default:
223 }
224}
225
226
227
228
230 switch (CodeObjectVersion) {
232 return 24;
235 default:
237 }
238}
239
241 switch (CodeObjectVersion) {
243 return 32;
246 default:
248 }
249}
250
252 switch (CodeObjectVersion) {
254 return 40;
257 default:
259 }
260}
261
262#define GET_MIMGBaseOpcodesTable_IMPL
263#define GET_MIMGDimInfoTable_IMPL
264#define GET_MIMGInfoTable_IMPL
265#define GET_MIMGLZMappingTable_IMPL
266#define GET_MIMGMIPMappingTable_IMPL
267#define GET_MIMGBiasMappingTable_IMPL
268#define GET_MIMGOffsetMappingTable_IMPL
269#define GET_MIMGG16MappingTable_IMPL
270#define GET_MAIInstInfoTable_IMPL
271#include "AMDGPUGenSearchableTables.inc"
272
274 unsigned VDataDwords, unsigned VAddrDwords) {
275 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
276 VDataDwords, VAddrDwords);
277 return Info ? Info->Opcode : -1;
278}
279
283}
284
290 return NewInfo ? NewInfo->Opcode : -1;
291}
292
295 bool IsG16Supported) {
296 unsigned AddrWords = BaseOpcode->NumExtraArgs;
299 if (IsA16)
300 AddrWords += divideCeil(AddrComponents, 2);
301 else
302 AddrWords += AddrComponents;
303
304
305
306
307
308
310 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16)
311
312
313
314 AddrWords += alignTo<2>(Dim->NumGradients / 2);
315 else
317 }
318 return AddrWords;
319}
320
330};
331
339};
340
344};
345
349};
350
353};
354
357};
358
361};
362
367};
368
374};
375
379};
380
381#define GET_FP4FP8DstByteSelTable_DECL
382#define GET_FP4FP8DstByteSelTable_IMPL
383
387};
388
393};
394
395#define GET_MTBUFInfoTable_DECL
396#define GET_MTBUFInfoTable_IMPL
397#define GET_MUBUFInfoTable_DECL
398#define GET_MUBUFInfoTable_IMPL
399#define GET_SMInfoTable_DECL
400#define GET_SMInfoTable_IMPL
401#define GET_VOP1InfoTable_DECL
402#define GET_VOP1InfoTable_IMPL
403#define GET_VOP2InfoTable_DECL
404#define GET_VOP2InfoTable_IMPL
405#define GET_VOP3InfoTable_DECL
406#define GET_VOP3InfoTable_IMPL
407#define GET_VOPC64DPPTable_DECL
408#define GET_VOPC64DPPTable_IMPL
409#define GET_VOPC64DPP8Table_DECL
410#define GET_VOPC64DPP8Table_IMPL
411#define GET_VOPCAsmOnlyInfoTable_DECL
412#define GET_VOPCAsmOnlyInfoTable_IMPL
413#define GET_VOP3CAsmOnlyInfoTable_DECL
414#define GET_VOP3CAsmOnlyInfoTable_IMPL
415#define GET_VOPDComponentTable_DECL
416#define GET_VOPDComponentTable_IMPL
417#define GET_VOPDPairs_DECL
418#define GET_VOPDPairs_IMPL
419#define GET_VOPTrue16Table_DECL
420#define GET_VOPTrue16Table_IMPL
421#define GET_WMMAOpcode2AddrMappingTable_DECL
422#define GET_WMMAOpcode2AddrMappingTable_IMPL
423#define GET_WMMAOpcode3AddrMappingTable_DECL
424#define GET_WMMAOpcode3AddrMappingTable_IMPL
425#define GET_getMFMA_F8F6F4_WithSize_DECL
426#define GET_getMFMA_F8F6F4_WithSize_IMPL
427#define GET_isMFMA_F8F6F4Table_IMPL
428#define GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL
429
430#include "AMDGPUGenSearchableTables.inc"
431
433 const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc);
434 return Info ? Info->BaseOpcode : -1;
435}
436
438 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
439 return Info ? Info->Opcode : -1;
440}
441
443 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
444 return Info ? Info->elements : 0;
445}
446
448 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
449 return Info ? Info->has_vaddr : false;
450}
451
453 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
454 return Info ? Info->has_srsrc : false;
455}
456
458 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
459 return Info ? Info->has_soffset : false;
460}
461
463 const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
464 return Info ? Info->BaseOpcode : -1;
465}
466
468 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
469 return Info ? Info->Opcode : -1;
470}
471
473 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
474 return Info ? Info->elements : 0;
475}
476
478 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
479 return Info ? Info->has_vaddr : false;
480}
481
483 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
484 return Info ? Info->has_srsrc : false;
485}
486
488 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
489 return Info ? Info->has_soffset : false;
490}
491
493 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
494 return Info ? Info->IsBufferInv : false;
495}
496
498 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
499 return Info ? Info->tfe : false;
500}
501
503 const SMInfo *Info = getSMEMOpcodeHelper(Opc);
504 return Info ? Info->IsBuffer : false;
505}
506
508 const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
509 return Info ? Info->IsSingle : true;
510}
511
513 const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
514 return Info ? Info->IsSingle : true;
515}
516
518 const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
519 return Info ? Info->IsSingle : true;
520}
521
523 return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
524}
525
526bool isVOPCAsmOnly(unsigned Opc) { return isVOPCAsmOnlyOpcodeHelper(Opc); }
527
530 return Info ? Info->is_dgemm : false;
531}
532
535 return Info ? Info->is_gfx940_xdl : false;
536}
537
539 switch (EncodingVal) {
542 return 6;
544 return 4;
547 default:
548 return 8;
549 }
550
552}
553
555 unsigned BLGP,
556 unsigned F8F8Opcode) {
559 return getMFMA_F8F6F4_InstWithNumRegs(SrcANumRegs, SrcBNumRegs, F8F8Opcode);
560}
561
563 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
565 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
567 llvm_unreachable("Subtarget generation does not support VOPD!");
568}
569
573 return {Info->CanBeVOPDX, true};
574 return {false, false};
575}
576
579 return Info ? Info->VOPDOp : ~0u;
580}
581
584}
585
587 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
588 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
589 Opc == AMDGPU::V_MAC_F32_e64_vi ||
590 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
591 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
592 Opc == AMDGPU::V_MAC_F16_e64_vi ||
593 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
594 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
595 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
596 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
597 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
598 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
599 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
600 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
601 Opc == AMDGPU::V_FMAC_F16_fake16_e64_gfx11 ||
602 Opc == AMDGPU::V_FMAC_F16_fake16_e64_gfx12 ||
603 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
604 Opc == AMDGPU::V_DOT2C_F32_BF16_e64_vi ||
605 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
606 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
607 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
608}
609
611 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
612 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
613 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
614 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
615 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
616 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
617 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
618 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
619}
620
622 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
623 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
624 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
625 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
626 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
627 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
628 Opc == AMDGPU::V_CVT_PK_F32_BF8_fake16_e64_gfx12 ||
629 Opc == AMDGPU::V_CVT_PK_F32_FP8_fake16_e64_gfx12 ||
630 Opc == AMDGPU::V_CVT_PK_F32_BF8_t16_e64_gfx12 ||
631 Opc == AMDGPU::V_CVT_PK_F32_FP8_t16_e64_gfx12;
632}
633
635 return Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
636 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
637 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
638 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
639 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
640 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
641 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
642 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
643 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
644 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
645 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
646 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
647 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
648 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
649 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
650 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
651 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
652}
653
656 return Info ? Info->IsTrue16 : false;
657}
658
663 if (Info->HasFP8DstByteSel)
665 if (Info->HasFP4DstByteSel)
667
669}
670
673 return Info ? Info->Opcode3Addr : ~0u;
674}
675
678 return Info ? Info->Opcode2Addr : ~0u;
679}
680
681
682
683
685 return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
686}
687
688int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily) {
690 getVOPDInfoFromComponentOpcodes(OpX, OpY, EncodingFamily);
691 return Info ? Info->Opcode : -1;
692}
693
695 const VOPDInfo *Info = getVOPDOpcodeHelper(VOPDOpcode);
697 const auto *OpX = getVOPDBaseFromComponent(Info->OpX);
698 const auto *OpY = getVOPDBaseFromComponent(Info->OpY);
700 return {OpX->BaseVOP, OpY->BaseVOP};
701}
702
703namespace VOPD {
704
707
712 HasSrc2Acc = TiedIdx != -1;
713
716
718 unsigned CompOprIdx;
719 for (CompOprIdx = Component::SRC1; CompOprIdx < OperandsNum; ++CompOprIdx) {
721 MandatoryLiteralIdx = CompOprIdx;
722 break;
723 }
724 }
725}
726
729
732
736
737
738 return 0;
739}
740
742 std::function<unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc) const {
743
746
747 const unsigned CompOprNum =
749 unsigned CompOprIdx;
750 for (CompOprIdx = 0; CompOprIdx < CompOprNum; ++CompOprIdx) {
752 if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
753 ((OpXRegs[CompOprIdx] & BanksMasks) ==
754 (OpYRegs[CompOprIdx] & BanksMasks)))
755 return CompOprIdx;
756 }
757
758 return {};
759}
760
761
762
763
764
765
766
767
769 unsigned CompIdx,
770 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
772
773 const auto &Comp = CompInfo[CompIdx];
775
776 RegIndices[DST] = GetRegIdx(CompIdx, Comp.getIndexOfDstInMCOperands());
777
778 for (unsigned CompOprIdx : {SRC0, SRC1, SRC2}) {
779 unsigned CompSrcIdx = CompOprIdx - DST_NUM;
781 Comp.hasRegSrcOperand(CompSrcIdx)
782 ? GetRegIdx(CompIdx, Comp.getIndexOfSrcInMCOperands(CompSrcIdx))
783 : 0;
784 }
786}
787
788}
789
792}
793
797 const auto &OpXDesc = InstrInfo->get(OpX);
798 const auto &OpYDesc = InstrInfo->get(OpY);
802}
803
804namespace IsaInfo {
805
813}
814
816
817
818
820 std::optional XnackRequested;
821 std::optional SramEccRequested;
822
823 for (const std::string &Feature : Features.getFeatures()) {
824 if (Feature == "+xnack")
825 XnackRequested = true;
826 else if (Feature == "-xnack")
827 XnackRequested = false;
828 else if (Feature == "+sramecc")
829 SramEccRequested = true;
830 else if (Feature == "-sramecc")
831 SramEccRequested = false;
832 }
833
836
837 if (XnackRequested) {
838 if (XnackSupported) {
839 XnackSetting =
841 } else {
842
843
844 if (*XnackRequested) {
845 errs() << "warning: xnack 'On' was requested for a processor that does "
846 "not support it!\n";
847 } else {
848 errs() << "warning: xnack 'Off' was requested for a processor that "
849 "does not support it!\n";
850 }
851 }
852 }
853
854 if (SramEccRequested) {
855 if (SramEccSupported) {
856 SramEccSetting =
858 } else {
859
860
861
862 if (*SramEccRequested) {
863 errs() << "warning: sramecc 'On' was requested for a processor that "
864 "does not support it!\n";
865 } else {
866 errs() << "warning: sramecc 'Off' was requested for a processor that "
867 "does not support it!\n";
868 }
869 }
870 }
871}
872
875 if (FeatureString.ends_with("-"))
877 if (FeatureString.ends_with("+"))
879
881}
882
885 TargetID.split(TargetIDSplit, ':');
886
887 for (const auto &FeatureString : TargetIDSplit) {
888 if (FeatureString.starts_with("xnack"))
890 if (FeatureString.starts_with("sramecc"))
892 }
893}
894
896 std::string StringRep;
898
901
902 StreamRep << TargetTriple.getArchName() << '-'
903 << TargetTriple.getVendorName() << '-'
904 << TargetTriple.getOSName() << '-'
905 << TargetTriple.getEnvironmentName() << '-';
906
907 std::string Processor;
908
909
910
913 else
916 .str();
917
918 std::string Features;
920
922 Features += ":sramecc-";
924 Features += ":sramecc+";
925
927 Features += ":xnack-";
929 Features += ":xnack+";
930 }
931
932 StreamRep << Processor << Features;
933
934 return StringRep;
935}
936
939 return 16;
941 return 32;
942
943 return 64;
944}
945
948
949
950
951
953 BytesPerCU *= 2;
954
955 return BytesPerCU;
956}
957
959 if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize32768))
960 return 32768;
961 if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize65536))
962 return 65536;
963 if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize163840))
964 return 163840;
965 return 0;
966}
967
969
970
971
973 return 2;
974
975
976 return 4;
977}
978
980 unsigned FlatWorkGroupSize) {
981 assert(FlatWorkGroupSize != 0);
983 return 8;
986 if (N == 1) {
987
988 return MaxWaves;
989 }
990
991 unsigned MaxBarriers = 16;
993 MaxBarriers = 32;
994
995 return std::min(MaxWaves / N, MaxBarriers);
996}
997
999 return 1;
1000}
1001
1003
1005 return 8;
1007 return 10;
1009}
1010
1012 unsigned FlatWorkGroupSize) {
1015}
1016
1018 return 1;
1019}
1020
1022
1023 return 1024;
1024}
1025
1027 unsigned FlatWorkGroupSize) {
1029}
1030
1033 if (Version.Major >= 10)
1036 return 16;
1037 return 8;
1038}
1039
1041 return 8;
1042}
1043
1047 return 800;
1048 return 512;
1049}
1050
1054
1056 if (Version.Major >= 10)
1057 return 106;
1059 return 102;
1060 return 104;
1061}
1062
1064 assert(WavesPerEU != 0);
1065
1067 if (Version.Major >= 10)
1068 return 0;
1069
1071 return 0;
1072
1073 unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
1075 MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
1078}
1079
1081 bool Addressable) {
1082 assert(WavesPerEU != 0);
1083
1086 if (Version.Major >= 10)
1087 return Addressable ? AddressableNumSGPRs : 108;
1088 if (Version.Major >= 8 && !Addressable)
1089 AddressableNumSGPRs = 112;
1092 MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
1094 return std::min(MaxNumSGPRs, AddressableNumSGPRs);
1095}
1096
1098 bool FlatScrUsed, bool XNACKUsed) {
1099 unsigned ExtraSGPRs = 0;
1100 if (VCCUsed)
1101 ExtraSGPRs = 2;
1102
1104 if (Version.Major >= 10)
1105 return ExtraSGPRs;
1106
1107 if (Version.Major < 8) {
1108 if (FlatScrUsed)
1109 ExtraSGPRs = 4;
1110 } else {
1111 if (XNACKUsed)
1112 ExtraSGPRs = 4;
1113
1114 if (FlatScrUsed ||
1116 ExtraSGPRs = 6;
1117 }
1118
1119 return ExtraSGPRs;
1120}
1121
1123 bool FlatScrUsed) {
1126}
1127
1129 unsigned Granule) {
1130 return divideCeil(std::max(1u, NumRegs), Granule);
1131}
1132
1134
1136 1;
1137}
1138
1140 std::optional EnableWavefrontSize32) {
1142 return 8;
1143
1144 bool IsWave32 = EnableWavefrontSize32 ?
1145 *EnableWavefrontSize32 :
1147
1149 return IsWave32 ? 24 : 12;
1150
1152 return IsWave32 ? 16 : 8;
1153
1154 return IsWave32 ? 8 : 4;
1155}
1156
1158 std::optional EnableWavefrontSize32) {
1160 return 8;
1161
1162 bool IsWave32 = EnableWavefrontSize32 ?
1163 *EnableWavefrontSize32 :
1165
1166 return IsWave32 ? 8 : 4;
1167}
1168
1171 return 512;
1173 return 256;
1176 return IsWave32 ? 1536 : 768;
1177 return IsWave32 ? 1024 : 512;
1178}
1179
1181
1184 return 512;
1186}
1187
1189 unsigned NumVGPRs) {
1193}
1194
1196 unsigned MaxWaves,
1197 unsigned TotalNumVGPRs) {
1198 if (NumVGPRs < Granule)
1199 return MaxWaves;
1200 unsigned RoundedRegs = alignTo(NumVGPRs, Granule);
1201 return std::min(std::max(TotalNumVGPRs / RoundedRegs, 1u), MaxWaves);
1202}
1203
1207 return MaxWaves;
1208
1210 if (SGPRs <= 80)
1211 return 10;
1212 if (SGPRs <= 88)
1213 return 9;
1214 if (SGPRs <= 100)
1215 return 8;
1216 return 7;
1217 }
1218 if (SGPRs <= 48)
1219 return 10;
1220 if (SGPRs <= 56)
1221 return 9;
1222 if (SGPRs <= 64)
1223 return 8;
1224 if (SGPRs <= 72)
1225 return 7;
1226 if (SGPRs <= 80)
1227 return 6;
1228 return 5;
1229}
1230
1232 assert(WavesPerEU != 0);
1233
1235 if (WavesPerEU >= MaxWavesPerEU)
1236 return 0;
1237
1241 unsigned MaxNumVGPRs = alignDown(TotNumVGPRs / WavesPerEU, Granule);
1242
1243 if (MaxNumVGPRs == alignDown(TotNumVGPRs / MaxWavesPerEU, Granule))
1244 return 0;
1245
1247 if (WavesPerEU < MinWavesPerEU)
1249
1250 unsigned MaxNumVGPRsNext = alignDown(TotNumVGPRs / (WavesPerEU + 1), Granule);
1251 unsigned MinNumVGPRs = 1 + std::min(MaxNumVGPRs - Granule, MaxNumVGPRsNext);
1252 return std::min(MinNumVGPRs, AddrsableNumVGPRs);
1253}
1254
1256 assert(WavesPerEU != 0);
1257
1261 return std::min(MaxNumVGPRs, AddressableNumVGPRs);
1262}
1263
1265 std::optional EnableWavefrontSize32) {
1268 1;
1269}
1270
1272 unsigned NumVGPRs,
1273 std::optional EnableWavefrontSize32) {
1276}
1277}
1278
1292 } else {
1294 }
1295
1296
1297
1299
1300
1301
1305
1306 if (Version.Major >= 10) {
1310 }
1311}
1312
1315}
1316
1319}
1320
1325}
1326
1329}
1330
1331std::pair<unsigned, unsigned>
1333 std::pair<unsigned, unsigned> Default,
1334 bool OnlyFirstRequired) {
1336 return {Attr->first, Attr->second ? *(Attr->second) : Default.second};
1338}
1339
1340std::optional<std::pair<unsigned, std::optional>>
1342 bool OnlyFirstRequired) {
1344 if (.isStringAttribute())
1345 return std::nullopt;
1346
1348 std::pair<unsigned, std::optional> Ints;
1349 std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
1350 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1351 Ctx.emitError("can't parse first integer attribute " + Name);
1352 return std::nullopt;
1353 }
1354 unsigned Second = 0;
1355 if (Strs.second.trim().getAsInteger(0, Second)) {
1356 if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1357 Ctx.emitError("can't parse second integer attribute " + Name);
1358 return std::nullopt;
1359 }
1360 } else {
1361 Ints.second = Second;
1362 }
1363
1364 return Ints;
1365}
1366
1368 unsigned Size,
1372
1374 if (.isStringAttribute())
1376
1378
1380
1382 unsigned i = 0;
1383 for (; !S.empty() && i < Size; i++) {
1384 std::pair<StringRef, StringRef> Strs = S.split(',');
1385 unsigned IntVal;
1386 if (Strs.first.trim().getAsInteger(0, IntVal)) {
1387 Ctx.emitError("can't parse integer attribute " + Strs.first + " in " +
1390 }
1391 Vals[i] = IntVal;
1392 S = Strs.second;
1393 }
1394
1397 " has incorrect number of integers; expected " +
1398 llvm::utostr(Size));
1400 }
1401 return Vals;
1402}
1403
1405 return (1 << (getVmcntBitWidthLo(Version.Major) +
1406 getVmcntBitWidthHi(Version.Major))) -
1407 1;
1408}
1409
1411 return (1 << getLoadcntBitWidth(Version.Major)) - 1;
1412}
1413
1415 return (1 << getSamplecntBitWidth(Version.Major)) - 1;
1416}
1417
1419 return (1 << getBvhcntBitWidth(Version.Major)) - 1;
1420}
1421
1423 return (1 << getExpcntBitWidth(Version.Major)) - 1;
1424}
1425
1427 return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
1428}
1429
1431 return (1 << getDscntBitWidth(Version.Major)) - 1;
1432}
1433
1435 return (1 << getKmcntBitWidth(Version.Major)) - 1;
1436}
1437
1439 return (1 << getStorecntBitWidth(Version.Major)) - 1;
1440}
1441
1443 unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major),
1444 getVmcntBitWidthLo(Version.Major));
1445 unsigned Expcnt = getBitMask(getExpcntBitShift(Version.Major),
1446 getExpcntBitWidth(Version.Major));
1447 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(Version.Major),
1448 getLgkmcntBitWidth(Version.Major));
1449 unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(Version.Major),
1450 getVmcntBitWidthHi(Version.Major));
1451 return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1452}
1453
1455 unsigned VmcntLo = unpackBits(Waitcnt, getVmcntBitShiftLo(Version.Major),
1456 getVmcntBitWidthLo(Version.Major));
1457 unsigned VmcntHi = unpackBits(Waitcnt, getVmcntBitShiftHi(Version.Major),
1458 getVmcntBitWidthHi(Version.Major));
1459 return VmcntLo | VmcntHi << getVmcntBitWidthLo(Version.Major);
1460}
1461
1463 return unpackBits(Waitcnt, getExpcntBitShift(Version.Major),
1464 getExpcntBitWidth(Version.Major));
1465}
1466
1468 return unpackBits(Waitcnt, getLgkmcntBitShift(Version.Major),
1469 getLgkmcntBitWidth(Version.Major));
1470}
1471
1473 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
1477}
1478
1484 return Decoded;
1485}
1486
1488 unsigned Vmcnt) {
1490 getVmcntBitWidthLo(Version.Major));
1491 return packBits(Vmcnt >> getVmcntBitWidthLo(Version.Major), Waitcnt,
1492 getVmcntBitShiftHi(Version.Major),
1493 getVmcntBitWidthHi(Version.Major));
1494}
1495
1497 unsigned Expcnt) {
1498 return packBits(Expcnt, Waitcnt, getExpcntBitShift(Version.Major),
1499 getExpcntBitWidth(Version.Major));
1500}
1501
1503 unsigned Lgkmcnt) {
1504 return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(Version.Major),
1505 getLgkmcntBitWidth(Version.Major));
1506}
1507
1509 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
1515}
1516
1519}
1520
1522 bool IsStore) {
1523 unsigned Dscnt = getBitMask(getDscntBitShift(Version.Major),
1524 getDscntBitWidth(Version.Major));
1525 if (IsStore) {
1526 unsigned Storecnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1527 getStorecntBitWidth(Version.Major));
1528 return Dscnt | Storecnt;
1529 }
1530 unsigned Loadcnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1531 getLoadcntBitWidth(Version.Major));
1532 return Dscnt | Loadcnt;
1533}
1534
1538 unpackBits(LoadcntDscnt, getLoadcntStorecntBitShift(Version.Major),
1539 getLoadcntBitWidth(Version.Major));
1540 Decoded.DsCnt = unpackBits(LoadcntDscnt, getDscntBitShift(Version.Major),
1541 getDscntBitWidth(Version.Major));
1542 return Decoded;
1543}
1544
1548 unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major),
1549 getStorecntBitWidth(Version.Major));
1550 Decoded.DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.Major),
1551 getDscntBitWidth(Version.Major));
1552 return Decoded;
1553}
1554
1556 unsigned Loadcnt) {
1557 return packBits(Loadcnt, Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1558 getLoadcntBitWidth(Version.Major));
1559}
1560
1562 unsigned Storecnt) {
1563 return packBits(Storecnt, Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1564 getStorecntBitWidth(Version.Major));
1565}
1566
1568 unsigned Dscnt) {
1569 return packBits(Dscnt, Waitcnt, getDscntBitShift(Version.Major),
1570 getDscntBitWidth(Version.Major));
1571}
1572
1574 unsigned Dscnt) {
1579}
1580
1583}
1584
1586 unsigned Storecnt, unsigned Dscnt) {
1591}
1592
1594 const Waitcnt &Decoded) {
1596}
1597
1598
1599
1600
1601
1605 unsigned Enc = 0;
1607 const auto &Op = Opr[Idx];
1608 if (Op.isSupported(STI))
1609 Enc |= Op.encode(Op.Default);
1610 }
1611 return Enc;
1612}
1613
1615 int Size, unsigned Code,
1616 bool &HasNonDefaultVal,
1618 unsigned UsedOprMask = 0;
1619 HasNonDefaultVal = false;
1621 const auto &Op = Opr[Idx];
1622 if (.isSupported(STI))
1623 continue;
1624 UsedOprMask |= Op.getMask();
1625 unsigned Val = Op.decode(Code);
1626 if (.isValid(Val))
1627 return false;
1628 HasNonDefaultVal |= (Val != Op.Default);
1629 }
1630 return (Code & ~UsedOprMask) == 0;
1631}
1632
1635 unsigned &Val, bool &IsDefault,
1638 const auto &Op = Opr[Idx++];
1639 if (Op.isSupported(STI)) {
1641 Val = Op.decode(Code);
1642 IsDefault = (Val == Op.Default);
1643 return true;
1644 }
1645 }
1646
1647 return false;
1648}
1649
1651 int64_t InputVal) {
1652 if (InputVal < 0 || InputVal > Op.Max)
1654 return Op.encode(InputVal);
1655}
1656
1659 unsigned &UsedOprMask,
1663 const auto &Op = Opr[Idx];
1665 if (.isSupported(STI)) {
1667 continue;
1668 }
1669 auto OprMask = Op.getMask();
1670 if (OprMask & UsedOprMask)
1672 UsedOprMask |= OprMask;
1674 }
1675 }
1676 return InvalidId;
1677}
1678
1679
1680
1681
1682
1683namespace DepCtr {
1684
1686 static int Default = -1;
1690}
1691
1695 HasNonDefaultVal, STI);
1696}
1697
1701 IsDefault, STI);
1702}
1703
1707 STI);
1708}
1709
1711 return unpackBits(Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1712}
1713
1715 return unpackBits(Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1716}
1717
1719 return unpackBits(Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1720}
1721
1723 return packBits(VmVsrc, Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1724}
1725
1728}
1729
1731 return packBits(VaVdst, Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1732}
1733
1736}
1737
1739 return packBits(SaSdst, Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1740}
1741
1744}
1745
1746}
1747
1748
1749
1750
1751
1752namespace Exp {
1753
1758};
1759
1768};
1769
1772 if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1773 Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1774 Name = Val.Name;
1775 return true;
1776 }
1777 }
1778 return false;
1779}
1780
1782
1784 if (Val.MaxIndex == 0 && Name == Val.Name)
1785 return Val.Tgt;
1786
1787 if (Val.MaxIndex > 0 && Name.starts_with(Val.Name)) {
1788 StringRef Suffix = Name.drop_front(Val.Name.size());
1789
1790 unsigned Id;
1791 if (Suffix.getAsInteger(10, Id) || Id > Val.MaxIndex)
1793
1794
1795 if (Suffix.size() > 1 && Suffix[0] == '0')
1797
1798 return Val.Tgt + Id;
1799 }
1800 }
1802}
1803
1805 switch (Id) {
1814 default:
1817 return true;
1818 }
1819}
1820
1821}
1822
1823
1824
1825
1826
1827namespace MTBUFFormat {
1828
1832 return Id;
1833 }
1835}
1836
1840}
1841
1848}
1849
1853 if (Name == lookupTable[Id])
1854 return Id;
1855 }
1857}
1858
1862}
1863
1865 unsigned Dfmt;
1866 unsigned Nfmt;
1869}
1870
1873}
1874
1877}
1878
1882}
1883
1888 return Id;
1889 }
1890 } else {
1893 return Id;
1894 }
1895 }
1897}
1898
1902 return "";
1903}
1904
1907}
1908
1915 return Id;
1916 }
1917 } else {
1920 return Id;
1921 }
1922 }
1924}
1925
1928}
1929
1934}
1935
1936}
1937
1938
1939
1940
1941
1942namespace SendMsg {
1943
1946}
1947
1950}
1951
1953 bool Strict) {
1955
1956 if (!Strict)
1957 return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1958
1961 return false;
1962
1964 }
1965
1967}
1968
1972
1973 if (!Strict)
1975
1977 switch (MsgId) {
1984 }
1985 }
1987}
1988
1993}
1994
2000}
2001
2006 OpId = 0;
2008 } else {
2011 }
2012}
2013
2018}
2019
2020}
2021
2022
2023
2024
2025
2027 return F.getFnAttributeAsParsedInteger("InitialPSInputAddr", 0);
2028}
2029
2031
2032 return F.getFnAttributeAsParsedInteger(
2033 "amdgpu-color-export",
2035}
2036
2038 return F.getFnAttributeAsParsedInteger("amdgpu-depth-export", 0) != 0;
2039}
2040
2042 switch(cc) {
2052 return true;
2053 default:
2054 return false;
2055 }
2056}
2057
2060}
2061
2064}
2065
2067 switch (CC) {
2077 return true;
2078 default:
2079 return false;
2080 }
2081}
2082
2084 switch (CC) {
2086 return true;
2087 default:
2089 }
2090}
2091
2093 switch (CC) {
2096 return true;
2097 default:
2098 return false;
2099 }
2100}
2101
2104}
2105
2107 return STI.hasFeature(AMDGPU::FeatureXNACK);
2108}
2109
2111 return STI.hasFeature(AMDGPU::FeatureSRAMECC);
2112}
2113
2115 return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
2116}
2117
2119 return STI.hasFeature(AMDGPU::FeatureA16);
2120}
2121
2123 return STI.hasFeature(AMDGPU::FeatureG16);
2124}
2125
2127 return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && (STI) &&
2129}
2130
2132 return STI.hasFeature(AMDGPU::FeatureGDS);
2133}
2134
2137 if (Version.Major == 10)
2138 return Version.Minor >= 3 ? 13 : 5;
2139 if (Version.Major == 11)
2140 return 5;
2141 if (Version.Major >= 12)
2142 return HasSampler ? 4 : 5;
2143 return 0;
2144}
2145
2147
2149 return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
2150}
2151
2153 return STI.hasFeature(AMDGPU::FeatureSeaIslands);
2154}
2155
2157 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2158}
2159
2161 return STI.hasFeature(AMDGPU::FeatureGFX9);
2162}
2163
2166}
2167
2170}
2171
2174}
2175
2178}
2179
2182}
2183
2185
2187 return STI.hasFeature(AMDGPU::FeatureGFX10);
2188}
2189
2192}
2193
2196}
2197
2199 return STI.hasFeature(AMDGPU::FeatureGFX11);
2200}
2201
2204}
2205
2208}
2209
2211
2213
2216}
2217
2220}
2221
2224}
2225
2227 return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
2228}
2229
2231 return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2232}
2233
2235 return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2236}
2237
2239 return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
2240}
2241
2244}
2245
2247 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2248}
2249
2251 return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
2252}
2253
2255 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2256}
2257
2259 return STI.hasFeature(AMDGPU::FeatureMAIInsts);
2260}
2261
2263 return STI.hasFeature(AMDGPU::FeatureVOPD);
2264}
2265
2267 return STI.hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2268}
2269
2271 return STI.hasFeature(AMDGPU::FeatureKernargPreload);
2272}
2273
2275 int32_t ArgNumVGPR) {
2276 if (has90AInsts && ArgNumAGPR)
2277 return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
2278 return std::max(ArgNumVGPR, ArgNumAGPR);
2279}
2280
2282 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
2283 const MCRegister FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
2284 return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
2285 Reg == AMDGPU::SCC;
2286}
2287
2290}
2291
2292#define MAP_REG2REG \
2293 using namespace AMDGPU; \
2294 switch(Reg.id()) { \
2295 default: return Reg; \
2296 CASE_CI_VI(FLAT_SCR) \
2297 CASE_CI_VI(FLAT_SCR_LO) \
2298 CASE_CI_VI(FLAT_SCR_HI) \
2299 CASE_VI_GFX9PLUS(TTMP0) \
2300 CASE_VI_GFX9PLUS(TTMP1) \
2301 CASE_VI_GFX9PLUS(TTMP2) \
2302 CASE_VI_GFX9PLUS(TTMP3) \
2303 CASE_VI_GFX9PLUS(TTMP4) \
2304 CASE_VI_GFX9PLUS(TTMP5) \
2305 CASE_VI_GFX9PLUS(TTMP6) \
2306 CASE_VI_GFX9PLUS(TTMP7) \
2307 CASE_VI_GFX9PLUS(TTMP8) \
2308 CASE_VI_GFX9PLUS(TTMP9) \
2309 CASE_VI_GFX9PLUS(TTMP10) \
2310 CASE_VI_GFX9PLUS(TTMP11) \
2311 CASE_VI_GFX9PLUS(TTMP12) \
2312 CASE_VI_GFX9PLUS(TTMP13) \
2313 CASE_VI_GFX9PLUS(TTMP14) \
2314 CASE_VI_GFX9PLUS(TTMP15) \
2315 CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
2316 CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
2317 CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
2318 CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
2319 CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
2320 CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
2321 CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
2322 CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
2323 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
2324 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
2325 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
2326 CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
2327 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
2328 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
2329 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2330 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2331 CASE_GFXPRE11_GFX11PLUS(M0) \
2332 CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
2333 CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
2334 }
2335
2336#define CASE_CI_VI(node) \
2337 assert(!isSI(STI)); \
2338 case node: return isCI(STI) ? node##_ci : node##_vi;
2339
2340#define CASE_VI_GFX9PLUS(node) \
2341 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2342
2343#define CASE_GFXPRE11_GFX11PLUS(node) \
2344 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2345
2346#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
2347 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2348
2351 return Reg;
2353}
2354
2355#undef CASE_CI_VI
2356#undef CASE_VI_GFX9PLUS
2357#undef CASE_GFXPRE11_GFX11PLUS
2358#undef CASE_GFXPRE11_GFX11PLUS_TO
2359
2360#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
2361#define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
2362#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
2363#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
2364
2366
2368 switch (Reg) {
2369 case AMDGPU::SRC_SHARED_BASE_LO:
2370 case AMDGPU::SRC_SHARED_BASE:
2371 case AMDGPU::SRC_SHARED_LIMIT_LO:
2372 case AMDGPU::SRC_SHARED_LIMIT:
2373 case AMDGPU::SRC_PRIVATE_BASE_LO:
2374 case AMDGPU::SRC_PRIVATE_BASE:
2375 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2376 case AMDGPU::SRC_PRIVATE_LIMIT:
2377 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2378 return true;
2379 case AMDGPU::SRC_VCCZ:
2380 case AMDGPU::SRC_EXECZ:
2381 case AMDGPU::SRC_SCC:
2382 return true;
2383 case AMDGPU::SGPR_NULL:
2384 return true;
2385 default:
2386 return false;
2387 }
2388}
2389
2390#undef CASE_CI_VI
2391#undef CASE_VI_GFX9PLUS
2392#undef CASE_GFXPRE11_GFX11PLUS
2393#undef CASE_GFXPRE11_GFX11PLUS_TO
2394#undef MAP_REG2REG
2395
2398 unsigned OpType = Desc.operands()[OpNo].OperandType;
2401}
2402
2405 unsigned OpType = Desc.operands()[OpNo].OperandType;
2408}
2409
2412 unsigned OpType = Desc.operands()[OpNo].OperandType;
2413 switch (OpType) {
2430 return true;
2431 default:
2432 return false;
2433 }
2434}
2435
2438 unsigned OpType = Desc.operands()[OpNo].OperandType;
2443}
2444
2445
2446
2448 switch (RCID) {
2449 case AMDGPU::SGPR_LO16RegClassID:
2450 case AMDGPU::AGPR_LO16RegClassID:
2451 return 16;
2452 case AMDGPU::SGPR_32RegClassID:
2453 case AMDGPU::VGPR_32RegClassID:
2454 case AMDGPU::VRegOrLds_32RegClassID:
2455 case AMDGPU::AGPR_32RegClassID:
2456 case AMDGPU::VS_32RegClassID:
2457 case AMDGPU::AV_32RegClassID:
2458 case AMDGPU::SReg_32RegClassID:
2459 case AMDGPU::SReg_32_XM0RegClassID:
2460 case AMDGPU::SRegOrLds_32RegClassID:
2461 return 32;
2462 case AMDGPU::SGPR_64RegClassID:
2463 case AMDGPU::VS_64RegClassID:
2464 case AMDGPU::SReg_64RegClassID:
2465 case AMDGPU::VReg_64RegClassID:
2466 case AMDGPU::AReg_64RegClassID:
2467 case AMDGPU::SReg_64_XEXECRegClassID:
2468 case AMDGPU::VReg_64_Align2RegClassID:
2469 case AMDGPU::AReg_64_Align2RegClassID:
2470 case AMDGPU::AV_64RegClassID:
2471 case AMDGPU::AV_64_Align2RegClassID:
2472 return 64;
2473 case AMDGPU::SGPR_96RegClassID:
2474 case AMDGPU::SReg_96RegClassID:
2475 case AMDGPU::VReg_96RegClassID:
2476 case AMDGPU::AReg_96RegClassID:
2477 case AMDGPU::VReg_96_Align2RegClassID:
2478 case AMDGPU::AReg_96_Align2RegClassID:
2479 case AMDGPU::AV_96RegClassID:
2480 case AMDGPU::AV_96_Align2RegClassID:
2481 return 96;
2482 case AMDGPU::SGPR_128RegClassID:
2483 case AMDGPU::SReg_128RegClassID:
2484 case AMDGPU::VReg_128RegClassID:
2485 case AMDGPU::AReg_128RegClassID:
2486 case AMDGPU::VReg_128_Align2RegClassID:
2487 case AMDGPU::AReg_128_Align2RegClassID:
2488 case AMDGPU::AV_128RegClassID:
2489 case AMDGPU::AV_128_Align2RegClassID:
2490 return 128;
2491 case AMDGPU::SGPR_160RegClassID:
2492 case AMDGPU::SReg_160RegClassID:
2493 case AMDGPU::VReg_160RegClassID:
2494 case AMDGPU::AReg_160RegClassID:
2495 case AMDGPU::VReg_160_Align2RegClassID:
2496 case AMDGPU::AReg_160_Align2RegClassID:
2497 case AMDGPU::AV_160RegClassID:
2498 case AMDGPU::AV_160_Align2RegClassID:
2499 return 160;
2500 case AMDGPU::SGPR_192RegClassID:
2501 case AMDGPU::SReg_192RegClassID:
2502 case AMDGPU::VReg_192RegClassID:
2503 case AMDGPU::AReg_192RegClassID:
2504 case AMDGPU::VReg_192_Align2RegClassID:
2505 case AMDGPU::AReg_192_Align2RegClassID:
2506 case AMDGPU::AV_192RegClassID:
2507 case AMDGPU::AV_192_Align2RegClassID:
2508 return 192;
2509 case AMDGPU::SGPR_224RegClassID:
2510 case AMDGPU::SReg_224RegClassID:
2511 case AMDGPU::VReg_224RegClassID:
2512 case AMDGPU::AReg_224RegClassID:
2513 case AMDGPU::VReg_224_Align2RegClassID:
2514 case AMDGPU::AReg_224_Align2RegClassID:
2515 case AMDGPU::AV_224RegClassID:
2516 case AMDGPU::AV_224_Align2RegClassID:
2517 return 224;
2518 case AMDGPU::SGPR_256RegClassID:
2519 case AMDGPU::SReg_256RegClassID:
2520 case AMDGPU::VReg_256RegClassID:
2521 case AMDGPU::AReg_256RegClassID:
2522 case AMDGPU::VReg_256_Align2RegClassID:
2523 case AMDGPU::AReg_256_Align2RegClassID:
2524 case AMDGPU::AV_256RegClassID:
2525 case AMDGPU::AV_256_Align2RegClassID:
2526 return 256;
2527 case AMDGPU::SGPR_288RegClassID:
2528 case AMDGPU::SReg_288RegClassID:
2529 case AMDGPU::VReg_288RegClassID:
2530 case AMDGPU::AReg_288RegClassID:
2531 case AMDGPU::VReg_288_Align2RegClassID:
2532 case AMDGPU::AReg_288_Align2RegClassID:
2533 case AMDGPU::AV_288RegClassID:
2534 case AMDGPU::AV_288_Align2RegClassID:
2535 return 288;
2536 case AMDGPU::SGPR_320RegClassID:
2537 case AMDGPU::SReg_320RegClassID:
2538 case AMDGPU::VReg_320RegClassID:
2539 case AMDGPU::AReg_320RegClassID:
2540 case AMDGPU::VReg_320_Align2RegClassID:
2541 case AMDGPU::AReg_320_Align2RegClassID:
2542 case AMDGPU::AV_320RegClassID:
2543 case AMDGPU::AV_320_Align2RegClassID:
2544 return 320;
2545 case AMDGPU::SGPR_352RegClassID:
2546 case AMDGPU::SReg_352RegClassID:
2547 case AMDGPU::VReg_352RegClassID:
2548 case AMDGPU::AReg_352RegClassID:
2549 case AMDGPU::VReg_352_Align2RegClassID:
2550 case AMDGPU::AReg_352_Align2RegClassID:
2551 case AMDGPU::AV_352RegClassID:
2552 case AMDGPU::AV_352_Align2RegClassID:
2553 return 352;
2554 case AMDGPU::SGPR_384RegClassID:
2555 case AMDGPU::SReg_384RegClassID:
2556 case AMDGPU::VReg_384RegClassID:
2557 case AMDGPU::AReg_384RegClassID:
2558 case AMDGPU::VReg_384_Align2RegClassID:
2559 case AMDGPU::AReg_384_Align2RegClassID:
2560 case AMDGPU::AV_384RegClassID:
2561 case AMDGPU::AV_384_Align2RegClassID:
2562 return 384;
2563 case AMDGPU::SGPR_512RegClassID:
2564 case AMDGPU::SReg_512RegClassID:
2565 case AMDGPU::VReg_512RegClassID:
2566 case AMDGPU::AReg_512RegClassID:
2567 case AMDGPU::VReg_512_Align2RegClassID:
2568 case AMDGPU::AReg_512_Align2RegClassID:
2569 case AMDGPU::AV_512RegClassID:
2570 case AMDGPU::AV_512_Align2RegClassID:
2571 return 512;
2572 case AMDGPU::SGPR_1024RegClassID:
2573 case AMDGPU::SReg_1024RegClassID:
2574 case AMDGPU::VReg_1024RegClassID:
2575 case AMDGPU::AReg_1024RegClassID:
2576 case AMDGPU::VReg_1024_Align2RegClassID:
2577 case AMDGPU::AReg_1024_Align2RegClassID:
2578 case AMDGPU::AV_1024RegClassID:
2579 case AMDGPU::AV_1024_Align2RegClassID:
2580 return 1024;
2581 default:
2583 }
2584}
2585
2588}
2589
2591 unsigned OpNo) {
2593 unsigned RCID = Desc.operands()[OpNo].RegClass;
2595}
2596
2599 return true;
2600
2602 return (Val == llvm::bit_cast<uint64_t>(0.0)) ||
2603 (Val == llvm::bit_cast<uint64_t>(1.0)) ||
2604 (Val == llvm::bit_cast<uint64_t>(-1.0)) ||
2605 (Val == llvm::bit_cast<uint64_t>(0.5)) ||
2606 (Val == llvm::bit_cast<uint64_t>(-0.5)) ||
2607 (Val == llvm::bit_cast<uint64_t>(2.0)) ||
2608 (Val == llvm::bit_cast<uint64_t>(-2.0)) ||
2609 (Val == llvm::bit_cast<uint64_t>(4.0)) ||
2610 (Val == llvm::bit_cast<uint64_t>(-4.0)) ||
2611 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2612}
2613
2616 return true;
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2628 return (Val == llvm::bit_cast<uint32_t>(0.0f)) ||
2629 (Val == llvm::bit_cast<uint32_t>(1.0f)) ||
2630 (Val == llvm::bit_cast<uint32_t>(-1.0f)) ||
2631 (Val == llvm::bit_cast<uint32_t>(0.5f)) ||
2632 (Val == llvm::bit_cast<uint32_t>(-0.5f)) ||
2633 (Val == llvm::bit_cast<uint32_t>(2.0f)) ||
2634 (Val == llvm::bit_cast<uint32_t>(-2.0f)) ||
2635 (Val == llvm::bit_cast<uint32_t>(4.0f)) ||
2636 (Val == llvm::bit_cast<uint32_t>(-4.0f)) ||
2637 (Val == 0x3e22f983 && HasInv2Pi);
2638}
2639
2641 if (!HasInv2Pi)
2642 return false;
2644 return true;
2646 return Val == 0x3F00 ||
2647 Val == 0xBF00 ||
2648 Val == 0x3F80 ||
2649 Val == 0xBF80 ||
2650 Val == 0x4000 ||
2651 Val == 0xC000 ||
2652 Val == 0x4080 ||
2653 Val == 0xC080 ||
2654 Val == 0x3E22;
2655}
2656
2659}
2660
2662 if (!HasInv2Pi)
2663 return false;
2665 return true;
2667 return Val == 0x3C00 ||
2668 Val == 0xBC00 ||
2669 Val == 0x3800 ||
2670 Val == 0xB800 ||
2671 Val == 0x4000 ||
2672 Val == 0xC000 ||
2673 Val == 0x4400 ||
2674 Val == 0xC400 ||
2675 Val == 0x3118;
2676}
2677
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2691 return 128 + Signed;
2692
2694 return 192 + std::abs(Signed);
2695
2696 if (IsFloat) {
2697
2699 case 0x3800: return 240;
2700 case 0xB800: return 241;
2701 case 0x3C00: return 242;
2702 case 0xBC00: return 243;
2703 case 0x4000: return 244;
2704 case 0xC000: return 245;
2705 case 0x4400: return 246;
2706 case 0xC400: return 247;
2707 case 0x3118: return 248;
2708 default: break;
2709 }
2710
2711 } else {
2712
2714 case 0x3F000000: return 240;
2715 case 0xBF000000: return 241;
2716 case 0x3F800000: return 242;
2717 case 0xBF800000: return 243;
2718 case 0x40000000: return 244;
2719 case 0xC0000000: return 245;
2720 case 0x40800000: return 246;
2721 case 0xC0800000: return 247;
2722 case 0x3E22F983: return 248;
2723 default: break;
2724 }
2725
2726 }
2727
2728 return {};
2729}
2730
2731
2732
2735}
2736
2737
2738
2742 return 128 + Signed;
2743
2745 return 192 + std::abs(Signed);
2746
2747
2749 case 0x3F00: return 240;
2750 case 0xBF00: return 241;
2751 case 0x3F80: return 242;
2752 case 0xBF80: return 243;
2753 case 0x4000: return 244;
2754 case 0xC000: return 245;
2755 case 0x4080: return 246;
2756 case 0xC080: return 247;
2757 case 0x3E22: return 248;
2758 default: break;
2759 }
2760
2761
2762 return std::nullopt;
2763}
2764
2765
2766
2769}
2770
2771
2773 switch (OpType) {
2786 default:
2788 }
2789}
2790
2791
2794}
2795
2796
2799}
2800
2801
2804}
2805
2807 if (IsFP64)
2808 return !(Val & 0xffffffffu);
2809
2810 return isUInt<32>(Val) || isInt<32>(Val);
2811}
2812
2815
2816
2818 switch (CC) {
2821 return true;
2832
2833
2834 return A->hasAttribute(Attribute::InReg) ||
2835 A->hasAttribute(Attribute::ByVal);
2836 default:
2837
2838 return A->hasAttribute(Attribute::InReg);
2839 }
2840}
2841
2843
2845 switch (CC) {
2848 return true;
2859
2860
2861 return CB->paramHasAttr(ArgNo, Attribute::InReg) ||
2863 default:
2864 return CB->paramHasAttr(ArgNo, Attribute::InReg);
2865 }
2866}
2867
2870}
2871
2873 int64_t EncodedOffset) {
2875 return isUInt<23>(EncodedOffset);
2876
2878 : isUInt<8>(EncodedOffset);
2879}
2880
2882 int64_t EncodedOffset,
2883 bool IsBuffer) {
2885 return isInt<24>(EncodedOffset);
2886
2887 return !IsBuffer &&
2889 isInt<21>(EncodedOffset);
2890}
2891
2893 return (ByteOffset & 3) == 0;
2894}
2895
2899 return ByteOffset;
2900
2902 return ByteOffset >> 2;
2903}
2904
2906 int64_t ByteOffset, bool IsBuffer,
2907 bool HasSOffset) {
2908
2909
2910
2912 return std::nullopt;
2913
2914 if (isGFX12Plus(ST))
2915 return isInt<24>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2916 : std::nullopt;
2917
2918
2921 return isInt<20>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2922 : std::nullopt;
2923 }
2924
2926 return std::nullopt;
2927
2930 ? std::optional<int64_t>(EncodedOffset)
2931 : std::nullopt;
2932}
2933
2935 int64_t ByteOffset) {
2937 return std::nullopt;
2938
2940 return isUInt<32>(EncodedOffset) ? std::optional<int64_t>(EncodedOffset)
2941 : std::nullopt;
2942}
2943
2946 return 12;
2947
2949 return 24;
2950 return 13;
2951}
2952
2953namespace {
2954
2955struct SourceOfDivergence {
2957};
2958const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
2959
2961 unsigned Intr;
2962};
2964
2965#define GET_SourcesOfDivergence_IMPL
2966#define GET_UniformIntrinsics_IMPL
2967#define GET_Gfx9BufferFormat_IMPL
2968#define GET_Gfx10BufferFormat_IMPL
2969#define GET_Gfx11PlusBufferFormat_IMPL
2970
2971#include "AMDGPUGenSearchableTables.inc"
2972
2973}
2974
2976 return lookupSourceOfDivergence(IntrID);
2977}
2978
2980 return lookupAlwaysUniform(IntrID);
2981}
2982
2988 ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
2989 NumFormat)
2990 : isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2991 NumComponents, NumFormat)
2992 : getGfx9BufferFormatInfo(BitsPerComp,
2993 NumComponents, NumFormat);
2994}
2995
2999 : isGFX10(STI) ? getGfx10BufferFormatInfo(Format)
3000 : getGfx9BufferFormatInfo(Format);
3001}
3002
3004 for (auto OpName : { OpName::vdst, OpName::src0, OpName::src1,
3005 OpName::src2 }) {
3007 if (Idx == -1)
3008 continue;
3009
3010 if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID ||
3011 OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
3012 return true;
3013 }
3014
3015 return false;
3016}
3017
3020}
3021
3023
3024 return 128;
3025}
3026
3027}
3028
3031 switch (S) {
3033 OS << "Unsupported";
3034 break;
3036 OS << "Any";
3037 break;
3039 OS << "Off";
3040 break;
3042 OS << "On";
3043 break;
3044 }
3045 return OS;
3046}
3047
3048}
unsigned const MachineRegisterInfo * MRI
static llvm:🆑:opt< unsigned > DefaultAMDHSACodeObjectVersion("amdhsa-code-object-version", llvm:🆑:Hidden, llvm:🆑:init(llvm::AMDGPU::AMDHSA_COV5), llvm:🆑:desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))
Provides AMDGPU specific target descriptions.
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
#define S_00B848_MEM_ORDERED(x)
#define S_00B848_WGP_MODE(x)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned unsigned DefaultVal
bool isSramEccSupported() const
void setTargetIDFromFeaturesString(StringRef FS)
TargetIDSetting getXnackSetting() const
AMDGPUTargetID(const MCSubtargetInfo &STI)
bool isXnackSupported() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
std::string toString() const
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
unsigned getIndexOfDstInParsedOperands() const
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
unsigned getCompParsedSrcOperandsNum() const
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
CallingConv::ID getCallingConv() const
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Determine whether the argument or parameter has the given attribute.
This class represents an Operation in the Expression.
constexpr bool test(unsigned I) const
unsigned getAddressSpace() const
This is an important class for using LLVM in a threaded context.
void emitError(const Instruction *I, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
const FeatureBitset & getFeatureBits() const
A Module instance is used to store all the information related to an LLVM module.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
std::string str() const
str - Get the contents as an std::string.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Manages the enabling and disabling of subtarget specific features.
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Triple - Helper class for working with autoconf configuration names.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ LOCAL_ADDRESS
Address space for local memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
const CustomOperandVal DepCtrInfo[]
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
static constexpr ExpTgt ExpTgtInfo[]
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
@ ET_DUAL_SRC_BLEND_MAX_IDX
constexpr uint32_t VersionMajor
HSA metadata major version.
@ COMPLETION_ACTION_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)
static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs, unsigned Granule)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
StringLiteral const UfmtSymbolicGFX11[]
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
unsigned const DfmtNfmt2UFmtGFX10[]
StringLiteral const DfmtSymbolic[]
static StringLiteral const * getNfmtLookupTable(const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
StringLiteral const NfmtSymbolicGFX10[]
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
unsigned const DfmtNfmt2UFmtGFX11[]
StringLiteral const NfmtSymbolicVI[]
StringLiteral const NfmtSymbolicSICI[]
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
StringLiteral const UfmtSymbolicGFX10[]
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a sendmsg operation.
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
const int OPR_ID_UNSUPPORTED
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI)
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV216(bool IsFloat, uint32_t Literal)
FPType getFPDstSelType(unsigned Opc)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
const int OPR_VAL_INVALID
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
uint8_t mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal)
bool isGroupSegment(const GlobalValue *GV)
IsaVersion getIsaVersion(StringRef GPU)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
static unsigned getCombinedCountBitMask(const IsaVersion &Version, bool IsStore)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
static bool isDwordAligned(uint64_t ByteOffset)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFTfe(unsigned Opc)
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
bool isGFX10Plus(const MCSubtargetInfo &STI)
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_V2BF16
@ OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)
bool isNotGFX9Plus(const MCSubtargetInfo &STI)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
const int OPR_ID_DUPLICATE
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
bool getMUBUFIsBufferInv(unsigned Opc)
MCRegister mc2PseudoReg(MCRegister Reg)
Convert hardware register Reg to a pseudo register.
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
const MFMA_F8F6F4_Info * getMFMA_F8F6F4_WithFormatArgs(unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V6
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
constexpr T alignDown(U Value, V Align, W Skew=0)
Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
constexpr T divideCeil(U Numerator, V Denominator)
Returns the integer ceil(Numerator / Denominator).
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
@ AlwaysUniform
The result values are always uniform.
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
uint16_t amd_machine_version_major
uint16_t amd_machine_kind
uint16_t amd_machine_version_stepping
uint8_t private_segment_alignment
int64_t kernel_code_entry_byte_offset
uint32_t amd_kernel_code_version_major
uint16_t amd_machine_version_minor
uint8_t group_segment_alignment
uint8_t kernarg_segment_alignment
uint32_t amd_kernel_code_version_minor
uint64_t compute_pgm_resource_registers
Instruction set architecture version.
Represents the counter values to wait for in an s_waitcnt instruction.
Description of the encoding of one expression Op.