LLVM: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp File Reference (original) (raw)

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Classes
struct llvm::AMDGPU::MUBUFInfo
struct llvm::AMDGPU::MTBUFInfo
struct llvm::AMDGPU::SMInfo
struct llvm::AMDGPU::VOPInfo
struct llvm::AMDGPU::VOPC64DPPInfo
struct llvm::AMDGPU::VOPCDPPAsmOnlyInfo
struct llvm::AMDGPU::VOP3CDPPAsmOnlyInfo
struct llvm::AMDGPU::VOPDComponentInfo
struct llvm::AMDGPU::VOPDInfo
struct llvm::AMDGPU::VOPTrue16Info
struct llvm::AMDGPU::DPMACCInstructionInfo
struct llvm::AMDGPU::FP4FP8DstByteSelInfo
struct llvm::AMDGPU::Exp::ExpTgt
Namespaces
namespace llvm
This is an optimization pass for GlobalISel generic memory operations.
namespace llvm::AMDGPU
namespace llvm::AMDGPU::VOPD
namespace llvm::AMDGPU::IsaInfo
namespace llvm::AMDGPU::DepCtr
namespace llvm::AMDGPU::Exp
namespace llvm::AMDGPU::MTBUFFormat
namespace llvm::AMDGPU::SendMsg
Macros
#define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRMAP_INFO
#define GET_MIMGBaseOpcodesTable_IMPL
#define GET_MIMGDimInfoTable_IMPL
#define GET_MIMGInfoTable_IMPL
#define GET_MIMGLZMappingTable_IMPL
#define GET_MIMGMIPMappingTable_IMPL
#define GET_MIMGBiasMappingTable_IMPL
#define GET_MIMGOffsetMappingTable_IMPL
#define GET_MIMGG16MappingTable_IMPL
#define GET_MAIInstInfoTable_IMPL
#define GET_WMMAInstInfoTable_IMPL
#define GET_FP4FP8DstByteSelTable_DECL
#define GET_FP4FP8DstByteSelTable_IMPL
#define GET_MTBUFInfoTable_DECL
#define GET_MTBUFInfoTable_IMPL
#define GET_MUBUFInfoTable_DECL
#define GET_MUBUFInfoTable_IMPL
#define GET_SMInfoTable_DECL
#define GET_SMInfoTable_IMPL
#define GET_VOP1InfoTable_DECL
#define GET_VOP1InfoTable_IMPL
#define GET_VOP2InfoTable_DECL
#define GET_VOP2InfoTable_IMPL
#define GET_VOP3InfoTable_DECL
#define GET_VOP3InfoTable_IMPL
#define GET_VOPC64DPPTable_DECL
#define GET_VOPC64DPPTable_IMPL
#define GET_VOPC64DPP8Table_DECL
#define GET_VOPC64DPP8Table_IMPL
#define GET_VOPCAsmOnlyInfoTable_DECL
#define GET_VOPCAsmOnlyInfoTable_IMPL
#define GET_VOP3CAsmOnlyInfoTable_DECL
#define GET_VOP3CAsmOnlyInfoTable_IMPL
#define GET_VOPDComponentTable_DECL
#define GET_VOPDComponentTable_IMPL
#define GET_VOPDPairs_DECL
#define GET_VOPDPairs_IMPL
#define GET_VOPTrue16Table_DECL
#define GET_VOPTrue16Table_IMPL
#define GET_True16D16Table_IMPL
#define GET_WMMAOpcode2AddrMappingTable_DECL
#define GET_WMMAOpcode2AddrMappingTable_IMPL
#define GET_WMMAOpcode3AddrMappingTable_DECL
#define GET_WMMAOpcode3AddrMappingTable_IMPL
#define GET_getMFMA_F8F6F4_WithSize_DECL
#define GET_getMFMA_F8F6F4_WithSize_IMPL
#define GET_isMFMA_F8F6F4Table_IMPL
#define GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL
#define MAP_REG2REG
#define CASE_CI_VI(node)
#define CASE_VI_GFX9PLUS(node)
#define CASE_GFXPRE11_GFX11PLUS(node)
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
#define CASE_CI_VI(node)
#define CASE_VI_GFX9PLUS(node)
#define CASE_GFXPRE11_GFX11PLUS(node)
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
#define GET_SourcesOfDivergence_IMPL
#define GET_UniformIntrinsics_IMPL
#define GET_Gfx9BufferFormat_IMPL
#define GET_Gfx10BufferFormat_IMPL
#define GET_Gfx11PlusBufferFormat_IMPL
Functions
bool llvm::AMDGPU::hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
bool llvm::AMDGPU::isHsaAbi (const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion (const Module &M)
unsigned llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion ()
unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion (unsigned ABIVersion)
uint8_t llvm::AMDGPU::getELFABIVersion (const Triple &T, unsigned CodeObjectVersion)
unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)
unsigned llvm::AMDGPU::getHostcallImplicitArgPosition (unsigned CodeObjectVersion)
unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)
unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)
int llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode (unsigned Opc)
int llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
unsigned llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc)
int llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
int llvm::AMDGPU::getMTBUFElements (unsigned Opc)
bool llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc)
bool llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc)
bool llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc)
int llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc)
int llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
int llvm::AMDGPU::getMUBUFElements (unsigned Opc)
bool llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc)
bool llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc)
bool llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc)
bool llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc)
bool llvm::AMDGPU::getMUBUFTfe (unsigned Opc)
bool llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc)
bool llvm::AMDGPU::getVOP1IsSingle (unsigned Opc)
bool llvm::AMDGPU::getVOP2IsSingle (unsigned Opc)
bool llvm::AMDGPU::getVOP3IsSingle (unsigned Opc)
bool llvm::AMDGPU::isVOPC64DPP (unsigned Opc)
bool llvm::AMDGPU::isVOPCAsmOnly (unsigned Opc)
bool llvm::AMDGPU::getMAIIsDGEMM (unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
bool llvm::AMDGPU::getMAIIsGFX940XDL (unsigned Opc)
bool llvm::AMDGPU::getWMMAIsXDL (unsigned Opc)
uint8_t llvm::AMDGPU::mfmaScaleF8F6F4FormatToNumRegs (unsigned EncodingVal)
const MFMA_F8F6F4_Info * llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs (unsigned CBSZ, unsigned BLGP, unsigned F8F8Opcode)
uint8_t llvm::AMDGPU::wmmaScaleF8F6F4FormatToNumRegs (unsigned Fmt)
const MFMA_F8F6F4_Info * llvm::AMDGPU::getWMMA_F8F6F4_WithFormatArgs (unsigned FmtA, unsigned FmtB, unsigned F8F8Opcode)
unsigned llvm::AMDGPU::getVOPDEncodingFamily (const MCSubtargetInfo &ST)
CanBeVOPD llvm::AMDGPU::getCanBeVOPD (unsigned Opc, unsigned EncodingFamily, bool VOPD3)
unsigned llvm::AMDGPU::getVOPDOpcode (unsigned Opc, bool VOPD3)
bool llvm::AMDGPU::isVOPD (unsigned Opc)
bool llvm::AMDGPU::isMAC (unsigned Opc)
bool llvm::AMDGPU::isPermlane16 (unsigned Opc)
bool llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)
bool llvm::AMDGPU::isGenericAtomic (unsigned Opc)
bool llvm::AMDGPU::isAsyncStore (unsigned Opc)
bool llvm::AMDGPU::isTensorStore (unsigned Opc)
unsigned llvm::AMDGPU::getTemporalHintType (const MCInstrDesc TID)
bool llvm::AMDGPU::isTrue16Inst (unsigned Opc)
FPType llvm::AMDGPU::getFPDstSelType (unsigned Opc)
unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode (unsigned Opc)
int llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)
unsigned llvm::AMDGPU::getBitOp2 (unsigned Opc)
int llvm::AMDGPU::getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily, bool VOPD3)
std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents (unsigned VOPDOpcode)
VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)
VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)
static TargetIDSetting llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString (StringRef FeatureString)
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)
static unsigned llvm::AMDGPU::IsaInfo::getGranulatedNumRegisterBlocks (unsigned NumRegs, unsigned Granule)
unsigned llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, unsigned DynamicVGPRBlockSize, std::optional< bool > EnableWavefrontSize32)
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned llvm::AMDGPU::IsaInfo::getArchVGPRAllocGranule ()
For subtargets with a unified VGPR file and mixed ArchVGPR/AGPR usage, returns the allocation granule for ArchVGPRs.
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumArchVGPRs (const MCSubtargetInfo *STI)
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI, unsigned DynamicVGPRBlockSize)
unsigned llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (const MCSubtargetInfo *STI, unsigned NumVGPRs, unsigned DynamicVGPRBlockSize)
unsigned llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (unsigned NumVGPRs, unsigned Granule, unsigned MaxWaves, unsigned TotalNumVGPRs)
unsigned llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs (unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, unsigned DynamicVGPRBlockSize)
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, unsigned DynamicVGPRBlockSize)
unsigned llvm::AMDGPU::IsaInfo::getEncodedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned llvm::AMDGPU::IsaInfo::getAllocatedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, unsigned DynamicVGPRBlockSize, std::optional< bool > EnableWavefrontSize32)
void llvm::AMDGPU::initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
static bool llvm::AMDGPU::isValidRegPrefix (char C)
std::tuple< char, unsigned, unsigned > llvm::AMDGPU::parseAsmPhysRegName (StringRef TupleString)
Returns a valid charcode or 0 in the first entry if this is a valid physical register name.
std::tuple< char, unsigned, unsigned > llvm::AMDGPU::parseAsmConstraintPhysReg (StringRef Constraint)
Returns a valid charcode or 0 in the first entry if this is a valid physical register constraint.
std::pair< unsigned, unsigned > llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
std::optional< std::pair< unsigned, std::optional< unsigned > > > llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, bool OnlyFirstRequired)
SmallVector< unsigned > llvm::AMDGPU::getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size, unsigned DefaultVal)
std::optional< SmallVector< unsigned > > llvm::AMDGPU::getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size)
Similar to the function above, but returns std::nullopt if any error occurs.
bool llvm::AMDGPU::hasValueInRangeLikeMetadata (const MDNode &MD, int64_t Val)
Checks if Val is inside MD, a !range-like metadata.
unsigned llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getLoadcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getSamplecntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getBvhcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getDscntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getKmcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getXcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getStorecntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version)
unsigned llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
unsigned llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
void llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.
Waitcnt llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
unsigned llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
unsigned llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
static unsigned llvm::AMDGPU::getCombinedCountBitMask (const IsaVersion &Version, bool IsStore)
Waitcnt llvm::AMDGPU::decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt)
Waitcnt llvm::AMDGPU::decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt)
static unsigned llvm::AMDGPU::encodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
static unsigned llvm::AMDGPU::encodeStorecnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static unsigned llvm::AMDGPU::encodeDscnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
static unsigned llvm::AMDGPU::encodeLoadcntDscnt (const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
unsigned llvm::AMDGPU::encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)
static unsigned llvm::AMDGPU::encodeStorecntDscnt (const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
unsigned llvm::AMDGPU::encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)
static unsigned llvm::AMDGPU::getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static bool llvm::AMDGPU::isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
static bool llvm::AMDGPU::decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
static int llvm::AMDGPU::encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)
static int llvm::AMDGPU::encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
int llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding (unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::DepCtr::decodeDepCtr (unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
int llvm::AMDGPU::DepCtr::encodeDepCtr (const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::decodeFieldVmVsrc (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::decodeFieldVaVdst (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::decodeFieldSaSdst (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::decodeFieldVaSdst (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::decodeFieldVaVcc (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::decodeFieldVaSsrc (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::decodeFieldHoldCnt (unsigned Encoded)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned Encoded, unsigned VmVsrc)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned VmVsrc, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned Encoded, unsigned VaVdst)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned VaVdst, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned Encoded, unsigned SaSdst)
unsigned llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned SaSdst, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaSdst (unsigned Encoded, unsigned VaSdst)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaSdst (unsigned VaSdst, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaVcc (unsigned Encoded, unsigned VaVcc)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaVcc (unsigned VaVcc, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaSsrc (unsigned Encoded, unsigned VaSsrc)
unsigned llvm::AMDGPU::DepCtr::encodeFieldVaSsrc (unsigned VaSsrc, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::DepCtr::encodeFieldHoldCnt (unsigned Encoded, unsigned HoldCnt)
unsigned llvm::AMDGPU::DepCtr::encodeFieldHoldCnt (unsigned HoldCnt, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index)
unsigned llvm::AMDGPU::Exp::getTgtId (const StringRef Name)
bool llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI)
int64_t llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name)
StringRef llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id)
static StringLiteral const * llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable (const MCSubtargetInfo &STI)
int64_t llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI)
StringRef llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI)
int64_t llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt)
void llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
int64_t llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name, const MCSubtargetInfo &STI)
StringRef llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id, const MCSubtargetInfo &STI)
int64_t llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI)
static uint64_t llvm::AMDGPU::SendMsg::getMsgIdMask (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
bool llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId, const MCSubtargetInfo &STI)
bool llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
uint64_t llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
bool llvm::AMDGPU::getHasColorExport (const Function &F)
bool llvm::AMDGPU::getHasDepthExport (const Function &F)
unsigned llvm::AMDGPU::getDynamicVGPRBlockSize (const Function &F)
bool llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasA16 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasGDS (const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler)
unsigned llvm::AMDGPU::getMaxNumUserSGPRs (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX9_GFX10 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX8Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isNotGFX9Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10_GFX11 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX11 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX11Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX12 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX12Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isNotGFX12Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX1250 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::supportsWGP (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isNotGFX11Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isNotGFX10Plus (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10Before1030 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX10_3_GFX11 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::isGFX940 (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasMAIInsts (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasVOPD (const MCSubtargetInfo &STI)
bool llvm::AMDGPU::hasDPPSrc1SGPR (const MCSubtargetInfo &STI)
unsigned llvm::AMDGPU::hasKernargPreload (const MCSubtargetInfo &STI)
int32_t llvm::AMDGPU::getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool llvm::AMDGPU::isSGPR (MCRegister Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool llvm::AMDGPU::isHi16Reg (MCRegister Reg, const MCRegisterInfo &MRI)
MCRegister llvm::AMDGPU::getMCReg (MCRegister Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
MCRegister llvm::AMDGPU::mc2PseudoReg (MCRegister Reg)
Convert hardware register Reg to a pseudo register.
bool llvm::AMDGPU::isInlineValue (MCRegister Reg)
bool llvm::AMDGPU::isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
Get the size in bits of a register from the register class RC.
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
Get the size in bits of a register from the register class RC.
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
bool llvm::AMDGPU::isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi)
bool llvm::AMDGPU::isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi)
bool llvm::AMDGPU::isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi)
std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV216 (bool IsFloat, uint32_t Literal)
std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2I16 (uint32_t Literal)
std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2BF16 (uint32_t Literal)
std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2F16 (uint32_t Literal)
bool llvm::AMDGPU::isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType)
bool llvm::AMDGPU::isInlinableLiteralV2I16 (uint32_t Literal)
bool llvm::AMDGPU::isInlinableLiteralV2BF16 (uint32_t Literal)
bool llvm::AMDGPU::isInlinableLiteralV2F16 (uint32_t Literal)
bool llvm::AMDGPU::isValid32BitLiteral (uint64_t Val, bool IsFP64)
int64_t llvm::AMDGPU::encode32BitLiteral (int64_t Imm, OperandType Type, bool IsLit)
bool llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)
bool llvm::AMDGPU::isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)
static bool llvm::AMDGPU::hasSMEMByteOffset (const MCSubtargetInfo &ST)
bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
static bool llvm::AMDGPU::isDwordAligned (uint64_t ByteOffset)
uint64_t llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
bool llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID)
bool llvm::AMDGPU::isIntrinsicAlwaysUniform (unsigned IntrID)
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
const MCRegisterClass * llvm::AMDGPU::getVGPRPhysRegClass (MCRegister Reg, const MCRegisterInfo &MRI)
unsigned llvm::AMDGPU::getVGPREncodingMSBs (MCRegister Reg, const MCRegisterInfo &MRI)
MCRegister llvm::AMDGPU::getVGPRWithMSBs (MCRegister Reg, unsigned MSBs, const MCRegisterInfo &MRI)
If Reg is a low VGPR return a corresponding high VGPR with MSBs set.
std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > llvm::AMDGPU::getVGPRLoweringOperandTables (const MCInstrDesc &Desc)
bool llvm::AMDGPU::supportsScaleOffset (const MCInstrInfo &MII, unsigned Opcode)
bool llvm::AMDGPU::hasAny64BitVGPROperands (const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool llvm::AMDGPU::isDPALU_DPP32BitOpc (unsigned Opc)
bool llvm::AMDGPU::isDPALU_DPP (const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
unsigned llvm::AMDGPU::getLdsDwGranularity (const MCSubtargetInfo &ST)
bool llvm::AMDGPU::isPackedFP32Inst (unsigned Opc)
raw_ostream & llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S)

◆ CASE_CI_VI [1/2]

#define CASE_CI_VI ( node )

Value:

case node: \

return isCI(STI) ? node##_ci : node##_vi;

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Definition at line 2666 of file AMDGPUBaseInfo.cpp.

◆ CASE_CI_VI [2/2]

#define CASE_CI_VI ( node )

◆ CASE_GFXPRE11_GFX11PLUS [1/2]

#define CASE_GFXPRE11_GFX11PLUS ( node )

Value:

case node: \

return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;

Definition at line 2675 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS [2/2]

#define CASE_GFXPRE11_GFX11PLUS ( node )

Value:

case node##_gfx11plus: \

case node##_gfxpre11: \

return node;

Definition at line 2675 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS_TO [1/2]

#define CASE_GFXPRE11_GFX11PLUS_TO ( node,
result )

Value:

case node: \

return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;

Definition at line 2679 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS_TO [2/2]

#define CASE_GFXPRE11_GFX11PLUS_TO ( node,
result )

◆ CASE_VI_GFX9PLUS [1/2]

#define CASE_VI_GFX9PLUS ( node )

Value:

case node: \

return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;

Definition at line 2671 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [2/2]

#define CASE_VI_GFX9PLUS ( node )

Value:

case node##_vi: \

case node##_gfx9plus: \

return node;

Definition at line 2671 of file AMDGPUBaseInfo.cpp.

◆ GET_FP4FP8DstByteSelTable_DECL

#define GET_FP4FP8DstByteSelTable_DECL

◆ GET_FP4FP8DstByteSelTable_IMPL

#define GET_FP4FP8DstByteSelTable_IMPL

◆ GET_getMFMA_F8F6F4_WithSize_DECL

#define GET_getMFMA_F8F6F4_WithSize_DECL

◆ GET_getMFMA_F8F6F4_WithSize_IMPL

#define GET_getMFMA_F8F6F4_WithSize_IMPL

◆ GET_Gfx10BufferFormat_IMPL

#define GET_Gfx10BufferFormat_IMPL

◆ GET_Gfx11PlusBufferFormat_IMPL

#define GET_Gfx11PlusBufferFormat_IMPL

◆ GET_Gfx9BufferFormat_IMPL

#define GET_Gfx9BufferFormat_IMPL

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

◆ GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL

#define GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL

◆ GET_isMFMA_F8F6F4Table_IMPL

#define GET_isMFMA_F8F6F4Table_IMPL

◆ GET_MAIInstInfoTable_IMPL

#define GET_MAIInstInfoTable_IMPL

◆ GET_MIMGBaseOpcodesTable_IMPL

#define GET_MIMGBaseOpcodesTable_IMPL

◆ GET_MIMGBiasMappingTable_IMPL

#define GET_MIMGBiasMappingTable_IMPL

◆ GET_MIMGDimInfoTable_IMPL

#define GET_MIMGDimInfoTable_IMPL

◆ GET_MIMGG16MappingTable_IMPL

#define GET_MIMGG16MappingTable_IMPL

◆ GET_MIMGInfoTable_IMPL

#define GET_MIMGInfoTable_IMPL

◆ GET_MIMGLZMappingTable_IMPL

#define GET_MIMGLZMappingTable_IMPL

◆ GET_MIMGMIPMappingTable_IMPL

#define GET_MIMGMIPMappingTable_IMPL

◆ GET_MIMGOffsetMappingTable_IMPL

#define GET_MIMGOffsetMappingTable_IMPL

◆ GET_MTBUFInfoTable_DECL

#define GET_MTBUFInfoTable_DECL

◆ GET_MTBUFInfoTable_IMPL

#define GET_MTBUFInfoTable_IMPL

◆ GET_MUBUFInfoTable_DECL

#define GET_MUBUFInfoTable_DECL

◆ GET_MUBUFInfoTable_IMPL

#define GET_MUBUFInfoTable_IMPL

◆ GET_SMInfoTable_DECL

#define GET_SMInfoTable_DECL

◆ GET_SMInfoTable_IMPL

#define GET_SMInfoTable_IMPL

◆ GET_SourcesOfDivergence_IMPL

#define GET_SourcesOfDivergence_IMPL

◆ GET_True16D16Table_IMPL

#define GET_True16D16Table_IMPL

◆ GET_UniformIntrinsics_IMPL

#define GET_UniformIntrinsics_IMPL

◆ GET_VOP1InfoTable_DECL

#define GET_VOP1InfoTable_DECL

◆ GET_VOP1InfoTable_IMPL

#define GET_VOP1InfoTable_IMPL

◆ GET_VOP2InfoTable_DECL

#define GET_VOP2InfoTable_DECL

◆ GET_VOP2InfoTable_IMPL

#define GET_VOP2InfoTable_IMPL

◆ GET_VOP3CAsmOnlyInfoTable_DECL

#define GET_VOP3CAsmOnlyInfoTable_DECL

◆ GET_VOP3CAsmOnlyInfoTable_IMPL

#define GET_VOP3CAsmOnlyInfoTable_IMPL

◆ GET_VOP3InfoTable_DECL

#define GET_VOP3InfoTable_DECL

◆ GET_VOP3InfoTable_IMPL

#define GET_VOP3InfoTable_IMPL

◆ GET_VOPC64DPP8Table_DECL

#define GET_VOPC64DPP8Table_DECL

◆ GET_VOPC64DPP8Table_IMPL

#define GET_VOPC64DPP8Table_IMPL

◆ GET_VOPC64DPPTable_DECL

#define GET_VOPC64DPPTable_DECL

◆ GET_VOPC64DPPTable_IMPL

#define GET_VOPC64DPPTable_IMPL

◆ GET_VOPCAsmOnlyInfoTable_DECL

#define GET_VOPCAsmOnlyInfoTable_DECL

◆ GET_VOPCAsmOnlyInfoTable_IMPL

#define GET_VOPCAsmOnlyInfoTable_IMPL

◆ GET_VOPDComponentTable_DECL

#define GET_VOPDComponentTable_DECL

◆ GET_VOPDComponentTable_IMPL

#define GET_VOPDComponentTable_IMPL

◆ GET_VOPDPairs_DECL

#define GET_VOPDPairs_DECL

◆ GET_VOPDPairs_IMPL

#define GET_VOPDPairs_IMPL

◆ GET_VOPTrue16Table_DECL

#define GET_VOPTrue16Table_DECL

◆ GET_VOPTrue16Table_IMPL

#define GET_VOPTrue16Table_IMPL

◆ GET_WMMAInstInfoTable_IMPL

#define GET_WMMAInstInfoTable_IMPL

◆ GET_WMMAOpcode2AddrMappingTable_DECL

#define GET_WMMAOpcode2AddrMappingTable_DECL

◆ GET_WMMAOpcode2AddrMappingTable_IMPL

#define GET_WMMAOpcode2AddrMappingTable_IMPL

◆ GET_WMMAOpcode3AddrMappingTable_DECL

#define GET_WMMAOpcode3AddrMappingTable_DECL

◆ GET_WMMAOpcode3AddrMappingTable_IMPL

#define GET_WMMAOpcode3AddrMappingTable_IMPL

◆ MAP_REG2REG

◆ DefaultAMDHSACodeObjectVersion